WO2010094511A3 - Bauteilanordnung und verfahren zu dessen herstellung - Google Patents

Bauteilanordnung und verfahren zu dessen herstellung Download PDF

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Publication number
WO2010094511A3
WO2010094511A3 PCT/EP2010/001211 EP2010001211W WO2010094511A3 WO 2010094511 A3 WO2010094511 A3 WO 2010094511A3 EP 2010001211 W EP2010001211 W EP 2010001211W WO 2010094511 A3 WO2010094511 A3 WO 2010094511A3
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WO
WIPO (PCT)
Prior art keywords
substrate
contact
protective layer
elements
component arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2010/001211
Other languages
English (en)
French (fr)
Other versions
WO2010094511A2 (de
Inventor
Hans-Hermann Oppermann
Matthias Klein
Michael Töpper
Jürgen Wolf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority to US13/138,440 priority Critical patent/US8564969B2/en
Priority to DE112010000715.2T priority patent/DE112010000715B4/de
Publication of WO2010094511A2 publication Critical patent/WO2010094511A2/de
Publication of WO2010094511A3 publication Critical patent/WO2010094511A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H10W72/07233—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/332—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H10W72/348—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Landscapes

  • Wire Bonding (AREA)
  • Manufacture Of Switches (AREA)

Abstract

Gegenstand der Erfindung ist eine Bauteilanordnung mit einem ersten Substrat und mindestens einem auf dem ersten Substrat angeordneten zweiten Substrat, wobei das erste Substrat mindestens ein erstes Kontaktelement und das mindestens eine zweite Substrat mindestens ein zweites Kontaktelement aufweist und die Kontaktelemente jeweils eine Kontaktfläche besitzen, welche zu jeweils einer elektrischen Kontaktierung verbunden sind und eine Stützschicht das erste Substrat und das mindestens eine zweite Substrat miteinander verbindet. Dabei wird während der Herstellung die Stützschicht derart strukturiert, dass eine Teilfläche des ersten Substrats und eine Teilfläche des mindestens einen zweiten Substrats nicht überdeckt sind, wobei die Teilfläche die jeweilige Kontaktfläche des mindestens einen ersten und zweiten Kontaktelements umschließt und die zwischen den Kontakt flächen hergestellte Kontaktierung somit nicht durch die Stützschicht verunreinigt ist. Die Kontaktflächen sind somit einander frei zugänglich, ohne dass Elemente der Stützschicht dazwischen liegen. Hierdurch wird eine verbesserte elektrische Leitfähigkeit bei gleich bleibender mechanischer Stabilität erzeugt.
PCT/EP2010/001211 2009-02-19 2010-02-19 Bauteilanordnung und verfahren zu dessen herstellung Ceased WO2010094511A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/138,440 US8564969B2 (en) 2009-02-19 2010-02-19 Component arrangement and method for production thereof
DE112010000715.2T DE112010000715B4 (de) 2009-02-19 2010-02-19 Bauteilanordnung und Verfahren zu dessen Herstellung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009009828A DE102009009828A1 (de) 2009-02-19 2009-02-19 Bauteilanordnung und Verfahren zu dessen Herstellung
DE102009009828.3 2009-02-19

Publications (2)

Publication Number Publication Date
WO2010094511A2 WO2010094511A2 (de) 2010-08-26
WO2010094511A3 true WO2010094511A3 (de) 2010-10-14

Family

ID=42224316

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2010/001211 Ceased WO2010094511A2 (de) 2009-02-19 2010-02-19 Bauteilanordnung und verfahren zu dessen herstellung

Country Status (3)

Country Link
US (1) US8564969B2 (de)
DE (2) DE102009009828A1 (de)
WO (1) WO2010094511A2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5807221B2 (ja) 2010-06-28 2015-11-10 アユミ工業株式会社 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム
FR2969374B1 (fr) * 2010-12-16 2013-07-19 St Microelectronics Crolles 2 Procédé d'assemblage de deux circuits intégrés et structure correspondante
DE102011000866A1 (de) 2011-02-22 2012-08-23 Friedrich-Alexander-Universität Erlangen-Nürnberg Elektrisches Bauelement mit einer elektrischen Verbindungsanordnung und Verfahren zu dessen Herstellung
DE102014201635B3 (de) * 2014-01-30 2015-05-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Anordnung von elektronischen Bauelementen und elektronische Schaltanordnung
DE102014211545A1 (de) * 2014-06-17 2015-12-17 Continental Automotive Gmbh Verfahren zur Montage eines ungehäusten Halbleiterchips auf einem Substrat
TWI606565B (zh) * 2016-08-31 2017-11-21 金寶電子工業股份有限公司 封裝結構及其製作方法
DE102018103431A1 (de) * 2018-02-15 2019-08-22 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Verbindung zwischen Bauteilen und Bauelement aus Bauteilen
DE102018104279B4 (de) 2018-02-26 2025-02-06 Tdk Corporation Elektronische Vorrichtung
DE102019111816A1 (de) 2019-05-07 2020-11-12 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur herstellung eines bauelements und bauelement
DE102019130209B4 (de) 2019-11-08 2025-10-30 Tdk Corporation Elektronische Vorrichtung und Verfahren zur Herstellung einer elektronischen Vorrichtung
DE102020202613A1 (de) 2020-03-02 2021-09-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur herstellung eines halbleiterbauelements, halbleiterbauelement und optoelektronische vorrichtung
EP4318567A4 (de) * 2021-03-30 2024-10-09 Mitsui Mining & Smelting Co., Ltd. Herstellungsverfahren für mehrschichtiges substrat und verdrahtungssubstrat
DE102024116246A1 (de) * 2024-06-11 2025-12-11 Rolls-Royce Deutschland Ltd & Co Kg Verfahren zum Herstellen einer Leiterplattenanordnung

Citations (4)

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US6239383B1 (en) * 1998-09-05 2001-05-29 Via Technologies, Inc. Ball-grid array IC packaging frame
US20050285152A1 (en) * 2004-06-25 2005-12-29 Harry Hedler Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
US20070145553A1 (en) * 2005-12-22 2007-06-28 Shinko Electric Industries Co., Ltd. Flip-chip mounting substrate and flip-chip mounting method
DE102006045094A1 (de) * 2006-09-21 2008-03-27 Qimonda Ag Verfahren zum Herstellen von Chip-zu-Chip-Verbindungen

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JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US7098073B1 (en) * 2005-04-18 2006-08-29 Freescale Semiconductor, Inc. Method for stacking an integrated circuit on another integrated circuit
EP1732116B1 (de) 2005-06-08 2017-02-01 Imec Methode zum Bonden mikroelektronischer Bauteile und damit hergestellte Vorrichtung
DE102006020869A1 (de) * 2006-05-04 2007-11-08 Infineon Technologies Ag Verfahren zur Stapelung von Halbleiterchips und durch das Verfahren hergestellter Halbleiterchipstapel
US7824960B2 (en) * 2007-05-22 2010-11-02 United Test And Assembly Center Ltd. Method of assembling a silicon stack semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239383B1 (en) * 1998-09-05 2001-05-29 Via Technologies, Inc. Ball-grid array IC packaging frame
US20050285152A1 (en) * 2004-06-25 2005-12-29 Harry Hedler Method for connecting an integrated circuit to a substrate and corresponding circuit arrangement
US20070145553A1 (en) * 2005-12-22 2007-06-28 Shinko Electric Industries Co., Ltd. Flip-chip mounting substrate and flip-chip mounting method
DE102006045094A1 (de) * 2006-09-21 2008-03-27 Qimonda Ag Verfahren zum Herstellen von Chip-zu-Chip-Verbindungen

Also Published As

Publication number Publication date
DE102009009828A1 (de) 2010-09-02
US20120039056A1 (en) 2012-02-16
DE112010000715A5 (de) 2012-06-21
US8564969B2 (en) 2013-10-22
DE112010000715B4 (de) 2021-08-19
WO2010094511A2 (de) 2010-08-26

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