WO2012102785A2 - Cellule de mémoire à mécanismes de lecture multiples - Google Patents

Cellule de mémoire à mécanismes de lecture multiples Download PDF

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Publication number
WO2012102785A2
WO2012102785A2 PCT/US2011/063416 US2011063416W WO2012102785A2 WO 2012102785 A2 WO2012102785 A2 WO 2012102785A2 US 2011063416 W US2011063416 W US 2011063416W WO 2012102785 A2 WO2012102785 A2 WO 2012102785A2
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Prior art keywords
memory cell
sense
voltage
memory
memory device
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WO2012102785A3 (fr
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Yoshihito Koya
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Rambus Inc
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Rambus Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Definitions

  • flash memory Many forms of nonvolatile memory, among them flash memory, rely on substances that can be switched between different stable states.
  • charge is selectively stored via a "programming,” “write” or “set” operation on an isolated “floating gate” or “charge trap region,” and this charge influences the extent to which current can flow through a substrate via a process known as “Fowler-Nordheim” (FN) tunneling.
  • FN Low-Nordheim
  • the charge can also be removed from the floating gate via an “erase” or “reset” operation. Whether a particular memory cell is “programmed” (or equivalently, “set”) or erased (or equivalently, “reset”) indicates the information stored in the memory cell.
  • the sensing of memory cell contents becomes relatively more complex in the case of multilevel memory cells, that is, where more than one tier of stored information is used in each individual cell.
  • certain flash memory cells can store either of two states in a floating gate, meaning that four different current flows (or sensed voltages) are possible.
  • the determination of information stored on each multilevel memory cell can be performed in two basic ways, that is, in an analog manner (e.g.
  • the cell is turned “on” and a measured current flow is sensed and compared to a number of thresholds), as well as in a digital manner (wordline voltage is applied representing a discrimination between states, with the cell either being turned “on” or “off” relative to the wordline voltage depending on cell state); a Boolean determination is then made regarding the current or voltage seen on the cell's bitline - for example, three different operations might be performed to distinguish four possible cell levels, each process producing a Boolean result).
  • the analog process is faster, but involves greater power consumption and has greater susceptibility to noise, while the digital process is slower (that is, it takes relatively longer for a steady bitline voltage to be obtained and to ascertain the specific state of each memory cell).
  • PV cycle program-verify
  • nonvolatile memory Although known by a variety of names, many forms of nonvolatile memory rely on analogous set, reset and read processes, that is, where a substance (e.g., the floating gate in the case of flash memory) is controlled to assume a state which will persist for a period of time, and where that state is subsequently electrically sensed in a "read operation,” usually by detecting current flow dependent on the state of the substance; resistive random access memory (RRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), nanowire RAM, silicon-oxide-nitride-oxide-silicon RAM (SONOS) all operate based on similar state change principles, although the principles of what causes the state change differ from case to case.
  • RRAM resistive random access memory
  • MRAM magnetic random access memory
  • PCRAM phase change random access memory
  • SONOS silicon-oxide-nitride-oxide-silicon RAM
  • flash memory remains one of the most common of these forms mostly because the technology is reliable, inexpensive and relatively mature.
  • designers may be forced to rely increasingly on multilevel cell designs, and to choose between inconsistent goals of performance and power minimization.
  • the present invention satisfies these needs and provides further, related advantages.
  • FIG. 1 provides an illustration of one embodiment of a memory device with multisense technology.
  • FIG. 2A provides an illustration of another embodiment of a memory device with multisense technology; as depicted, one sense methodology is analog in nature while a second sense methodology is digital in nature, with either method being selectively employed (e.g., in the alternative).
  • FIG. 2B provides an illustration of yet another embodiment of a memory device; this embodiment is similar to the embodiment seen in FIG. 2A, but employs circuitry configurable to support multiple, alternate sense methodologies. If desired, the multiple sense methodologies may be analog and digital, respectively, as was the case for the embodiment of FIG. 2A.
  • FIG. 3 provides a method block diagram for a multisense memory technology where (for example) analog or digital sense techniques are again used as the two different multisense technologies; as depicted by optional (dashed-line) blocks, a number of contemplated implementation options exist.
  • FIG. 4 shows a cross-sectional view of a "decapped" memory cell string.
  • FIG. 5 provides a schematic view of a memory device where memory cells are controlled using wordlines (WL), bitlines (BL), a source voltage (SRC) and a sense amplifier SA for each bitline.
  • WL wordlines
  • BL bitlines
  • SRC source voltage
  • SA sense amplifier
  • FIG. 6 shows provides a voltage state diagram, used to explain operation of a multilevel memory cell.
  • FIG. 7 provides a block diagram illustrating configuration of a specific memory device for either analog or digital sensing.
  • FIG. 8 shows a schematic for one exemplary voltage-mode analog sense circuit.
  • FIG. 9 provides a waveform diagram used to explain operation of the circuit of FIG. 8.
  • FIG. 10 provides a block diagram showing the use of multiple analog sense circuits to read a multilevel cell.
  • FIG. 1 1 graphs exemplary voltages that might be seen using an analog methodology to sense state of a multilevel cell.
  • FIG. 12 provides a schematic for one exemplary voltage-mode digital sense circuit.
  • FIG. 13 provides a waveform diagram used to explain operation of the circuit of FIG. 12.
  • FIG. 14 provides a schematic for one exemplary current-mode digital sense circuit.
  • FIG. 15 provides a waveform diagram used to explain operation of the circuit of FIG. 14.
  • FIG. 16 shows one example of a reconfigurable circuit, that is, a circuit configured through appropriate signal control to be either the circuit of FIG. 8 or the circuit of FIG. 14.
  • FIG. 17 provides a high level block diagram of an exemplary flash memory device.
  • FIG. 18 shows flow for a method where digital sense methodology is used for nonvolatile program-verify (PV) operation, while analog sense methodology is used for nonvolatile read operations.
  • PV program-verify
  • FIG. 19 provides a high level circuit diagram use to exemplify control logic (e.g., hardware) used in the circuit seen in FIG. 17.
  • control logic e.g., hardware
  • This disclosure provides a memory device having multiple, alternate sense methodologies.
  • digital sensing can be used when it is desired to minimize power consumption
  • analog sensing can be used when it is desired to maximize performance (i.e., provide relatively quick read operation).
  • type of sensing used is dynamically selective; also optionally, each form of the sensing can be invoked depending on specific type of memory operation. Examples of these operations and associated circuits and other structures are given below.
  • each of an analog sense circuit and a digital sense circuit is provided in a memory device.
  • each of the analog sense circuit and the digital sense circuit can be employed on a selective basis in dependence upon programming, for example, dependent upon contents of a programmable register, a fuse fixed at time of manufacture, or via another operation. This selection is optionally made on a one time basis (e.g., configuring a memory circuit to thereafter apply a chosen sense methodology) or is dynamic, to support run-time reprogramming by a remote memory controller or application for example.
  • Logic sufficient to implement this function for example, register, fuse or other circuit or operation, provides means for defining a mode of the memory device, where the mode indicates whether each sense mechanism is invoked in a particular context.
  • an analog sense methodology or a digital sense methodology is predefined to circumstance that is, either invoked according to a programmed value or according to a set preference dependent on run-time use.
  • a flash memory device "always" employs a digital sense circuit during individual programming (e.g., PV cycle) operations to "verify" cell contents; for flash devices, the multiple PV cycles typically required imply a relatively long latency irrespective of sense methodology, such that a digital sense mechanism would create little to no additional latency penalty, but would provide significant reliability and power savings.
  • an analog sense circuit is beneficially used during "pure” read operations, as a single read would present minimal power penalties, but provides significantly enhanced read performance (that is, faster speed in retrieving memory contents relative to digital sensing).
  • FIGS. 1 -3 certain multisense memory devices will be introduced.
  • FIGS. 4-7 will be used to explain the application of multisense methodology to flash memory, specifically, to NAND flash memory integrated circuits. As mentioned earlier, the principles of this disclosure are not limited to flash devices and are also applicable to any other form of memory, including potentially volatile and other forms of nonvolatile memory devices.
  • Third, specific circuits and architectures will be presented which make use of multisense methodologies, with reference to FIGS. 8-16.
  • FIGS. 17-19 certain specific applications will be discussed. Introduction.
  • FIG. 1 provides one embodiment of a memory system 101 that uses at least one multilevel cell 105, a first sense methodology 107, and a second sense methodology 109, each of which can be used to derive sensed data 1 1 1 from the multilevel memory cell.
  • methodology in this context, it is meant that two different processes or circuits, each capable on its own of sensing cell state, are invoked either in the alternative, or cumulative to each other, within a memory device; without limiting the foregoing, alternative sense methodologies can include two different sense circuits or sets of operations to determine cell contents.
  • the two methodologies are analog and digital, respectively, but it is also possible to use two different analog circuits or processes, two different digital circuits or processes, respective current-mode and voltage-mode circuits or processes, more than two processes or methodologies, or some other scheme.
  • analog and digital represent the respective methodologies in a two-methodology scheme.
  • each of these components is optionally integrated on one memory device, such as a memory drive, memory module, memory integrated circuit (IC), a system on-chip or system in- package, or a single memory die.
  • each of these components is implemented on a single flash memory die, such that dashed-line 103 can be seen to represent a single flash memory die or IC.
  • FIGS. 2A and 2B illustrate two alternative implementations for the memory system just introduced.
  • FIG. 2A shows an implementation 201 with distinct analog and digital sense circuits 207 and 209, respectively, where either one of the distinct circuits is selectively invoked or invoked under specific circumstances, as schematically represented by the presence of a switch 206.
  • the switch couples a bitline 210 from a memory cell 205 to one of the distinct sense circuits 207 or 209.
  • a particular one of these circuits can be invoked depending on circumstance (e.g., depending on operation type or context), or the choice can be selective, for example, as defined by a specific command or responsive to a selected one of several modes.
  • the applied sense circuit 207 or 209 provides sensed data 21 1 as an output representing memory cell contents, with all components optionally collocated to form a single device 203.
  • FIG. 2B shows another embodiment 251 having a single sense circuit 257 that is configured to act as a desired one of two or more alternate sense methodologies, for example, under governance by configuration logic 259.
  • the single sense circuit 257 can be configured as an analog sense circuit or configured as a digital sense circuit; for embodiments that support reconfigurability, the single sense circuit 257 can be configured as an analog sense circuit and then reconfigured as a digital sense circuit, or vice-versa.
  • the various components are optionally embodied as part of a single device 253 having at least one multilevel memory cell 255, a bitline 256 that is measured by the sense circuit to determine cell contents, and some form of output or signal representing sensed data 261 .
  • both sense methodologies e.g., analog and digital
  • both sense methodologies may be concurrently used, either for the same memory cell or for different memory cells, or for the same task or different tasks.
  • the embodiments depicted by FIGS. 2A and 2B involve dedicated and shared circuitry respectively, but in many practical embodiments including some presented below, certain circuits will be shared by the alternate sense methodologies while other circuits are dedicated to one sense methodology or the other.
  • FIG. 3 illustrates methodology 301 based on the principles introduced above.
  • dashed-line blocks represent optional process blocks.
  • the type of sense methodology used optionally depends on mode or context, as indicated by a first dash-line block 303.
  • this mode or context can be determined by reference to a register, as indicated by dashed-line block 305, or in connection with a particular command, per dashed-line block 307.
  • a register can be collocated with the memory device, for example, on a common chip or via a serial presence detect (SPD) register present on a memory module.
  • SPD serial presence detect
  • one type of command may invoke an operation that relies on a first, analog sense methodology, while a different type of command may invoke the very same type of operation, but in a manner that relies on a second, digital sense methodology.
  • the type of sense methodology used can be made to be dependent upon operation or transaction type, per block 309.
  • the previously alluded-to flash memory embodiment that uses analog sensing for read transactions and digital sensing for programming transactions exemplifies this type of process; an inbound command is determined to be a program command or a read command 31 1 or 313, and the appropriate methodology is responsively selected, per process block 315.
  • Sensed data is thereafter decoded, per process block 317, and responsively provided to a write data buffer or an IO buffer 319 or 321 , respectively.
  • Usage of each of these types of buffers has a connotation generally associated with flash memory, and is therefore indicated in FIG. 3 as optional; the use of these buffers will be further explained below in the context of flash memory implementation.
  • a typical flash memory device has millions of flash memory cells, arranged at intersections of a matrix of thousands of wordlines and thousands of bitlines; typically, a single memory cell exists at each unique wordline/bitline intersection.
  • cells are further organized as "strings" that are controlled in unison to program, erase and read contents of any particular memory cell.
  • a conventional flash memory device might have 16-128 memory cells per string (usually a power of two), with a wordline for each memory cell in a string; thus, there would in this example typically be 16-128 wordlines that cross each string.
  • Each wordline is typically used to program an entire "page" at once (i.e., one cell in every string crossed by the wordline); since there are typically tens of thousands of cells accessed by each wordline (e.g., 32,768), page size would in this hypothetical typically consist of 32,768 bits.
  • the array structure typically erases NAND flash memory in units of "blocks" with a block consisting of all cells in each parallel string that is crossed by a given set of wordlines (e.g., with 32 cells per string, and 32,768 strings per wordline, there would be approximately a million bits per block, or about 128 kilobytes per block.
  • these numbers are illustrative only and are not meant to represent any specific device, but to convey “typical” values.
  • Each bitline in turn might be used to selectively access hundreds to thousands of strings (or blocks).
  • FIG. 4 provides a cross-sectional illustration of a single string 401 .
  • a flash memory device embodying the principles of this disclosure might have many thousands of such strings, with a sense amplifier (digital and/or analog) for each bitline or string, and with shared control circuitry and buffers to support programming, erasing and read operations.
  • the structure seen in FIG. 4 includes a substrate 403 and a group of memory cells 405, 407 and 409, which are part of a NAND flash memory cell string.
  • each string effectively forms a structure that permits some amount of current flow through a "channel" formed within the substrate from a first access transistor 41 1 to a second access transistor 413, dependent on collective cell content and control over the cells.
  • each cell is selectively turned “on” irrespective of contents (via control of the associated wordline), and each cell is selectively caused (also by control of the associated wordline) to variably influence substrate conductance adjacent that cell, dependent on cell contents.
  • each cell is selectively turned “on” irrespective of contents (via control of the associated wordline), and each cell is selectively caused (also by control of the associated wordline) to variably influence substrate conductance adjacent that cell, dependent on cell contents.
  • the first access transistor 41 1 effectively couples the bitline to the channel (i.e., to the substrate) through a bitline contact 415 to gate the flow of charge into or out of the substrate (that is, the substrate channel), while the second access transistor 413 selectively couples the channel to a source line (e.g., specific voltage such as ground for read and verify operations), through source line ("SL") contact 417.
  • a source line e.g., specific voltage such as ground for read and verify operations
  • SL source line
  • Each memory cell e.g., for cell 409 is effectively itself also a double transistor structure with a respective control gate 419 controlling whether the transistor is conducting, dependent on the amount of charge stored on associated floating gate 421 (which sets the effective threshold voltage of the memory cells 405, 407, and 409).
  • control gate 419 for each cell in the depicted string is coupled to a unique wordline (which effectively runs into and out of the page in FIG. 4).
  • a unique wordline which effectively runs into and out of the page in FIG. 4.
  • the specific cell and the substrate are collectively controlled in a manner that isolates charge on the floating gate for the associated cell, such that charge can be retained even in the absence of an active power supply.
  • the floating gate 421 stores up to two bits of information, with the pages of memory organized such that each stored bit represents a different page (i.e., each 2- level cell stores two bits, one each for each of two different pages).
  • the operation of the string depicted in FIG. 4 is explained with reference to three landmarks used for operations involving each memory cell.
  • the three landmarks include (1 ) the substrate (which is controlled via the two access transistors 41 1 , 413 and a mechanism to selectively charge the substrate, e.g., for a block erase), (2) the floating gate for the specific cell (e.g., gate 421 for memory cell 409), and (3) the control gate 419 for the specific cell (e.g., cell 409).
  • a current is caused to flow (as indicated by dashed-line arrow 425) between the associated control gate and the substrate, to either store charge within the floating gate or remove charge from the floating gate, with the stored charge indicating the logic state of the cell.
  • applying a first polarity voltage difference causes electrons to tunnel to the floating gate and become isolated on that gate to program a single bit (e.g., by applying a positive voltage to the control gate with a grounded substrate).
  • voltage opposite in polarity charge is effectively removed from the floating gate, to thereby erase (or "reset") the cell.
  • the second access transistor 41 3 would typically be turned “off” (i.e., at point "C") for each string along a wordline that will be the subject of programming (i.e., for an entire page at once, such as for 32,768 strings at once).
  • the gate of the first access transistor for each string e.g., transistor 41 1 in FIG. 4
  • a positive voltage e.g. " V dd ”
  • bitline contact 41 5 Each bitline contact in turn will be either connected to a positive voltage (e.g.
  • V dd if programming is to be inhibited for that string (i.e., the pertinent cell is to be left un-programmed, e.g., as a logic "0") or to ground if the memory cells within the string are to be programmed (or "set", e.g., to a logic "1 "). Setting a bitline to a high voltage effectively turns “off” the access transistor and isolates the channel transistors associated with that bitline string from ground. At this time, the wordline representing a page of memory to be programmed (e.g. one bit of which is represented by cell 409) is raised to a programming voltage. In FIG.
  • this programming voltage would be applied to the memory cell 409 at point "A” (the rightmost of the three control gates 419), which causes charge to flow between the substrate and the respective floating gate (as indicated by arrow 425) and thereby charges that floating gate (if the associated bitline is coupled to ground at point "B").
  • the charging of the respective floating gate 421 is substantially suppressed, typically by a factor of 1 00 to 1 000.
  • a multilevel cell such as cells 405, 407 or 409 of FIG.
  • each bit stored in a given floating gate typically represents a different logical page, with one page represented by a least significant bit (LSB) for each cell, and a second page represented by a most significant bit (MSB) ; programming is usually effectuated using different programming voltages or duration specific to whether the MSB or LSB is being programmed.
  • the extent of tunneling that need to occur in order to program each associated floating gate is a function of the gap that separates the associated floating gate from the channel, represented by numeral 433 in FIG. 4.
  • each bitline has its own dedicated sense amplifier (not shown in FIG. 4) which then senses the state of the bitline.
  • the "unselected" wordlines for the string are raised to a relatively high state " V pa ss” to force the associated memory cells to an "on” condition, irrespective of the memory cell contents (e.g., for 32,768 affected strings).
  • V pa ss a relatively high state
  • voltage is raised to a read level " Vread” which allows current flow (represented by arrow 427) only if the associated floating gate voltage is at a higher potential than the associated control gate 419 (i.e., higher than V read ) ; the cell otherwise remains in an "off” condition and no substantial tunneling occurs.
  • the read voltage is specifically selected to trigger tunneling dependent on the possible states of the cell, e.g., such that each state is separately tested for or such that specific states are discriminated.
  • analog and digital read techniques can be used depending on desired application and effect.
  • An analog read mechanism typically uses a 1 ⁇ 2 eaci that is relatively high, as well as a sense amplifier capable of measuring variable current or voltage in the bitline, to compare analog current flows or voltages with multiple thresholds in order to determine cell state; the discrimination of state is performed relatively "close to" the sense amplifier.
  • a digital read mechanism typically uses a specially selected eaci from among multiple choices to effectively discriminate between states at the memory cell, and then current flow through the associated channel (i.e., for each string) is either determined to occur or to not occur.
  • FIG. 5 presents a schematic view 501 of an entire block, that is, a structure having multiple strings, bitlines and associated sense amplifiers. Each string runs vertically in FIG. 5, and crosses a series of horizontal signal lines, including first access transistor and second access transistor control lines (respectively labeled “S1 " and “S2”), a source line labeled "SRC,” and a group of wordlines (with each wordline labeled "WL # ").
  • first access transistor and second access transistor control lines respectively labeled "S1 " and "S2”
  • SRC source line labeled
  • WL # group of wordlines
  • wordlines WL 0 , Wl_i and WL 2
  • wordlines 1 6-1 28 wordlines will typically be used for each block; also, while only three bitlines are illustrated (BL ; BL 2 and BL,), it should be appreciated that there typically are tens of thousands of bitlines (and associated strings) per block, e.g., with each string being a vertical "column" of transistors as depicted in FIG. 5.
  • bitlines and associated strings
  • a "first access transistor” 517 is used to selectively couple an associated string to the source line (SRC) while the associated “second access transistor” 519 is used to selectively couple the associated string to a bitline (e.g., BL-i ).
  • SRC source line
  • SRC source line
  • FIG. 6 is a voltage diagram illustrating statistical voltage distribution in a two- level flash memory cell.
  • a graph 601 presents four voltage distributions representing four possible memory cell states.
  • a first state represents an erased state ("ER"), i.e., the logical value "1 1 ;” other states, representing logical states of "10,” “01 “ and “00” are respectively designated as "A,” "B” and "C” states.
  • ER erased state
  • the graph 601 presents typical voltage distributions given differences in cell-to-cell tolerances; for example, for the "A" state, a median voltage might be 0.65V, while because of semiconductor processing differences, some cells might be programmed to have a floating gate voltage of 0.35V while others might have a voltage of 0.8V.
  • Vertical lines in FIG. 6 represent voltage thresholds used to discriminate between states, e.g., a second voltage threshold 605 for example clearly discriminates the "A” and "B” states, but does not discriminate on its own either the "C” state from the "B” state nor does it discriminate the "A” state from the "ER” state.
  • three sense operations having respective voltage thresholds represented by vertical lines 603, 605 and 607 in FIG. 6, might be used.
  • the programming voltage is then removed and the cell contents tested to determine whether the cell has reached the appropriate state; this operation completes one PV cycle.
  • an entire page is typically programmed at once (for NAND flash memory, e.g., 32,768 or a greater number of bits at once) - in typical operation, not all floating gates will assume their intended state on the first programming attempt, and so, those that fail the first time are tried a second time, via a discrete PV cycle, and so on.
  • a typical flash memory device might allow for 20 or more PV cycles for the correct programming of an entire page, with a large, associated latency typically on the order of a microsecond to a millisecond.
  • the system is designed such that a memory controller initiates a programming operation for a page, and then "checks back" with the memory device after a predetermined latency period (e.g., to read a status register to determine whether the memory device is done).
  • a predetermined latency period e.g., to read a status register to determine whether the memory device is done.
  • FIG. 7 provides a flow diagram 701 for one implementation of multisense technology in connection with the flash memory principles just introduced. While this example is rooted in the analog/digital sense examples introduced earlier, it should be understood that these principles can be applied to other types of multisense technology, as well as to other forms of "analog” and "digital" sensing.
  • a decision block 703 it is first determined whether an analog or digital sense methodology is to be applied, with a particular path 705 or 707 selected in response to this determination.
  • This selection of the ensuing path is invoked by means of any suitable logic, whether hardware or software, which is capable of varying the sense methodology, for example, logic that controls a reconfigurable circuit to a selective one of multiple sense methodologies, logic that controls a switch to electrically couple one of several, alternate sense methodologies, logic that sets various thresholds so as to affect sensing determination, logic that defines the states or values of electrical control signals that empower or depower electrical components, or any other mechanism for selecting amongst multiple sense methodologies.
  • the first, leftmost path 705 in FIG. 7 represents the digital sense path.
  • This path calls for placing a specific sense voltage on a "selected" wordline where the sense voltage is tailored to a specific state or states that are to be discriminated from other states.
  • box 709 speaks of setting a "selected" wordline to a specific threshold voltage (the selected wordline represents the page being read, which is page "j" using the terminology of FIG. 7).
  • a sense amplifier for a string crossed by the "selected" wordline (following a bitline pre-charge) determines whether current flows in the associated bitline.
  • This process might then be repeated 2"- 1 times for a read operation, each time with a different voltage threshold, as represented by box 71 3 and feedback loop 71 5.
  • “n" represents the number of levels or tiers associated with the cell, e.g., 3 sensing passes would be used for a 2-level cell.
  • a Boolean result is returned each time (e.g., with a determination that current either flows or does not flow for a current-mode sense amplifier, or equivalently, a determination that a sensed voltage either does or does not exceed a threshold). For example, returning to FIG.
  • a wordline may be successively set to three different voltage thresholds and used to discriminate (1 ) states “ER” and “A” from states “B” and “C", (2) state “ER” from state “A” and (3) state “B” from state “C;” other methodologies are also possible. It should be appreciated that for a PV cycle operation, only one pass might be necessary dependent on design, to determine whether a memory cell in question has been sufficiently programmed (to the desired state). Because the voltage thresholds in this "digital” example are applied at the wordline, and relatively “far” from the sense amplifier, this process represents a relatively long process, but is reliable (current either flows or does not) and consumes relatively little power. When sufficient passes have been made to identify cell state, the method is finished, per block 71 7.
  • any electrical circuitry or logic effective to implement these functions can be used, including some conventional circuit designs; this circuitry or logic provides means for determining a bit of information representing content of a single level of the cell. That is to say, using circuitry or logic, a current or voltage can be obtained that, relative to wordline voltage, represents the content of a single bit of information stored in a specific level of the multilevel cell.
  • the second, rightmost path 707 represents the analog sense path.
  • This path calls for application of a single wordline voltage with comparison of bitline voltage or current flow against one or more thresholds; because this discrimination is "close to" the bitline, and can facilitate comparison of the result of one sense operation result against multiple thresholds, the sense operation it is relatively fast, but involves relatively large current swings on the bitline corresponding to various states that are to be discriminated. Accordingly, per box 71 9, the "selected" wordline is set to a single target voltage that will be used to determine cell contents.
  • the gate voltage is then measured (either using a current-mode or voltage-mode sense methodology) and compared to as many as 2"-7 different voltage thresholds in the sense amplifier (e.g., three voltage thresholds in the 2-level cell example described above). If multiple thresholds are employed, this sensing can be sequential or simultaneous; for example, bitline contents can be held and compared to different thresholds in 2"- 1 successive cycles; alternatively, 2"- 1 parallel comparison circuits can be used to simultaneously discriminate between states (e.g., the "ER,” "A,” “B” and “C” states described above). Indeed, for applications where response time is an important factor, simultaneous sensing provides latency benefits, albeit at the cost of slightly higher power consumption. These functions are represented by numerals 721 and 723 in FIG. 7.
  • any electrical circuitry or logic effective to implement these functions can be used, including some conventional circuit designs; this circuitry or logic provides means for generating a measure representing stored information for at least two levels of the cell. That is to say, using circuitry or logic, a single current or voltage can be obtained that is then compared against a reference; with sufficient threshold comparisons or part or all of this circuitry or logic duplicated for multiple thresholds, the state of each stored bit of information for the multilevel cell can be determined.
  • there is a separate sense amplifier per bitline and a wordline is activated to simultaneously read contents of an entire page at once using a bitline for each string crossed by the wordline.
  • one contemplated embodiment provides a memory device having a digital sense circuit and an analog sense circuit, either of which can be individually applied (e.g., either analog sense or digital sense or both). Such an embodiment was discussed in conjunction with FIG. 2A. While a variety of designs for a digital sense circuit or methodology and an analog sense circuit or methodology may be applied, FIGS. 8-1 5 are used to explain specific circuits for each.
  • FIG. 8 shows one exemplary analog sense circuit 801 . While a voltage-mode circuit is illustrated, a current-mode design can also be applied, if desired.
  • bitline from a cell is seen at the left-hand side of FIG. 8, labeled "BL.”
  • the cell is controlled in a manner previously described to produce a voltage on bitline "BL” representing contents of the cell. It is desired to measure this voltage, and FIG. 8 provides an "analog" sense circuit for this purpose.
  • bitline BL is first grounded (under the influence of bitline precharge control signal "BLP," which controls NMOS transistor 803); at this same time, a push- pull comparator 829 is zeroed via control signal EQ (the signal EQ controls equalizing transistor 833).
  • BLP bitline precharge control signal
  • EQ the signal EQ controls equalizing transistor 833.
  • the sense operation begins with the BLP control signal being deasserted to decouple the bitline BL from ground, allowing it to float in dependence upon cell state; the EQ signal is also deasserted at this time to allow the push-pull comparator to react to bitline voltage.
  • access transistors such as transistors 41 1 and 413 from FIG.
  • NMOS transistor 81 3 is turned “on” to transfer voltage from the source of transistor 81 3 to storage capacitor 815 and node N1 .
  • the described circuitry amplifies and transfers voltage from the bitline in a manner minimizing disturbance to the bitline BL. Once transferred to node N1 , the sensed voltage from the bitline is ready for comparison with a selected threshold.
  • FIG. 8 The right side of FIG. 8 represents circuitry that provides that threshold for comparison, and that also provides a comparison output.
  • PMOS transistors 817 and 81 9 Up until the transfer of sensed bitline voltage, PMOS transistors 817 and 81 9 are kept “on” and “off” states respectively, which places a high voltage ( V dd ) at node LAT.
  • PMOS transistor 817 is turned “off” and a reference voltage is applied to the control gate of PMOS transistor 81 9, which drops the source of transistor 81 9 to the desired threshold voltage.
  • the threshold voltage (at node LAT) is transferred to node N2 by means of transistor 821 , for storage on capacitor 823. Both the sensed bitline voltage (at node N1 ) and the selected threshold (at node N2) are at this time ready for comparison.
  • the signal "CMP" is raised high to cause both of NMOS transistors 825 and 827 to transfer the respective voltages from node N1 and node N2 to push-pull comparator 829.
  • transistor 833 turned “off,” signal SAN (and node 831 ) is slowly ramped from V ⁇ to ground, with the result that the voltage at one of nodes C1 or C2 will cause either transistor 833 or 835 to conduct first, thereby driving one of nodes C1 or C2 to V dd , (i.e., the node with the greater voltage will be driven to this state) and the other of nodes C1 or C2 to ground.
  • the voltage at node C2 will be driven to zero; if the selected threshold is greater than bitline voltage, then node C2 will be driven high.
  • the voltage at node C2 is then transferred to node LAT by once again turning transistors 821 and 827 "on,” thereby storing the result of comparison on storage capacitor 823 and making the result visible at node LAT.
  • the sensing of data using the circuit of FIG. 8 can roughly be divided into several periods, all of which are represented in FIG.
  • FIG. 1 0 shows such an implementation 1 001 , which effectively uses three different sense circuits 1 007, 1 009 and 101 1 to sense a single bitline and simultaneously compare that bitline against three different thresholds. While such an approach does add circuit overhead, as mentioned earlier, a single sense amplifier (i.e., a single circuit consisting of three duplicate sense circuits) can be shared by several bitlines and be time-multiplexed between them.
  • FIG. 10 also shows a multilevel cell 1003, a bitline 1005, and a decoder 1013; the decoder receives the results of comparison and outputs cell contents using relatively simple combinatorial logic.
  • the presented design also provides a zero current bias method to eliminate variability in source resistance due to data state of other cells in string. Specifically, it was illustrated in FIG. 9 (and also discussed in conjunction with FIG. 8) that the turning “off" of PFET 807 and NFET 809, and the delayed transfer of settled voltage by NFET transistor 813, allow the settling of voltage on the bitline BL. In this regard, as transistors 807 and 809 are turned “off,” the use of transistor 81 1 provides for minimal current flow on the bitline BL, instead relying on charge on storage capacitor 805 to hold sensed voltage.
  • FIG. 1 1 illustrates beneficial effects of this approach in a voltage versus current graph 1 101 ; in particular, as the transistors are turned “off” (e.g., assuming a cell state for a 2-level cell of "01 ,” or state “B” as referenced above), bitline voltage and current remain substantially constant despite a brief transient, with bitline voltage changing slightly from point “a” to point “b” in FIG. 1 1 , with the transient represented by arrow 1 103. Similar transients are associated with sensing the other states of a multilevel cell, as illustrated.
  • This approach is beneficial, as providing a more reliable (return to zero) analog read but, as should be apparent, is not the only design that can be used for an analog sense circuit.
  • FIG. 12 presents a voltage-type digital sense circuit 1201 , with the waveforms associated with the operation of this circuit being presented in FIG. 13.
  • This circuit for example, could be used as the digital sense circuit in the embodiment of FIG. 2A.
  • bitline BL Prior to sensing, the bitline BL is first grounded, and the circuit initialized. At time to, sense node N1 and the bitline are precharged using NMOS transistors 1203 and 1 205.
  • the sense node N1 is biased to a voltage which is equal to V bias -V t hN, where V thN is the threshold voltage of the NMOS transistor 1 203 (and of the other NMOS transistors seen in the FIG.), and 1 ⁇ 2, /as is selected such that node N1 is biased to a voltage equal to 3.0 volts.
  • signal BLC is used to turn "on" NMOS transistor 1 205 with a voltage of at least 3.0 volts, which will result in charging the bitline BL to a voltage of at least 3.0 volts minus V thN .
  • signal RST is brought low to turn "on” PMOS transistor 1 207, to thereby raise node INV to V dd .
  • Signals RST2 and STB2 are deasserted, allowing the state of the latch to be predefined by the signal LAT prior to time t 0 . Later in time, during sensing, the value of LAT can change when the signals SE, RST2, and STB2 are asserted (depending on the value of INV).
  • the BLC and PRE control signals are brought low to turn "off" NMOS transistors 1 203 and 1 205 and thereby isolate the sense node N1 and the bitline BL.
  • the RST signal is also de-asserted at time t1, to leave the INV node floating at V dd .
  • sensing begins.
  • a high voltage is used ( V pa ss) to turn "on” those cells irrespective of cell contents.
  • bitline contents will as a result of the digital sense operation represent whether the associated cell has a state "above” or "below” the associated wordline threshold (see e.g., FIG. 1 0).
  • the digital sense circuit is used only for predetermined, select operations; for example, in a flash implementation, a digital sense circuit is advantageously used in connection with individual PV cycles, to verify whether a programming iteration was successful or not. In this context, because cells begin erased and are progressively programmed toward the desired state (i.e., by increasing floating gate voltage as depicted in FIG.
  • the digital sense circuit in some designs is used with only a single predetermined voltage, with programming cycles progressive performed using one wordline voltage until the desired cell state has been reached.
  • a digital sense could be performed using successive iterations of a digital sense circuit, with different wordline voltages being used in each pass to discriminate the various possible cell states, e.g., for a two level cell, three different wordline voltages might used in successive passes to determine cell contents.
  • the potential of the bitline BL will start to ramp down for an "on" cell (it will otherwise remain at 3.0 volts minus I ). Then, at time t 3 , the BLC signal is raised to 2.0 volts to discriminate cell state. If the potential of the bitline BL is about 2.0 volts minus V thN voltage, then the NMOS transistor 1205 will start to conduct, which in turn reduces the potential of the N1 node (again, if the cell is an "on” cell - the voltage at node N1 will otherwise remain high).
  • N1 is used to control NMOS transistor 121 1 ; thus, when strobe signal STB is turned on at time t 4 , transistors 121 1 and 1213 will discharge node INV (and storage capacitor 1209) for an "on” cell, causing node INV to adopt the opposite state of the memory cell relative to wordline voltage. That is, node INV will be low for an "on” cell, and high for an “off” cell.
  • strobe signal STB turns on NMOS transistor 1213 and sense enable signal SE turns on NMOS transistor 1215 to transfer the INV data to a latch 1217, which will once again invert the data (from node INV).
  • the digital sense circuit begins with an erased memory cell and a bitline which has been initialized to a low value. As a consequence, the value at node LAT begins low and ends high once the memory cell program is complete.
  • FIG. 13 provides a timing diagram 1301 for the circuit illustrated in FIG. 12.
  • the diagram once again illustrates control voltages "S1 " and “S2" (used to control coupling of a string's substrate to source line and bitline, respectively, for a flash memory embodiment), as well as source voltage.
  • control voltages "S1 " and “S2” used to control coupling of a string's substrate to source line and bitline, respectively, for a flash memory embodiment
  • source voltages For program verification or read operations, “S1 " and “S2” are used to turn “on” associated access transistors at time t 2 (these access transistors are not seen in FIGS. 12 or 13); the source line itself is grounded.
  • programming operations although not reflected in FIG.
  • signal "S1” is used to turn all associated access transistors “off” (to decouple the substrate from the source line for all strings associated with the programming operation) while signal “S2” is used to turn its associated access transistor “on” (to couple each string to an associated bitline, and for programming or programming inhibition as determined by the specific bitline, per the circuit of FIG. 12).
  • FIG. 14 provides an alternative digital sense circuit 1401 , one based on a current-mode approach;
  • FIG. 15 provides a timing diagram 1501 to illustrate the operation of the circuit 1401 .
  • voltage-mode or current-mode technique can be used, depending on desired implementation objectives.
  • the sense amplifier is divided into two sensing nodes: SEN and SEN2.
  • a PMOS transistor 1403 and a NMOS transistor 1405 cooperate to supply current to precharge these nodes (these transistors will later be selectively turned “on” and “off” for charge transfers to nodes SEN and SEN2 during the actual sense process).
  • the second mode SEN2 also has an associated storage capacitor 1407 used to hold charge during the various processes.
  • a node INV is also initialized by grounding it, using an NMOS reset transistor 1409.
  • the threshold voltage will be selected to discriminate desired states (e.g., using a selected threshold for a programming operation, or using multiple passes with different thresholds for a read operation).
  • NMOS transistors 141 1 , 1413 and 1415 are all turned “on” using respective control voltages of I plus 0.9 volts, 0.7 volts and 0.5 volts.
  • the bitline will have been charged up to a voltage of around 0.5 volts, and the transistor 1403 is then turned “off” to stop the supply of current to nodes SEN and SEN2; transistor 1405 is also then turned “off” to decouple these two nodes. This decoupling makes it possible to prevent voltage discharge from node SEN even if unintended discharge of node SEN2 occurs.
  • the selected memory cell is "on,” that is, if it has a floating gate voltage that is lower than the applied wordline threshold, then the cell will connect the bitline to the source line (SRC), e.g., to ground, with current discharging from the sense circuit 1401 through this connection. As a result of this discharge, the level on the second node SEN2 gradually reduces. If the cell is an "off" cell, the degree of the reduction in level is smaller because the selected cell will not couple the bitline in question to the source line. Following the settling of voltage, at time t 5 , the control signal H00 for transistor 1405 is raised up to V sense + V thN , where V sense is on the order of 1 .0 Volts.
  • transistor 141 1 If the selected memory cell is an "on” cell, then transistor 141 1 is drained by current flowing through the bitline, and the voltage on node SEN2 drops below 1 .0 volts. By contrast, for an "off” memory cell, the transistor 141 1 stays “off” and node SEN2 is kept at a relatively high voltage (i.e., V dd ). Transistor 1405 then has a sense voltage applied ( Vsense) with the result that it too conducts and drops node SEN for an "on” cell, effectively transferring the state of the selected memory cell from node SEN2 to node SEN.
  • Vsense sense voltage applied
  • transistor 1417 conducts current from supply transistor 1419 to charge node INV to V dd (it should be recalled that signal RST previously initialized this node to ground); if the cell is an "on” cell, then transistor 1417 is turned “off” and node INV remains at ground. This data is then latched (and inverted) by circuit 1421 , with the result that node (and signal) LAT is driven to a state corresponding to the selected memory cell.
  • a digital sense circuit e.g., the circuit of FIG. 14
  • a digital sense circuit is advantageously applied for PV cycle operation; to this effect, transistors 1451 , 1453, 1457 and 1459 are controlled responsive to detected state to either enable or inhibit programming from voltage supply V dd .
  • FIG. 14 indicates that this functionality is based on the signal INV from node INV, other designs are also possible, for example, based on signal LAT or using other circuit designs or control methodologies.
  • FIGS. 8-15 were used to describe exemplary analog and digital circuits, respectively, which could optionally be applied in the embodiment of FIG. 2A. However, as mentioned earlier, it is also possible to use a single circuit which is configured (dynamically or otherwise) to the desired sense methodology, per the embodiment of FIG. 2B.
  • FIG. 16 shows such a configurable sense circuit 1601 .
  • circuit 1601 is selectively configurable into either of those earlier-described sense circuits. That is to say, circuit 1601 becomes either of circuit 801 from FIG. 8, or circuit 1401 from FIG. 14, through application of suitable control signals.
  • circuit 1601 becomes either of circuit 801 from FIG. 8, or circuit 1401 from FIG. 14, through application of suitable control signals.
  • FIG. 16 provides one example of a circuit with heavy reliance on shared circuit components.
  • signals PEN, BLX, IHT, XFR2 and RST2 are all grounded, turning “off” the associated NMOS transistors and turning “on” the lone PMOS transistor (associated with signal RST2); signals BLC, XXO and HOO are all set to V DD + VWN (i.e., turning these transistors all "on”); and signals FLT and STB2 are set to V DD , effectively turning the associated PMOS transistors "off.”
  • signals BLP, XFR, SAN and EQ are all grounded; signals STB2 and REF are all tied to V DD , and signals XFR2, CMP and XFR3 are all tied to V DD + V THN .
  • comparison circuit 1603 via appropriate control over signals RST2, EQ and SAN) as either the push-pull comparison circuit of FIG. 8 or the inverting latch described in connection with FIG. 14.
  • alternate-path NMOS transistors 1605 and 1607 are selectively controlled to cause sensing transistor 1609 to support either the analog current sense or digital voltage sense methodology, described above.
  • NMOS transistor 161 1 is enabled for a current-mode implementation (e.g., the circuit of FIG. 8), to provide a current supply to the bitline, or is disabled for voltage-mode sensing. Irrespective of the configuration of these elements, data representing memory cell state (relative to the applied wordline voltage) is produced as a high or low signal at node LAT (identified using numeral 1613 in FIG. 16).
  • FIG. 17 shows a high level block diagram of a flash memory system 1701 .
  • the system includes a flash memory device 1702 and a memory controller 1703.
  • the flash memory device includes a non-volatile storage array 1704 consisting of a number of individual memory cells 1705, which are each used to store one or more bits of data. While the flash memory device may be configured as NOR or NAND flash memory, it should be assumed in connection with the description below that the array 1704 is a NAND flash memory array, such that data is erased in units of blocks and both programmed and read in units of pages (i.e., using wordlines and strings as has previously been described). These memory cells can be multilevel memory cells, for example, two-level memory cells as has been previously described.
  • a group of sense amplifiers 1707 is used to sense memory cell contents for use in either programming or read transactions as has been previously described.
  • a page of data will be received via a write command from the memory controller 1703.
  • the memory controller will be connected to the flash device via one or more system busses, encompassing both a data path 1719 and a control path 1721 .
  • a command is received along the control path, with data being transferred in one direction or the other via the data path.
  • a programming operation or transaction that is, where the memory controller 1703 is to write a page of data to the flash memory device 1702
  • data will be received in IO circuitry 1717, with operations being managed by write control circuitry 1709.
  • the write control circuitry stores the received page of data into a write data register (or program register) 171 1 .
  • the flash memory device attempts in multiple program-verify (PV) cycles to cause every cell in a selected page (i.e., using a common wordline) to adopt a desired state.
  • PV program-verify
  • the write control circuitry 1709 attempts to program the data, and the sense amplifiers 1707 are then used to sense data in the page of memory cells to determine the extent of proper programming.
  • Data from the sense amplifiers is provided to the write control circuitry 1709 which then performs and "exclusive-OR" function with the information in the write data register, and which overwrites the page of data in the write data register with the results of the exclusive-OR.
  • the write data register stores "1 's" only for those locations which still require programming; that is to say, the original page of programming data is not left in the write data register, but rather the write data register is overwritten with the "delta" for use in further PV cycle attempts.
  • the write control circuitry 1709 attempts another programming cycle, with subsequent sense and/or exclusive-OR operations, and so on, until (a) proper programming of the entire page is achieved, or (b) a predetermined PV cycle limit is reached (e.g., 20 PV cycles). Either way, the memory controller is then informed of these states (e.g., busy, done or error) via a status register, reply command, or other structure, via control logic 1713.
  • programming operations involve a fair amount of latency, on the order of a microsecond to a millisecond for some designs.
  • read transactions that is, where the memory controller is to retrieve a page of data that was earlier programmed into the flash memory device
  • the operation typically requires only a single cycle and does not involve write control circuitry 1709; rather, the sense amplifiers 1707 return the requested page of data (typically involving only a subset of each multilevel cell) via path 1525 to buffer 1715, and subsequently, to IO circuitry 1717 and the memory controller 1703.
  • the sense amplifiers are coupled to the various buffers via an internal bus 1721 , with one path (1723) used during write (or programming) operations to check the results of each PV cycle programming attempt, and a second path (1725) used for read operations.
  • Flash memory can therefore involve significant latency for programming operations relative to read operations.
  • the latency is typically not an issue for most programming applications (e.g., the data is typically stored at times other than when it is urgently needed, and a memory controller or application can multitask while data is being written).
  • the latency penalty is typically a much more significant problem.
  • multimedia applications including gaming applications may require large amounts of data supplied at a very rapid pace.
  • the various circuits seen in FIG. 17 can be configured to reconcile demands for high performance (e.g., for read operations) and power conservation (e.g., where performance is not as critical, for example, for programming operations, where latency typically presents no significant issue).
  • FIG. 18 provides an embodiment to this end, illustrating a method 1801 that employs digital sense methodology for programming operations (e.g., for PV cycle verification) and analog sense methodology for read operations.
  • digital sense methodology for programming operations (e.g., for PV cycle verification) and analog sense methodology for read operations.
  • some conventional designs use 20 or more PV cycles for each programming operation, with significant allowance for latency built into the application or operation of the memory controller.
  • a digital sense mechanism can provide a highly reliable, low power sense mechanism which matches any existing latency allowance.
  • an analog sense mechanism can be advantageously employed to provide a relatively fast sense mechanism.
  • control logic configures the sense amplifiers and write control circuitry as appropriate to use either analog or digital sense methodology as desired for the implementation.
  • control logic identifies the operation or transaction type, per reference numeral 1803. In the depicted embodiment, this is be effectuated by determining that a command received from a remote memory controller is a write (or programming) command, as opposed to a read command. As indicated by numerals 1805 and 1807, if a programming operation is called for, digital sense methodology is employed, and if a read operation is called for, analog sense methodology is used; for example, alternative or reconfigurable circuits can be used for this purpose, per the discussion above (see, e.g., the embodiments set forth in FIGS. 2A and 2B). For a programming operation, sense amplifier output is fed back into write data circuitry (per method block 1809 and feedback path 181 1 ) and for a read operation, sense amplifier output is fed into a buffer or IO circuitry 1813.
  • PGMA PGMA
  • PGMD PGMD
  • the specific sense methodology is dependent on mode, e.g., analog sense methodology might be used for a write transaction if a mode register has a first value, and digital sense methodology might be used if the mode register has a second value.
  • FIG. 19 provides a block diagram 1901 illustrating operation of control circuitry 1903, such as was introduced in connection with FIG. 17.
  • the control circuitry 1903 includes a command parser 1905, for example, that identifies commands from the memory controller and that determines whether digital or analog sense methodology is to be employed.
  • the command parser also includes configuration logic 1909 that configures sense amplifier circuitry 1907 as appropriate, as well as array control circuitry 191 1 and voltage regulators 1913 to provide the desired operations and voltages as has previously been described. For example, it was mentioned that different wordline and source voltages can be applied depending on whether analog or digital sense methodology is used; the voltage regulation circuitry provides at least two mode-dependent voltages as outputs, as indicated in FIG. 19.
  • the array control circuitry provides the desired control signals and controls the voltage regulation circuitry to provide special voltage signals to cause individual circuit elements to behave a certain way (for example, by generating voltages such as V dd +V t hN, to cause certain transistors to act as short circuits).
  • the sense methodology optionally is dependent upon a predetermined correspondence 1915 or a programmable correspondence 1917.
  • this disclosure provides specific examples of a system, method and integrated circuit device that enhance the flexibility of memory devices.
  • this disclosure provides a mechanism that enables memory to be optimized to specific applications, to provide power savings and/or performance benefits on a selective basis not obtainable with many prior designs.
  • the combination of both analog and digital sense alternatives is optional.
  • teachings provided by this disclosure are not limited to flash memory, but are applicable to other memory forms, including both volatile and nonvolatile forms.

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  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention concerne la technologie des amplificateurs de lecture destinés à un dispositif de mémoire utilisant de multiples procédés de lecture. Dans une forme de réalisation, un dispositif de mémoire est configuré de manière à comporter à la fois des circuits de lecture numériques et des circuits de lecture analogiques, pouvant être utilisés en alternance ou simultanément. Dans une autre forme de réalisation, l'utilisation de circuits de lecture spécifiques dépend d'un mode ou d'une commande. Dans un autre mode de réalisation, les circuits de lecture spécifiques utilisés sont sensibles à des tâches prédéterminées. Dans une application envisageable, un dispositif de mémoire non volatile à niveaux multiples (tel qu'un dispositif à mémoire flash) utilise (a) des circuits de lecture numériques lors d'opérations de vérification des programmes, pour lesquelles il est souhaitable de minimiser la puissance et de rendre maximal l'impact des lignes de bits et pour lesquelles la latence est déjà fixée dans une certaine mesure par une opération de programmation et (b) des circuits de lecture analogiques répondant à des commandes de lecture, pour fournir des performances relativement élevées (au prix d'une plus forte consommation d'énergie). Différents ensembles de circuits peuvent être utilisés ou des circuits peuvent être partagés et/ou configurés en vue d'une opération de lecture multiple, selon la conception particulière.
PCT/US2011/063416 2011-01-27 2011-12-06 Cellule de mémoire à mécanismes de lecture multiples Ceased WO2012102785A2 (fr)

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Cited By (5)

* Cited by examiner, † Cited by third party
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FR3044460A1 (fr) * 2015-12-01 2017-06-02 Stmicroelectronics Rousset Amplificateur de lecture pour memoire, en particulier une memoire eeprom
WO2020237026A1 (fr) 2019-05-23 2020-11-26 Hefei Reliance Memory Limited Dispositifs et circuits de mémoire numérique-analogique mixte pour stockage et calcul sécurisés
TWI725482B (zh) * 2018-07-19 2021-04-21 慧榮科技股份有限公司 快閃記憶體控制器以及用來存取快閃記憶體模組的方法
CN113628671A (zh) * 2020-05-07 2021-11-09 美光科技公司 感测两个多级存储器单元以确定多个数据值
CN115240732A (zh) * 2022-07-29 2022-10-25 华中科技大学 一种1s1c存储器数据读取方法及系统

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US6044004A (en) * 1998-12-22 2000-03-28 Stmicroelectronics, Inc. Memory integrated circuit for storing digital and analog data and method
US6538922B1 (en) * 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
ITMI20041988A1 (it) * 2004-10-20 2005-01-20 Atmel Corp "metodo e sistema per la fornitura di rilevazione in un dispositivo di memoria a banchi multipli."
KR20090027458A (ko) * 2007-09-12 2009-03-17 삼성전자주식회사 반도체 장치

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3044460A1 (fr) * 2015-12-01 2017-06-02 Stmicroelectronics Rousset Amplificateur de lecture pour memoire, en particulier une memoire eeprom
US9761316B2 (en) 2015-12-01 2017-09-12 Stmicroelectronics (Rousset) Sas Reconfigurable sense amplifier for a memory device
US10049753B2 (en) 2015-12-01 2018-08-14 Stmicroelectronics (Rousset) Sas Reconfigurable sense amplifier
US11256425B2 (en) 2018-07-19 2022-02-22 Silicon Motion, Inc. Flash memory controller, flash memory module and associated electronic device
TWI725482B (zh) * 2018-07-19 2021-04-21 慧榮科技股份有限公司 快閃記憶體控制器以及用來存取快閃記憶體模組的方法
US11086567B2 (en) 2018-07-19 2021-08-10 Silicon Motion, Inc. Flash memory controller, flash memory module and associated electronic device
US11099781B2 (en) 2018-07-19 2021-08-24 Silicon Motion, Inc. Flash memory controller, flash memory module and associated electronic device
US11494086B2 (en) 2018-07-19 2022-11-08 Silicon Motion, Inc. Flash memory controller, flash memory module and associated electronic device
US11494085B2 (en) 2018-07-19 2022-11-08 Silicon Motion, Inc. Flash memory controller, flash memory module and associated electronic device
WO2020237026A1 (fr) 2019-05-23 2020-11-26 Hefei Reliance Memory Limited Dispositifs et circuits de mémoire numérique-analogique mixte pour stockage et calcul sécurisés
CN114756884A (zh) * 2019-05-23 2022-07-15 合肥睿科微电子有限公司 用于安全存储和计算的数模混合式存储器件及其操作方法
EP3973529A4 (fr) * 2019-05-23 2023-04-05 Hefei Reliance Memory Limited Dispositifs et circuits de mémoire numérique-analogique mixte pour stockage et calcul sécurisés
US11694744B2 (en) 2019-05-23 2023-07-04 Hefei Reliance Memory Limited Mixed digital-analog memory devices and circuits for secure storage and computing
CN114756884B (zh) * 2019-05-23 2026-03-17 合肥睿科微电子有限公司 用于安全存储和计算的数模混合式存储器件及其操作方法
CN113628671A (zh) * 2020-05-07 2021-11-09 美光科技公司 感测两个多级存储器单元以确定多个数据值
CN115240732A (zh) * 2022-07-29 2022-10-25 华中科技大学 一种1s1c存储器数据读取方法及系统

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