WO2013013959A3 - Hochvolttransistorbauelement und herstellungsverfahren - Google Patents

Hochvolttransistorbauelement und herstellungsverfahren Download PDF

Info

Publication number
WO2013013959A3
WO2013013959A3 PCT/EP2012/063282 EP2012063282W WO2013013959A3 WO 2013013959 A3 WO2013013959 A3 WO 2013013959A3 EP 2012063282 W EP2012063282 W EP 2012063282W WO 2013013959 A3 WO2013013959 A3 WO 2013013959A3
Authority
WO
WIPO (PCT)
Prior art keywords
region
voltage transistor
transistor component
body region
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2012/063282
Other languages
English (en)
French (fr)
Other versions
WO2013013959A2 (de
Inventor
Martin Knaipp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Ams AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams AG filed Critical Ams AG
Priority to US14/234,364 priority Critical patent/US9685437B2/en
Publication of WO2013013959A2 publication Critical patent/WO2013013959A2/de
Publication of WO2013013959A3 publication Critical patent/WO2013013959A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0156—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Das Hochvolttransistorbauelement weist ein p-leitendes Halbleitersubstrat (1) auf, das mit einer p-leitenden Epitaxieschicht (2) versehen ist. In der Epitaxieschicht befinden sich eine Wanne (3) und ein Body-Bereich (4). In dem Body-Bereich ist ein Source-Bereich (5) angeordnet, und in der Wanne ist ein Drain-Bereich (6) angeordnet. Ein Kanalbereich (7) befindet sich in dem Body-Bereich zwischen der Wanne und dem Source-Bereich. Eine Gate-Elektrode (8) ist über dem Kanalbereich angeordnet. Unterhalb des Source-Bereiches und des Kanalbereiches ist in dem Halbleitersubstrat und in der Epitaxieschicht ein tiefer Body-Bereich (11) vorhanden, der eine im Vergleich zu dem übrigen Halbleitersubstrat höhere Dotierstoffkonzentration aufweist.
PCT/EP2012/063282 2011-07-26 2012-07-06 Hochvolttransistorbauelement und herstellungsverfahren Ceased WO2013013959A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/234,364 US9685437B2 (en) 2011-07-26 2012-07-06 High-voltage transistor device and production method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011108651.3A DE102011108651B4 (de) 2011-07-26 2011-07-26 Hochvolttransistorbauelement und Herstellungsverfahren
DE102011108651.3 2011-07-26

Publications (2)

Publication Number Publication Date
WO2013013959A2 WO2013013959A2 (de) 2013-01-31
WO2013013959A3 true WO2013013959A3 (de) 2013-05-30

Family

ID=46513744

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2012/063282 Ceased WO2013013959A2 (de) 2011-07-26 2012-07-06 Hochvolttransistorbauelement und herstellungsverfahren

Country Status (3)

Country Link
US (1) US9685437B2 (de)
DE (1) DE102011108651B4 (de)
WO (1) WO2013013959A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2876686B1 (de) 2013-11-22 2019-03-20 ams AG Hochspannungs-Halbleitervorrichtung und Verfahren zu deren Herstellung
US9899484B1 (en) 2016-12-30 2018-02-20 Texas Instruments Incorporated Transistor with source field plates under gate runner layers
DE102017130223B4 (de) 2017-12-15 2020-06-04 Infineon Technologies Ag Halbleitervorrichtung mit elektrisch parallel geschalteten planaren Feldeffekttransistorzellen und zugehöriger DC-DC-Wandler

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890146A (en) * 1987-12-16 1989-12-26 Siliconix Incorporated High voltage level shift semiconductor device
EP0514060A2 (de) * 1991-05-06 1992-11-19 SILICONIX Incorporated DMOS-Transistorstruktur und Verfahren
US20040173846A1 (en) * 2003-03-05 2004-09-09 Hergenrother John Michael Diffused MOS devices with strained silicon portions and methods for forming same
WO2007128383A1 (en) * 2006-05-05 2007-11-15 Austriamicrosystems Ag High voltage transistor with improved high side performance
US20110049621A1 (en) * 2004-01-29 2011-03-03 Enpirion Incorporated, A Delaware Corporation Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57211778A (en) 1981-06-24 1982-12-25 Hitachi Ltd Mos semiconductor device
BE1007283A3 (nl) 1993-07-12 1995-05-09 Philips Electronics Nv Halfgeleiderinrichting met een most voorzien van een extended draingebied voor hoge spanningen.
US6249025B1 (en) * 1997-12-29 2001-06-19 Intel Corporation Using epitaxially grown wells for reducing junction capacitances
US7186609B2 (en) * 1999-12-30 2007-03-06 Siliconix Incorporated Method of fabricating trench junction barrier rectifier
US6784493B2 (en) * 2002-06-11 2004-08-31 Texas Instruments Incorporated Line self protecting multiple output power IC architecture
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
JP4667756B2 (ja) * 2004-03-03 2011-04-13 三菱電機株式会社 半導体装置
US8304830B2 (en) * 2010-06-10 2012-11-06 Macronix International Co., Ltd. LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process
US8623732B2 (en) * 2010-06-17 2014-01-07 Freescale Semiconductor, Inc. Methods of making laterally double diffused metal oxide semiconductor transistors having a reduced surface field structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4890146A (en) * 1987-12-16 1989-12-26 Siliconix Incorporated High voltage level shift semiconductor device
EP0514060A2 (de) * 1991-05-06 1992-11-19 SILICONIX Incorporated DMOS-Transistorstruktur und Verfahren
US20040173846A1 (en) * 2003-03-05 2004-09-09 Hergenrother John Michael Diffused MOS devices with strained silicon portions and methods for forming same
US20110049621A1 (en) * 2004-01-29 2011-03-03 Enpirion Incorporated, A Delaware Corporation Integrated Circuit with a Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same
WO2007128383A1 (en) * 2006-05-05 2007-11-15 Austriamicrosystems Ag High voltage transistor with improved high side performance

Also Published As

Publication number Publication date
US20140361374A1 (en) 2014-12-11
US9685437B2 (en) 2017-06-20
WO2013013959A2 (de) 2013-01-31
DE102011108651A1 (de) 2013-01-31
DE102011108651B4 (de) 2019-10-17

Similar Documents

Publication Publication Date Title
TW201613105A (en) Semiconductor device and manufacturing method thereof
WO2014051728A3 (en) Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates
WO2012092038A3 (en) A method to reduce contact resistance of n-channel transistors by using a iii-v semiconductor interlayer in source and drain
EP3514836A3 (de) Gate-kontakt-struktur über ein aktives gate und verfahren zur herstellung davon
WO2011123333A3 (en) Ldmos device with p-body for reduced capacitance
SG166085A1 (en) Semiconductor device including a mos transistor and production method therefor
EP2704188A3 (de) Halbleiterbauelement und Herstellungsverfahren dafür
GB2524677A (en) Deep gate-all-around semiconductor device having germanium or group III-V active layer
WO2011071598A3 (en) Quantum-well-based semiconductor devices
WO2008105077A1 (ja) 化合物半導体装置とその製造方法
PH12014500712A1 (en) Igbt and method of manufacturing the same
JP2013048246A5 (de)
TW201613097A (en) Semiconductor device and method of fabricating non-planar circuit device
EP2720272A3 (de) Transistor mit hoher Elektronenbeweglichkeit und Ansteuerverfahren dafür
TW201613107A (en) Semiconductor device and method for manufacturing semiconductor device
EP2755237A3 (de) Halbleiteranordnung mit Graben-Gateelektrode und Verfahren zu deren Herstellung
JP2011119690A5 (de)
WO2012119125A3 (en) High performance graphene transistors and fabrication processes thereof
JP2010258442A5 (ja) 溝の形成方法、および電界効果トランジスタの製造方法
EP2846358A3 (de) Halbleiterbauelement und Herstellungsverfahren dafür
JP2013016785A5 (de)
EP2824711A3 (de) Vertikale Transistoren mit P-Typ-Galliumnitridstromsperrschichten und Herstellungsverfahren dafür
TW201712873A (en) High electron mobility transistors with localized sub-fin isolation
EP2843708A8 (de) Transistoren auf Nitridbasis und Herstellungsverfahren dafür
EP2533291A3 (de) Halbleiterbauelement und Verfahren zu seiner Herstellung

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12735269

Country of ref document: EP

Kind code of ref document: A2

WWE Wipo information: entry into national phase

Ref document number: 14234364

Country of ref document: US

122 Ep: pct application non-entry in european phase

Ref document number: 12735269

Country of ref document: EP

Kind code of ref document: A2