Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/483—Converters with outputs that each can have more than two voltages levels
  • H02M7/487—Neutral point clamped inverters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0048—Circuits or arrangements for reducing losses
  • H02M1/0051—Diode reverse recovery losses
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/0048—Circuits or arrangements for reducing losses
  • H02M1/0054—Transistor switching losses
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
  • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
  • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
  • H02M7/5388—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with asymmetrical configuration of switches
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
  • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
  • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

• the present invention relates to the field of inverters, and more particularly to an inverter topology and a control method thereof for high frequency applications. Background technique
• Cool MOS Super Junction Field Effect Transistor
• FIG. 1 is a topological structure of a high efficiency inverter in the prior art, including two capacitors, two diodes Dx and Dx, and four power switches Ql, Q2, Q3, and Q4.
• Ql and Q4 are Cool MOS
• Q2 and Q3 are IGBTs.
• the control method is traditional SPWM (sinusoidal pulse width modulation), but its switching frequency is generally not high, mostly 19.2K. When the power is increased, the switching frequency may be lowered.
• the technical problem to be solved by the present invention is to provide an inverter topology and a control method thereof in a high frequency application, which have lower cost and obtain higher efficiency.
• an inverter topology in a high frequency application including: first and second capacitors, first, second, third, and fourth power switches, second and a three diode; wherein each power switch tube comprises a parasitic body diode connected in anti-parallel;
• the first capacitor and the second capacitor are connected in series, and the two ends thereof are respectively connected to the positive DC bus and the negative DC bus to provide DC input and output;
• the second diode is connected in series with the third diode, and the four power switching tubes are sequentially connected in series with the source and the drain connected;
• the two capacitors connected in series are connected in parallel with the four power switch tubes connected in series, and the junction of the first capacitor and the second capacitor is connected to the junction of the second diode and the third diode and connected sexual point or reference ground;
• the cathode of the second diode is connected to the junction of the first power switch tube and the second power switch tube, and the anode of the third diode is connected to the contact point of the third power switch tube and the fourth power switch tube;
• the second and third power switch tubes are connected to the inductor to provide an AC output; wherein, the first and fourth power switch tubes are respectively connected in series with a reverse fifth and sixth power switch tubes, and each Each of the power switch tubes includes an antiparallel parasitic body diode and a parasitic capacitance connected in parallel to block flow through the first and fourth power switch tubes by controlling turn-on and turn-off of the fifth and sixth power switch tubes The freewheeling current of the parasitic diode; at the same time, a separate first and fourth diodes are connected in parallel to the upper and lower arms to provide a freewheeling circuit.
• serial connection manner of the first to sixth power switch tubes is:
• the source of the first power switch is connected to the source of the fifth power switch
• a drain of the fifth power switch is connected to a drain of the second power switch
• a source of the second power switch is connected to a drain of the third power switch
• the source of the third power switch is connected to the drain of the fourth power switch
• the source of the fourth power switch tube is connected to the source of the sixth power switch tube
• the cathode of the second diode is connected to the junction of the fifth and second power switch tubes, the third two The anode of the pole tube is connected to the junction of the third and fourth power switch tubes;
• the cathode of the first diode is connected to the drain of the first power switch tube
• the anode of the fourth diode is connected to the drain of the sixth power switch tube
• the junction of the first and fourth diodes is connected to the second Connected to the junction of the third power switch.
• serial connection manner of the first to sixth power switch tubes is:
• a drain of the fifth power switch is connected to a drain of the first power switch
• a source of the first power switch is connected to a drain of the second power switch
• a source of the second power switch is connected to a drain of the third power switch
• the source of the third power switch tube is connected to the source of the sixth power switch tube
• a drain of the sixth power switch is connected to a drain of the fourth power switch
• a cathode of the second diode is connected to a junction of the first and second power switch tubes, and an anode of the third diode is connected to a junction of the third and sixth power switch tubes;
• the cathode of the first diode is connected to the source of the fifth power switch tube
• the anode of the fourth diode is connected to the source of the fourth power switch tube
• the junction of the first and fourth diodes is connected to the second Connected to the junction of the third power switch.
• serial connection manner of the first to sixth power switch tubes is:
• the source of the first power switch is connected to the source of the fifth power switch
• a drain of the fifth power switch is connected to a drain of the second power switch
• a source of the second power switch is connected to a drain of the third power switch
• the source of the third power switch is connected to the drain of the fourth power switch
• the source of the fourth power switch tube is connected to the source of the sixth power switch tube
• a cathode of the second diode is connected to a junction of the fifth and second power switch tubes, and an anode of the third diode is connected to a junction of the third and fourth power switch tubes;
• a cathode of the first diode is connected to a drain of the first power switch tube, and an anode of the first diode is connected to a contact point of the fifth and second power switch tubes;
• the anode of the fourth diode is coupled to the drain of the sixth power switch transistor, and the cathode of the fourth diode is coupled to the junction of the third and fourth power switch transistors.
• the parasitic body diodes of the fifth and sixth power switch tubes are diodes having avalanche breakdown characteristics.
• the fifth and sixth power switch tubes have R ds _ as small as possible.
• n a method for driving a control signal of an inverter topology is provided, including:
• Steps A, first, second, and fifth power switch tubes are turned on, so that current in the topology passes through the three power switch tubes;
• Step A2 the first and fifth power switch tubes are turned off, so that the current in the topology first charges the parasitic capacitances of the first and fifth power switch tubes, and then flows through the first diode;
• Step A3 the third and fifth power switch tubes are turned on, so that the current in the topology is freewheeled through the third power switch tube and the third diode; and the parasitic capacitance of the first power tube passes through the fifth power tube and the second Power tube charging;
• Step A4 The third power switch is turned off, so that the reverse passive current reversely charges the parasitic capacitance of the first power switch tube until the V ds of the first power switch tube is lower than the fifth power switch tube. V ds ;
• Step A5 the fifth power switch tube is turned off to block the reverse current, so that the current in the topology is freewheeled through the first diode;
• Steps Bl, third, fourth, the sixth power switch tube is turned on, so that the current in the topology passes through the three power switch tubes;
• Step B2 the fourth and sixth power switch tubes are turned off, so that the current first charges the parasitic capacitances of the fourth and sixth power switch tubes, and then flows through the fourth diode;
• Step B3 the second and sixth power tubes are turned on, and the inductor current can be freewheeled by the second diode and the second power tube; meanwhile, the parasitic capacitance of the fourth power tube is charged by the sixth power tube and the third power tube;
• Step B4 The second power tube is turned off, so that the reverse passive current is reversely charged to the parasitic capacitance of the fourth power tube through the sixth power tube and the third power tube until the V d on the fourth power tube is in the The maximum power of the six power tubes can withstand V ds ;
• Step B5 the sixth power tube is turned off, and the reverse current is blocked to make it flow through the fourth diode.
• the step A3 of the positive half-cycle operation further comprises: simultaneously opening the third and fifth power switch tubes; and the step B3 of the negative half-cycle operation further comprises: simultaneously opening the second and sixth power switch tubes.
• the first and fourth diodes are fast recovery or ultra fast recovery rectifier diodes.
• Step Cl the first, second, and fifth power switch tubes are turned on, so that the current in the topology passes through the three power switch tubes;
• Step C2 the first and fifth power switch tubes are turned off, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube, and when the inductor current and the voltage are reversed, The current in the topology flows through the first diode to the positive DC bus;
• Step C3 the first and fifth power switch tubes are kept off, and the third power switch tube is turned on.
• the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube.
• the inductor current is reversed from the voltage, the current in the topology flows through the third diode and the third power switch tube;
• Step C4 the first and fifth power switch tubes are kept off, the third power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the second diode and the second power switch tube. When the inductor current is reversed from the voltage, the current in the topology continues to flow through the first diode.
• Steps D1, third, fourth, the sixth power switch tube is turned on, so that the current in the topology passes through the three power switch tubes;
• Step D2 the fourth and sixth power switch tubes are turned off, and when the inductor current and the voltage are in the same direction, the current in the topology is freewheeled through the third power switch tube and the third diode, and when the inductor current and the voltage are reversed, The current in the topology flows from the negative DC bus to the output through the fourth diode;
• Step D3 the fourth and sixth power switch tubes are kept off, the second power switch tube is turned on, and when the inductor current and the voltage are in the same direction, the current in the topology flows through the third power switch tube and the third diode.
• the inductor current is reversed from the voltage, the current in the topology flows through the second diode and the second power switch tube;
• Step D4 the fourth and sixth power switch tubes are kept off, the second power switch tube is turned off, and when the inductor current and the voltage are in the same direction, the current in the topology passes through the third power switch tube and the third diode freewheeling When the inductor current is reversed from the voltage, the current in the topology continues to flow through the fourth diode.
• the invention has the advantages that: the added fifth and sixth power switch tubes and diodes are of a low voltage type, and the cost is low; the first and fourth power switch tubes in the inverter topology are not A special Cool MOS with a fast recovery body diode is required, and a cheaper common Cool MOS can be selected, and such a Cool MOS has a lower on-resistance, a lower price, and a higher efficiency. Moreover, the second and third power switch tubes only need to select a normal Cool MOS. DRAWINGS
• FIG. 1 is a schematic diagram of a topology structure of a commonly used high efficiency inverter in the prior art
• FIG. 2 is a schematic diagram of a topology of an inverter suitable for a high frequency switch in the prior art
• FIG. 3 is a schematic diagram of a topology of a high frequency inverter proposed in an embodiment of the present invention
• FIG. 4a-4d are diagrams A schematic diagram of driving mode and working mode of the high frequency inverter proposed in one embodiment
• FIG. 5 is a schematic diagram of a driving mode of a high frequency inverter according to another embodiment of the present invention
• FIGS. 6a-6f are schematic diagrams showing an operation mode of the driving mode of FIG. 5;
• FIG. 7 is a schematic diagram of a topology structure of a high frequency inverter according to another embodiment of the present invention.
• FIG. 8 is a schematic diagram of a topology structure of a high frequency inverter proposed in still another embodiment of the present invention.
• Cool MOS as a power switch is a good choice, but in a three-level inverter, due to the nonlinearity of the load, it is necessary to consider the reverse freewheeling current to the high frequency switch in the case of a non-linear load.
• a reverse low-voltage switch tube is connected in series, and by controlling the turn-on and turn-off of the low-voltage switch tube, the high-frequency switch can be blocked.
• the topology (ie, circuit structure) includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4; each power The switching transistors all have parasitic body diodes and parasitic capacitances (not shown in Figure 3).
• one end of the capacitor C1 and one end of the capacitor C2 are connected in series; the anode of the diode D2 is connected in series with the cathode of D3; the anode of the diode D1 is connected in series with the cathode of D4; the power switch tube Ql, Q2, Q3, Q4, Q5 and Q6 are connected in series; the series connection mode of the power switch is that the source of Q1 is connected to the source of Q5, the drain of Q5 is connected to the drain of Q2, the source of Q2 and the drain of Q3. Connected, the source of Q3 is connected to the drain of Q4, and the source of Q4 is connected to the source of Q6;
• the other end of the capacitor C1 is connected to the drain of the power switch tube Q1, the other end of the capacitor C2 is connected to the drain of the power switch tube Q6, and the junction of the capacitors C1 and C2 is connected to the junction of the diodes D2 and D3 and connected to the Neutral ( Neutral point, refers to the N line in the input L, N line, that is, the zero line; is the reference ground of the inverter system); the cathode of the diode D2 is connected to the junction of the power switch tube Q5 and Q2, and the anode connection power of the diode D3 The junction of the switch tube Q3 and Q4; the cathode of the diode D1 is connected to the drain of the power switch tube Q1, the anode of the diode D4 is connected to the drain of the power switch tube Q6, the junction of the diodes D1 and D4 is connected with the power switch tube Q2 and The junction of Q3 is connected.
• the power switch tubes Q5, Q6 and D1, D4 can prevent passive current from passing through the parasitic body diodes of Q1 and Q4, so that Q1 and Q4 can be used with lower source-drain equivalent resistance (Low R ds _ on ) It does not require the ultra-fast recovery of the body MOS of the body MOS, which reduces the cost of the inverter circuit structure.
• the upper bridge arm includes power switch tubes Q1, Q2, and Q5; and the lower bridge arm includes Q3, Q4, and Q6.
• Q5, Q6 should have as small as possible R ds _. n (for example, 1.8m ohm).
• R ds _. n for example, 1.8m ohm
• the power switching tubes Q5 and Q6 are low voltage switching tubes including a diode having an avalanche breakdown characteristic.
• the timing chart of the driving signals of the inverter topology shown in FIG. 3 may be as shown in FIG. 4a.
• Ql, Q2, Q3, Q4 drive the traditional SPWM control of the switch.
• Q1 and Q3, Q2 and Q4 are high frequency complementary, while Q1 and Q3 work in the first half of the power frequency cycle, and Q2 and Q4 work in the second half of the power frequency cycle.
• the Q5 driver follows Ql and the Q6 driver follows Q4.
• the working mode of the corresponding circuit is shown in Figures 4b ⁇ 4c.
• Q5 has an avalanche breakdown parasitic diode, that is, D5 is an avalanche diode:
• D5 When Q5 is subjected to back pressure, D5 reversely conducts, charging Q1 parasitic capacitance, forming protection for Q5 body;
• the voltage value is less than the avalanche breakdown voltage value of D5, D5 is turned off, and the freewheeling current only flows through D1.
• the current operation state returns to (1).
• the power switch tubes Q5 and Q6 are low voltage switch tubes including a general (no avalanche breakdown characteristic) parasitic body diode, according to another embodiment of the present invention, another embodiment is provided for the inverter topology shown in FIG. A control method, as shown in Figure 5.
• the circuit When the current and voltage have the same phase, the circuit operates in the same way as the traditional ideal mode (as shown in Figure 4a for Ql, Q2, Q3, Q4). However, the voltage and current on the inductor are always in phase difference.
• the design of the drive signal shown in Figure 5 is designed to properly handle the charge and discharge of the parasitic capacitance of the switch tube by controlling the switching of the device to avoid voltage spikes in the low-voltage tube. produce.
• the drive signal contains four period-period periodic drive signals:
• Q5 Before tl time, Q5 can also be turned on one's in advance, and the time is turned on to avoid switching loss on Q5 when Q1 is turned on.
• Q5 can be turned on, which is beneficial to reduce the loss caused by the Q1 parasitic capacitance charging current.
• Q5 is first turned on to reversely charge Q1, avoiding Q5 has a higher back pressure, and then turning off Q5 to block Q1. Reverse current
• the power switch tubes Ql, Q5, and Q2 are turned on, and in FIG. 6a, the current is filtered from the output inductor, through Q2.
• Q5 then flows through Q1 to the positive DC bus.
• the second time phase when the time t in Figure 5 is in the interval t2 and t3 (ie, when t2 ⁇ t ⁇ t3), the power switch tube Q1 is turned off, and the inverter operates in the dead time area;
• the working phase is shown in Figure 6b and Figure 6c.
• the power switch tube Q3 is turned on, and the current on the inductor passes through the power switch tube Q3 and the diode D3. After the freewheeling current, the current on the inductor flows through Q3 and D3 to the ground. At the same time, the positive DC bus charges the parasitic capacitance of Q1.
• the power switch Q5 can be turned on at any time, and Q5 is turned on to provide impedance to the parasitic capacitance of Q1. Small charging circuit.
• the power switch tubes Q5 and Q3 are simultaneously turned on;
• the fourth time phase when the time t in FIG. 5 is located in the interval t4 and t5 (ie, when t4 ⁇ t ⁇ t5), includes two working phases as shown in FIG. 6e and FIG. 6f; in FIG. 6e, when the power switch tube
• the reverse passive current (indicated by the arrow in the figure) reversely charges the parasitic capacitance of Q1 until the V d of the power switch Q1 is at the maximum V ds of the power switch Q5;
• Figure 6f turn off the low-voltage power switch Q5 to block the reverse current; the inductor current continues to flow through D1.
• the Q5 tube is briefly turned on after the Q3 tube is turned off, and the parasitic capacitance of the Q1 tube can be charged in advance, so that the voltage spike caused by the hard switch does not appear on the Q5.
• the above control can solve the transient high pressure of the low pressure pipe during the switching process. If the low-voltage power switch Q5 is not turned on to reverse the capacitance of the power switch Q1 in the corresponding working phase of Figure 6e, Q5 needs to withstand the instantaneous high voltage when the diode D1 is turned on, because the midpoint of the bridge arm on the left side of the inductor It is the positive bus voltage, and Q1 and Q5 still maintain the low voltage state before D1 is turned on.
• an inverter topology suitable for high frequency applications is also provided. As shown in FIG.
• the topology (ie, circuit structure) includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4;
• the rate switch tubes have parasitic body diodes and parasitic capacitances (not shown).
• the difference from the topology shown in FIG. 3 is: The positions of the power switch tubes Q5 and Q1 in FIG. 7 are opposite to those of the power switch tubes Q5 and Q1 in FIG. 3; the positions and diagrams of the power switch tubes Q6 and Q4 in FIG. 3 The position of the middle power switch tubes Q6 and Q4 is opposite.
• the upper arm includes power switch tubes Q5, Q1, and Q2; and the lower arm includes Q3, Q6, and Q4.
• the control scheme of the inverter topology suitable for high frequency applications shown in Fig. 7 is the same as that of the topology shown in Fig. 3, as shown in Fig. 4a and Fig. 5, respectively.
• an inverter topology suitable for high frequency applications is also provided.
• the topology ie, circuit structure
• the topology includes capacitors Cl, C2, power switch tubes Q1, Q2, Q3, Q4, power switch tubes Q5 and Q6, diodes D1, D2, D3, D4; each power
• the switching transistors each have a parasitic body diode and a parasitic capacitance (not shown).
• the diode D1 in Figure 8 is connected in parallel with the circuit in series with the power switch tubes Q5 and Q1; in Figure 8, the diode D4 is connected in parallel with the circuit in series with the power switch tubes Q6 and Q4.
• the upper arm includes power switches Q1 and Q5; and the lower arm includes Q4 and Q6.
• the control scheme of the inverter topology suitable for high frequency applications shown in Fig. 8 is the same as that of the topology shown in Fig. 3, as shown in Fig. 4a and Fig. 5, respectively.
• the power switch tubes Q5, Q6 and diodes added in the above inverter topology are of low voltage type, and the cost is low; the power switch tubes Q1 and Q4 in the inverter topology do not require special quick recovery body diodes.
• Cool MOS which can choose the cheaper common Cool MOS, has lower on-resistance, lower price and higher efficiency.
• Q2 and Q3 only need to select ordinary Cool MOS.

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