WO2015125722A1 - 複合基板 - Google Patents

複合基板 Download PDF

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WO2015125722A1
WO2015125722A1 PCT/JP2015/054085 JP2015054085W WO2015125722A1 WO 2015125722 A1 WO2015125722 A1 WO 2015125722A1 JP 2015054085 W JP2015054085 W JP 2015054085W WO 2015125722 A1 WO2015125722 A1 WO 2015125722A1
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Prior art keywords
silicon
substrate
coating layer
thin film
composite substrate
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PCT/JP2015/054085
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English (en)
French (fr)
Inventor
川合　信
小西　繁
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Shin-Etsu Chemical Co Ltd
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Shin-Etsu Chemical Co Ltd
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Priority to KR1020167024662A priority Critical patent/KR20160124796A/ko
Priority to US15/120,458 priority patent/US9716107B2/en
Priority to CN201580009375.7A priority patent/CN106062922B/zh
Priority to EP15752195.6A priority patent/EP3109893B1/en
Priority to JP2016504083A priority patent/JPWO2015125722A1/ja
Publication of WO2015125722A1 publication Critical patent/WO2015125722A1/ja
Anticipated expiration legal-status Critical
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    • C30—CRYSTAL GROWTH
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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Definitions

  • the present invention relates to a composite substrate mainly used for manufacturing a semiconductor device for high frequency, in which a silicon thin film is formed on the surface of a sintered substrate such as silicon nitride or aluminum nitride having high thermal conductivity.
  • the area where the device is made is from the surface to a thickness of about several ⁇ m, and the other area acts as a heat reservoir, so the efficiency is reduced from the viewpoint of heat dissipation.
  • the thermal conductivity of SiO 2 is 1.38 W / m ⁇ k, which is extremely problematic from the viewpoint of heat dissipation.
  • the silicon substrate has a large loss in the high frequency region due to its dielectric characteristics, and its use is limited.
  • silicon on sapphire (SOS) using a sapphire substrate has attracted attention because of its good thermal conductivity and low loss in the high frequency region, but has the following problems. That is, since the sapphire substrate is transparent in the visible light region, there is a problem that it does not react to the optical sensor used for checking the presence of the substrate or positioning the wafer during the device manufacturing process. There is also a problem that the cost of the sapphire substrate is high. In addition, the thermal expansion coefficient difference from silicon is large, and there is a problem that warpage is likely to occur during heat treatment or film formation of the composite substrate, and it is difficult to increase the diameter.
  • ceramic sintered bodies such as silicon nitride and aluminum nitride can be cited as substrates that are opaque to visible light, have good thermal conductivity, and are inexpensive.
  • the metal impurities such as Fe and Al contained in the powder, or the sintering aid itself such as alumina itself is a device manufacturing. There was a problem that it became a cause of contamination in the process and its use was difficult.
  • Patent Document 1 International Publication No. 2013/094665
  • the present invention has been made in view of the above circumstances, and is a composite in which a single crystal silicon thin film is provided on a ceramic sintered body that is opaque to visible light, has good thermal conductivity, has a low loss in a high frequency region, and is inexpensive.
  • An object of the present invention is to provide a composite substrate that is a substrate and can suppress metal impurity contamination from a sintered body and improve characteristics.
  • the present inventors have a composite substrate having a single crystal semiconductor thin film on at least the surface of an inorganic insulating sintered body substrate having a thermal conductivity of 5 W / m ⁇ K or more and a volume resistivity of 1 ⁇ 10 8 ⁇ ⁇ cm or more.
  • the above object can be effectively achieved by using a composite substrate in which a silicon coating layer made of polycrystalline silicon or amorphous silicon is interposed between the inorganic insulating sintered body substrate and the single crystal semiconductor thin film. I found out.
  • the present invention provides the following composite substrate.
  • a composite substrate having a single crystal semiconductor thin film on at least the surface of an inorganic insulating sintered body substrate having a thermal conductivity of 5 W / m ⁇ K or more and a volume resistivity of 1 ⁇ 10 8 ⁇ ⁇ cm or more A composite substrate comprising a silicon coating layer made of polycrystalline silicon or amorphous silicon between an inorganic insulating sintered body substrate and a single crystal semiconductor thin film.
  • the silicon coating layer covers the whole of the inorganic insulating sintered substrate.
  • the configuration of the composite substrate according to the embodiment of the present invention will be described below.
  • the composite substrate according to the present invention has a single crystal semiconductor thin film on at least the surface of an inorganic insulating sintered substrate having a thermal conductivity of 5 W / m ⁇ K or more and a volume resistivity of 1 ⁇ 10 8 ⁇ ⁇ cm or more.
  • a silicon coating layer made of polycrystalline silicon or amorphous silicon is provided between the inorganic insulating sintered body substrate and the single crystal semiconductor thin film.
  • the inorganic insulating sintered body used as the substrate its thermal conductivity is preferably higher than the thermal conductivity of SiO 2 of 1.5 W / m ⁇ k, more preferably 5 W / m ⁇ k or more, More preferably, it is 10 W / m ⁇ k or more.
  • the upper limit is not particularly limited, but is usually 2,500 W / m ⁇ K or less, particularly 2,000 W / m ⁇ K or less.
  • the volume resistivity of the substrate be as high as possible, preferably at least 1 ⁇ 10 8 ⁇ ⁇ cm or more, more preferably 1 ⁇ 10 10 ⁇ ⁇ cm or more. It is. Although the upper limit is not particularly limited, it is usually 1 ⁇ 10 18 ⁇ ⁇ cm or less, particularly 1 ⁇ 10 16 ⁇ ⁇ cm or less.
  • Examples of the inorganic insulating sintered body satisfying these conditions include a sintered body mainly composed of silicon nitride, aluminum nitride, sialon (SIALON: Si 3 N 4 .Al 2 O 3 ), or the like.
  • silicon nitride is most preferable because it has high resistance to chemicals used during the device manufacturing process and low substrate cost.
  • the “main component” means that silicon nitride, aluminum nitride, SIALON is used as a main raw material, and other auxiliary materials such as a sintering aid are included in addition to this, and silicon nitride, aluminum nitride, or SIALON is preferably used as a whole. Is more preferably 50% by mass or more, more preferably 80% by mass or more, and particularly preferably 90% by mass or more.
  • the thickness of the substrate is preferably 100 to 2,000 ⁇ m, particularly 200 to 1,000 ⁇ m.
  • the sintered body may contain a large amount of metal elements such as Fe and Al, particularly Al, which may have an adverse effect due to elution or diffusion in the device manufacturing process.
  • metal elements such as Fe and Al, particularly Al, which may have an adverse effect due to elution or diffusion in the device manufacturing process.
  • Fe is 1 ⁇ 10 17 atoms / cm 3 or less
  • Al is 1 ⁇ 10 17 atoms / cm 3 or less.
  • a single crystal semiconductor film can be formed directly on the substrate surface, but Fe exceeds the above concentration and is not more than 1 ⁇ 10 20 atoms / cm 3
  • Al exceeds the above concentration and is not more than 1 ⁇ 10 20 atoms / cm 3.
  • a silicon coating layer made of polycrystalline silicon or amorphous silicon.
  • the formation of the silicon coating layer is also recommended when Fe is 1 ⁇ 10 17 atoms / cm 3 or less and Al is 1 ⁇ 10 17 atoms / cm 3 or less.
  • a desired composite substrate can be obtained by providing a single crystal semiconductor film for forming an element, specifically, a single crystal silicon film, through the silicon coating layer.
  • the silicon coating layer is preferably provided not only on the surface of the substrate but also on the back surface and side surfaces to cover the entire substrate.
  • the silicon coating layer is intended to prevent elution or diffusion of metal impurities in the substrate, and the silicon coating layer needs to have high purity.
  • the respective concentrations of Al and Fe in the film of the silicon coating layer are not more than the concentration in the sintered body, typically not more than 1 ⁇ 10 17 atoms / cm 3 , preferably not less than 1 ⁇ 10 16.
  • the silicon coating layer makes it easy to obtain good adhesion between the single crystal semiconductor thin film and the substrate, or when an intermediate insulating layer described later is provided, the single crystal semiconductor thin film through the intermediate insulating layer is provided. It is easy to obtain good adhesion between the substrate and the substrate.
  • the thickness of the silicon coating layer is preferably 0.01 to 50 ⁇ m, particularly preferably 0.1 to 20 ⁇ m. If the thickness is less than 0.01 ⁇ m, it may be difficult to suppress metal impurity contamination from the substrate, and if it exceeds 50 ⁇ m, it may be disadvantageous in cost.
  • a single crystal silicon film is desirable because a device can be formed by a CMOS process using a normal bulk silicon substrate.
  • the thickness of the single crystal semiconductor thin film is usually 0.01 to 100 ⁇ m, preferably 0.05 to 1 ⁇ m.
  • a method for forming a single crystal semiconductor thin film a single crystal semiconductor substrate into which hydrogen or a rare gas ion is ion-implanted, such as a smart cut method, is bonded and then peeled off from the ion-implanted layer and transferred ( This method is referred to as a bonding method), and a method in which a semiconductor layer such as Si or SOI is bonded and then thinned by mechanical and / or chemical means.
  • the inorganic insulating sintered body substrate is coated with silicon nitride formed by chemical vapor deposition and a silicon coating layer is provided thereon, metal impurity contamination can be further suppressed.
  • the thickness of the silicon nitride coating layer is preferably 0.01 to 50 ⁇ m, particularly preferably 0.1 to 20 ⁇ m.
  • the silicon coating layer and the single crystal semiconductor thin film Is more preferable since the device characteristics are improved.
  • the thickness of the intermediate insulating layer is preferably 0.01 to 50 ⁇ m, particularly preferably 0.1 to 20 ⁇ m.
  • a single crystal semiconductor thin film may be formed by the bonding method after the intermediate insulating layer is formed on the silicon coating layer.
  • the entire surface of the silicon coating layer covering the entire surface of the substrate may be further coated with an intermediate insulating layer.
  • this intermediate insulating layer is formed on the surface of the single crystal semiconductor substrate in the bonding method, and after ion implantation, bonding is performed so that the intermediate insulating layer is in contact with the silicon coating layer. Alternatively, it may be peeled off from the ion-implanted layer and transferred. At this time, the intermediate insulating layer exists as an intervening layer only between the silicon coating layer and the single crystal semiconductor thin film.
  • the composite substrate of the present invention is mainly used for a power device generating a large amount of heat or an RF device using a high frequency.
  • Example 1 The structure of the composite substrate manufactured in this example is shown in FIG. First, an Si 3 N 4 sintered body having an outer diameter of 200 mm and a thickness of 725 ⁇ m was prepared as the inorganic insulating sintered body substrate 11. When the volume resistivity of this substrate was measured by the four-end needle method, it was 1 ⁇ 10 14 ⁇ ⁇ cm. Moreover, it was 15 W / m * k when the heat conductivity of the board
  • the concentration of the metal impurities contained in the silicon coating layer 12 is determined by immersing the substrate 11 on which the silicon coating layer 12 is formed in an HF aqueous solution, dissolving the natural oxide film of the silicon coating layer 12 in the HF aqueous solution, and ICM-MS. The analysis was performed by the method. As a result, the metal impurity in the silicon coating layer was the largest in Fe, and was 1.2 ⁇ 10 15 atoms / cm 3 . The next most metal impurity was Al, and its concentration was 1.0 ⁇ 10 14 atoms / cm 3 . Other metal impurities were below the detection limit (7 ⁇ 10 13 atoms / cm 3 ), and the concentrations were not problematic in the device manufacturing process.
  • a single crystal silicon thin film having a thickness of 0.3 ⁇ m was formed as a single crystal semiconductor thin film 13 on the silicon coating layer 12 on one surface of the substrate by a bonding method.
  • a composite substrate with less fear of metal contamination could be produced using an inexpensive sintered substrate having high thermal conductivity.
  • Example 2 The structure of the composite substrate manufactured in this example is shown in FIG. First, a Si 3 N 4 sintered body having an outer diameter of 150 mm and a thickness of 625 ⁇ m was prepared as the inorganic insulating sintered body substrate 11. When the volume resistivity of this substrate was measured by the four-end needle method, it was 1 ⁇ 10 14 ⁇ ⁇ cm. Moreover, it was 50 W / m * k when the heat conductivity of the board
  • the concentration of the metal impurities contained in the silicon coating layer 12 is determined by immersing the substrate 11 on which the silicon coating layer 12 is formed in an HF aqueous solution, dissolving the natural oxide film of the silicon coating layer 12 in the HF aqueous solution, and ICM-MS. The analysis was performed by the method. As a result, the metal impurity in the silicon coating layer was the largest in Fe, and was 1.5 ⁇ 10 15 atoms / cm 3 . The next most metal impurity was Al, and its concentration was 1.5 ⁇ 10 14 atoms / cm 3 . Other metal impurities were below the detection limit (7 ⁇ 10 13 atoms / cm 3 ), and the concentrations were not problematic in the device manufacturing process.
  • a single crystal silicon thin film having a thickness of 0.3 ⁇ m was formed as a single crystal semiconductor thin film 13 on the silicon coating layer 12 on one surface of the substrate by a bonding method.
  • a composite substrate with less fear of metal contamination could be produced using an inexpensive sintered substrate having high thermal conductivity.
  • Example 3 The composite substrate manufactured in this example is obtained by forming an intermediate insulating layer between the silicon coating layer 12 and the single crystal semiconductor thin film 13 with respect to the composite substrate shown in FIG. First, an Si 3 N 4 sintered body having an outer diameter of 200 mm and a thickness of 725 ⁇ m was prepared as the inorganic insulating sintered body substrate 11. When the volume resistivity of this substrate was measured by the four-end needle method, it was 1 ⁇ 10 14 ⁇ ⁇ cm. Moreover, it was 15 W / m * k when the heat conductivity of the board
  • An amorphous silicon film having a thickness of 1 ⁇ m was formed as a silicon coating layer 12 on the entire surface of the substrate 11 by sputtering.
  • the concentration of the metal impurities contained in the silicon coating layer 12 is determined by immersing the substrate 11 on which the silicon coating layer 12 is formed in an HF aqueous solution, dissolving the natural oxide film of the silicon coating layer 12 in the HF aqueous solution, and ICM-MS. The analysis was performed by the method. As a result, the metal impurity in the silicon coating layer was the largest in Fe, and was 1.5 ⁇ 10 15 atoms / cm 3 . The next most metal impurity was Al, and its concentration was 1.5 ⁇ 10 14 atoms / cm 3 .
  • a silicon oxide film as a middle insulating layer was formed on the silicon coating layer 12 on the entire surface of the substrate by a chemical vapor deposition method (CVD method) to a thickness of 2 ⁇ m.
  • the metal impurity concentration contained in the silicon oxide film was determined by dissolving the film in an HF aqueous solution and analyzing it by the ICM-MS method. As a result, the metal impurities in the film were below the detection limit (7 ⁇ 10 13 atoms / cm 3 ), and the concentration had no problem in the device manufacturing process.
  • a single crystal silicon thin film having a thickness of 0.3 ⁇ m was formed as a single crystal semiconductor thin film 13 on the intermediate insulating layer on one surface of the substrate by a bonding method.
  • a composite substrate with less fear of metal contamination could be produced using an inexpensive sintered substrate having high thermal conductivity.
  • Example 1 A Si 3 N 4 sintered body substrate having the same volume resistivity and thermal conductivity as in Example 1 was produced. When this substrate was immersed and dissolved in an HF aqueous solution and the metal impurity concentration was evaluated by the ICP-MS method, Fe was 1 ⁇ 10 19 atoms / cm 3 and Al was 5 ⁇ 10 18 atoms / cm 3. It was remarkably higher than the metal impurity concentration in the silicon coating layer of Example 1. Although there is no problem in volume resistivity and thermal conductivity, it is a concentration level at which contamination of the production line becomes a problem for use in the device manufacturing process, and cannot be used as it is.

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Abstract

　熱伝導率が５Ｗ／ｍ・Ｋ以上、かつ体積抵抗率が１×１０8Ω・ｃｍ以上の無機絶縁性焼結体基板１１の少なくとも表面に単結晶半導体薄膜１３を有する複合基板において、前記無機絶縁性焼結体基板１１と単結晶半導体薄膜１３との間に多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層１２を有する複合基板。　本発明により、可視光に不透明で熱伝導性がよく、更に高周波領域での損失が小さく、かつ安価なセラミックス焼結体上に単結晶シリコン薄膜を設けた複合基板であっても焼結体からの金属不純物汚染を抑制し、特性を向上させることが可能となる。

Description

複合基板
　本発明は、熱伝導性の高い窒化珪素や窒化アルミニウムのような焼結体基板の表面にシリコン薄膜を形成した主として高周波用の半導体デバイス製造用の複合基板に関するものである。
　近年、シリコン系半導体デバイスでは、デザインルールの微細化に伴い、益々その性能が向上している。そのため、個々のトランジスタやトランジスタ間を接続する金属配線からの放熱が問題となっている。この問題に対応するために、デバイスの作製後にシリコン基板の裏面を百～数百μｍ程度まで薄化し、巨大なファンをチップ上に取り付け、放熱を促すものや、水冷チューブをめぐらせたものも出現している。
　しかし、実際にシリコンを薄化しても、デバイスが作られる領域は表面から数μｍ程度の厚みまでであり、それ以外の領域は熱溜まりとして作用するので放熱という観点からは効率が悪くなっている。また近年、高性能プロセッサーなどに用いられるＳＯＩウェハなどはデバイス活性層の直下にＳｉＯ2からなる絶縁層を介した構造を有しているが、ＳｉＯ2の熱伝導率は１．３８Ｗ／ｍ・ｋと低く、放熱という観点から極めて問題であった。更に、シリコン基板は誘電特性の関係から高周波領域での損失が大きく、その使用には限界があった。
　また、熱伝導性が良く、かつ高周波領域での損失が小さいことよりサファイア基板を使用したシリコン・オン・サファイア（ＳＯＳ）が注目されているが、以下の問題がある。即ち、サファイア基板は可視光領域で透明であるため、デバイス製造プロセス中において基板の有無確認やウェハの位置決めに使用する光センサーに反応しない問題がある。また、サファイア基板のコストが高いという問題がある。更に、シリコンとの熱膨張率差も大きく、複合基板の熱処理や成膜時にそりが発生しやすく大口径化しにくいという問題もあった。
　また、可視光に不透明で熱伝導性が良く、かつ安価な基板として、窒化珪素や窒化アルミニウムなどのセラミックス焼結体を挙げることができる。しかし、これらは窒化珪素や窒化アルミニウムの粉体を焼結助剤で固めたものであるため、粉体中に含まれるＦｅやＡｌなどの金属不純物、あるいはアルミナなど焼結助剤そのものがデバイス製造プロセス中の汚染原因となり、その使用が困難であるという問題があった。
　なお、本発明に関連する先行技術として、国際公開第２０１３／０９４６６５号（特許文献１）が挙げられる。
国際公開第２０１３／０９４６６５号
　本発明は、上記事情に鑑みなされたもので、可視光に不透明で熱伝導性がよく、更に高周波領域での損失が小さく、かつ安価なセラミックス焼結体上に単結晶シリコン薄膜を設けた複合基板であって焼結体からの金属不純物汚染を抑制し、特性を向上させることが可能な複合基板を提供することを目的とする。
　本発明者らは、熱伝導率が５Ｗ／ｍ・Ｋ以上、かつ体積抵抗率が１×１０8Ω・ｃｍ以上の無機絶縁性焼結体基板の少なくとも表面に単結晶半導体薄膜を有する複合基板において、前記無機絶縁性焼結体基板と単結晶半導体薄膜との間に多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層を介在させた複合基板を用いることにより、上記目的が効果的に達成されることを知見した。
　即ち、本発明は、下記の複合基板を提供する。
〔１〕　熱伝導率が５Ｗ／ｍ・Ｋ以上、かつ体積抵抗率が１×１０8Ω・ｃｍ以上の無機絶縁性焼結体基板の少なくとも表面に単結晶半導体薄膜を有する複合基板において、前記無機絶縁性焼結体基板と単結晶半導体薄膜との間に多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層を有することを特徴とする複合基板。
〔２〕　前記シリコン被覆層が前記無機絶縁性焼結体基板の全体を覆っていることを特徴とする〔１〕記載の複合基板。
〔３〕　前記シリコン被覆層がスパッタリング法、電子ビーム蒸着法、化学気相成長法又はエピ成長法で形成された高純度シリコン層であることを特徴とする〔１〕又は〔２〕記載の複合基板。
〔４〕　前記無機絶縁性焼結体基板は、窒化珪素、窒化アルミニウム又はＳＩＡＬＯＮを主成分とすることを特徴とする〔１〕～〔３〕のいずれかに記載の複合基板。
〔５〕　前記単結晶半導体薄膜が単結晶シリコンであることを特徴とする〔１〕～〔４〕のいずれかに記載の複合基板。
〔６〕　更に、化学気相成長法で形成された窒化珪素被覆層を前記無機絶縁性焼結体基板とシリコン被覆層との間に有することを特徴とする〔１〕～〔５〕のいずれかに記載の複合基板。
〔７〕　前記シリコン被覆層と単結晶半導体薄膜との間に、酸化シリコン、窒化珪素、窒化アルミニウム及びＳＩＡＬＯＮから選ばれた材料からなる中間絶縁層を少なくとも一層有することを特徴とする〔１〕～〔６〕のいずれかに記載の複合基板。
　本発明によれば、可視光に不透明で熱伝導性がよく、更に高周波領域での損失が小さく、安価な無機絶縁性焼結体を用いて、金属不純物汚染が抑制された安価な複合基板を提供できる。
本発明に係る複合基板の構成例を示す断面図である。
　以下に、本発明に係る複合基板の一実施の形態における構成について説明する。
　本発明に係る複合基板は、熱伝導率が５Ｗ／ｍ・Ｋ以上、かつ体積抵抗率が１×１０8Ω・ｃｍ以上の無機絶縁性焼結体基板の少なくとも表面に単結晶半導体薄膜を有する複合基板において、前記無機絶縁性焼結体基板と単結晶半導体薄膜との間に多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層を有することを特徴とする。
　ここで、基板として使用する無機絶縁性焼結体としては、その熱伝導率はＳｉＯ2の熱伝導率１．５Ｗ／ｍ・ｋより高いことが好ましく、より好ましくは５Ｗ／ｍ・ｋ以上、更に好ましくは１０Ｗ／ｍ・ｋ以上である。その上限は特に制限されないが、通常２，５００Ｗ／ｍ・Ｋ以下、特に２，０００Ｗ／ｍ・Ｋ以下である。
　また、誘電特性による電力ロスを抑えるため、基板の体積抵抗率ができるだけ高いことが望まれ、少なくとも１×１０8Ω・ｃｍ以上であることが好ましく、より好ましくは１×１０10Ω・ｃｍ以上である。その上限は特に制限されないが、通常１×１０18Ω・ｃｍ以下、特に１×１０16Ω・ｃｍ以下である。
　これらの条件を満たす無機絶縁性焼結体としては、窒化珪素、窒化アルミニウム、サイアロン（ＳＩＡＬＯＮ：Ｓｉ3Ｎ4・Ａｌ2Ｏ3）などを主成分とする焼結体を挙げることができる。その中でも、デバイス製造プロセス中に使用される薬液耐性が高いこと、また基板コストが安いことより、窒化珪素が最も好ましい。なお、「主成分」とは、窒化珪素、窒化アルミニウム、ＳＩＡＬＯＮを主原料とし、それ以外に焼結助剤等の副原料を含むという意味であり、窒化珪素、窒化アルミニウム又はＳＩＡＬＯＮを好ましくは全体の５０質量％以上、より好ましくは８０質量％以上、特に好ましくは９０質量％以上含むものである。
　なお、上記基板の厚さは１００～２，０００μｍ、特に２００～１，０００μｍとすることが好ましい。
　上記焼結体にはＦｅ、Ａｌなどの金属元素、特にＡｌが多く含まれる場合があり、それらがデバイス製造プロセスにおいて溶出あるいは拡散などによって悪影響を及ぼすおそれがある。
　この場合、基板中の不純物濃度をＩＣＰ－ＭＳ法（誘導結合プラズマ質量分析法）で評価した場合、Ｆｅが１×１０17ａｔｏｍｓ／ｃｍ3以下、Ａｌが１×１０17ａｔｏｍｓ／ｃｍ3以下の場合は、基板表面に直接単結晶半導体膜を形成することができるが、Ｆｅが上記濃度を超え１×１０20ａｔｏｍｓ／ｃｍ3以下、Ａｌが上記濃度を超え１×１０20ａｔｏｍｓ／ｃｍ3以下の場合は、これら不純物の溶出を防止するため、基板全体を多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層で覆うことが好ましい。もちろん、Ｆｅが１×１０17ａｔｏｍｓ／ｃｍ3以下、Ａｌが１×１０17ａｔｏｍｓ／ｃｍ3以下の場合も、上記シリコン被覆層を形成することが推奨される。上記シリコン被覆層を介して、素子を形成する単結晶半導体膜、具体的には単結晶シリコン膜を設けることにより、所望の複合基板を得ることができる。なお、上記シリコン被覆層は基板の表面だけではなく、裏面及び側面にも設けて基板全体を覆うことが好ましい。
　上記シリコン被覆層は、基板中の金属不純物の溶出あるいは拡散防止が目的であり、このシリコン被覆層は高純度である必要がある。それを実現するため、シリコン被覆層を設ける手段として、スパッタリング法、電子ビーム蒸着法、化学気相成長法又はエピ成長法を用いることが好ましい。こうした手段を用いることにより、シリコン被覆層の膜中のＡｌ及びＦｅのそれぞれの濃度を焼結体中の濃度以下、典型的には１×１０17ａｔｏｍｓ／ｃｍ3以下、好ましくは１×１０16ａｔｏｍｓ／ｃｍ3以下、より好ましくは１×１０15ａｔｏｍｓ／ｃｍ3以下にすることができ、基板からの金属不純物汚染を抑えることができる。シリコン被覆層を構成する多結晶シリコンやアモルファスシリコンは一般的によく使われる膜であるため、安価かつ容易に形成することが可能である。
　また、シリコン被覆層により、単結晶半導体薄膜と基板との間で良好な密着性が得られやすくなり、又は後述する中間絶縁層を設ける場合には該中間絶縁層を介しての単結晶半導体薄膜と基板との間で良好な密着性が得られやすくなる。
　なお、シリコン被覆層の厚さは０．０１～５０μｍ、特に０．１～２０μｍとすることが好ましい。厚さが０．０１μｍ未満では基板からの金属不純物汚染を抑制することが困難となるおそれがあり、５０μｍ超ではコスト面で不利となる場合がある。
　上記シリコン被覆層を介して形成される単結晶半導体薄膜としては、単結晶シリコン膜とすれば、通常のバルクのシリコン基板を用いるＣＭＯＳ工程でデバイスを形成することが可能となり、望ましい。また、単結晶半導体薄膜の厚さとしては、通常０．０１～１００μｍ、特に０．０５～１μｍとすることが好ましい。この場合、単結晶半導体薄膜の形成方法としては、スマートカット法のような水素や希ガスイオンをイオン注入した単結晶半導体基板を貼り合わせた後、イオン注入した層から剥離して転写する方法（この方法を貼り合わせ法と称する）、ＳｉやＳＯＩなどの半導体層を接合した後、機械的及び／又は化学的手段で薄化する方法などが挙げられる。
　また、上記無機絶縁性焼結体基板が化学気相成長法で形成された窒化珪素で被覆され、その上にシリコン被覆層を設けると、より一層金属不純物汚染を抑制することができる。
　この窒化珪素の被覆層の厚さは０．０１～５０μｍ、特に０．１～２０μｍとすることが好ましい。
　更に、上記シリコン被覆層と単結晶半導体薄膜との間に、酸化シリコン、窒化珪素、窒化アルミニウム及びＳＩＡＬＯＮから選ばれた材料からなる中間絶縁層を少なくとも一層設けると、シリコン被覆層と単結晶半導体薄膜との間が絶縁され、作製するデバイス特性が良好になるのでより一層好ましい。なお、中間絶縁層を設ける手段として、スパッタリング、電子ビーム蒸着又は化学気相成長法を用いることが好ましい。また、この中間絶縁層の厚さは０．０１～５０μｍ、特に０．１～２０μｍとすることが好ましい。
　この場合の複合基板の製造手順としては、上記シリコン被覆層上にこの中間絶縁層を形成した後に、上記貼り合わせ法によって単結晶半導体薄膜を形成してもよい。このとき、基板全面を被覆したシリコン被覆層全面を中間絶縁層で更に被覆したものとするとよい。あるいは、複合基板の別の製造手順として、貼り合わせ法における単結晶半導体基板の表面にこの中間絶縁層を形成し、イオン注入した後に、シリコン被覆層に中間絶縁層が接するように貼り合わせを行い、イオン注入した層から剥離して転写するようにしてもよい。このとき、中間絶縁層は、シリコン被覆層と単結晶半導体薄膜との間のみに介在層として存在する。
　本発明の複合基板は、主として発熱の大きいパワーデバイスや高周波を用いるＲＦデバイスなどに用いられる。
　以下に、実施例及び比較例を挙げて、本発明を更に具体的に説明するが、本発明は下記の実施例に限定されるものではない。
［実施例１］
　本実施例で作製する複合基板の構成を図１に示す。
　まず無機絶縁性焼結体基板１１として、外径２００ｍｍ、厚さ７２５μｍのＳｉ3Ｎ4焼結体を作製した。この基板の体積抵抗率を４端針法で測定したところ、１×１０14Ω・ｃｍであった。また、基板の熱伝導率をレーザーフラッシュ法で測定したところ、１５Ｗ／ｍ・ｋであった。
　この基板１１の全面にシリコン被覆層１２として多結晶シリコン膜をＣＶＤ法で厚さ２μｍ形成した。このシリコン被覆層１２の膜中に含まれる金属不純物濃度は、シリコン被覆層１２を形成した基板１１ごとＨＦ水溶液中に浸漬し、シリコン被覆層１２の自然酸化膜をＨＦ水溶液に溶解しＩＣＭ－ＭＳ法で分析することにより行った。その結果、シリコン被覆層中の金属不純物はＦｅが最も多く、１．２×１０15ａｔｏｍｓ／ｃｍ3であった。次に多い金属不純物はＡｌであり、その濃度は１．０×１０14ａｔｏｍｓ／ｃｍ3であった。その他の金属不純物は検出限界（７×１０13ａｔｏｍｓ／ｃｍ3）以下であり、デバイス製造プロセスで問題の無い濃度であった。
　次いで、その基板の一方の面のシリコン被覆層１２上に単結晶半導体薄膜１３として厚さ０．３μｍの単結晶シリコン薄膜を貼り合わせ法によって作成した。
　以上のように、熱伝導率が高く安価な焼結体基板を用いて、金属汚染の懸念が少ない複合基板を作製することができた。
［実施例２］
　本実施例で作製する複合基板の構成を図１に示す。
　まず無機絶縁性焼結体基板１１として、外径１５０ｍｍ、厚さ６２５μｍのＳｉ3Ｎ4焼結体を作製した。この基板の体積抵抗率を４端針法で測定したところ、１×１０14Ω・ｃｍであった。また、基板の熱伝導率をレーザーフラッシュ法で測定したところ、５０Ｗ／ｍ・ｋであった。
　この基板１１の全面にシリコン被覆層１２としてアモルファスシリコン膜をスパッタリング法で厚さ１μｍ形成した。このシリコン被覆層１２の膜中に含まれる金属不純物濃度は、シリコン被覆層１２を形成した基板１１ごとＨＦ水溶液中に浸漬し、シリコン被覆層１２の自然酸化膜をＨＦ水溶液に溶解しＩＣＭ－ＭＳ法で分析することにより行った。その結果、シリコン被覆層中の金属不純物はＦｅが最も多く、１．５×１０15ａｔｏｍｓ／ｃｍ3であった。次に多い金属不純物はＡｌであり、その濃度は１．５×１０14ａｔｏｍｓ／ｃｍ3であった。その他の金属不純物は検出限界（７×１０13ａｔｏｍｓ／ｃｍ3）以下であり、デバイス製造プロセスで問題の無い濃度であった。
　次いで、その基板の一方の面のシリコン被覆層１２上に単結晶半導体薄膜１３として厚さ０．３μｍの単結晶シリコン薄膜を貼り合わせ法によって作成した。
　以上のように、熱伝導率が高く安価な焼結体基板を用いて、金属汚染の懸念が少ない複合基板を作製することができた。
［実施例３］
　本実施例で作製する複合基板は、図１に示す複合基板について、更にシリコン被覆層１２と単結晶半導体薄膜１３との間に中間絶縁層を形成したものである。
　まず無機絶縁性焼結体基板１１として、外径２００ｍｍ、厚さ７２５μｍのＳｉ3Ｎ4焼結体を作製した。この基板の体積抵抗率を４端針法で測定したところ、１×１０14Ω・ｃｍであった。また、基板の熱伝導率をレーザーフラッシュ法で測定したところ、１５Ｗ／ｍ・ｋであった。
　この基板１１の全面にシリコン被覆層１２としてアモルファスシリコン膜をスパッタリング法で厚さ１μｍ形成した。このシリコン被覆層１２の膜中に含まれる金属不純物濃度は、シリコン被覆層１２を形成した基板１１ごとＨＦ水溶液中に浸漬し、シリコン被覆層１２の自然酸化膜をＨＦ水溶液に溶解しＩＣＭ－ＭＳ法で分析することにより行った。その結果、シリコン被覆層中の金属不純物はＦｅが最も多く、１．５×１０15ａｔｏｍｓ／ｃｍ3であった。次に多い金属不純物はＡｌであり、その濃度は１．５×１０14ａｔｏｍｓ／ｃｍ3であった。その他の金属不純物は検出限界（７×１０13ａｔｏｍｓ／ｃｍ3）以下であり、デバイス製造プロセスで問題の無い濃度であった。
　次いで、この基板全面のシリコン被覆層１２上に中間絶縁層として酸化シリコン膜を化学気相成長法（ＣＶＤ法）で厚さ２μｍ形成した。この酸化シリコン膜中に含まれる金属不純物濃度は、その膜をＨＦ水溶液に溶解しＩＣＭ－ＭＳ法で分析することにより行った。その結果、膜中の金属不純物は検出限界（７×１０13ａｔｏｍｓ／ｃｍ3）以下であり、デバイス製造プロセスで問題の無い濃度であった。
　最後に、その基板の一方の面の中間絶縁層上に単結晶半導体薄膜１３として厚さ０．３μｍの単結晶シリコン薄膜を貼り合わせ法によって作成した。
　以上のように、熱伝導率が高く安価な焼結体基板を用いて、金属汚染の懸念が少ない複合基板を作製することができた。
［比較例１］
　実施例１と同じ体積抵抗率及び熱伝導率であるＳｉ3Ｎ4焼結体基板を作製した。この基板をＨＦ水溶液に浸漬して溶解し、ＩＣＰ－ＭＳ法で金属不純物濃度を評価したところ、Ｆｅが１×１０19ａｔｏｍｓ／ｃｍ3、Ａｌが５×１０18ａｔｏｍｓ／ｃｍ3であり、実施例１のシリコン被覆層中の金属不純物濃度に比べ著しく高かった。体積抵抗率や熱伝導率は問題ないが、デバイス製造プロセスで用いるには製造ラインの汚染が問題になる濃度レベルであり、そのままの形態では使用できなかった。
　なお、これまで本発明を図面に示した実施形態をもって説明してきたが、本発明は図面に示した実施形態に限定されるものではなく、他の実施形態、追加、変更、削除など、当業者が想到することができる範囲内で変更することができ、いずれの態様においても本発明の作用効果を奏する限り、本発明の範囲に含まれるものである。
１１　無機絶縁性焼結体基板
１２　シリコン被覆層
１３　単結晶半導体薄膜

Claims (7)

  1. 　熱伝導率が５Ｗ／ｍ・Ｋ以上、かつ体積抵抗率が１×１０8Ω・ｃｍ以上の無機絶縁性焼結体基板の少なくとも表面に単結晶半導体薄膜を有する複合基板において、前記無機絶縁性焼結体基板と単結晶半導体薄膜との間に多結晶シリコン又はアモルファスシリコンからなるシリコン被覆層を有することを特徴とする複合基板。
  2. 　前記シリコン被覆層が前記無機絶縁性焼結体基板の全体を覆っていることを特徴とする請求項１記載の複合基板。
  3. 　前記シリコン被覆層がスパッタリング法、電子ビーム蒸着法、化学気相成長法又はエピ成長法で形成された高純度シリコン層であることを特徴とする請求項１又は２記載の複合基板。
  4. 　前記無機絶縁性焼結体基板は、窒化珪素、窒化アルミニウム又はＳＩＡＬＯＮを主成分とすることを特徴とする請求項１～３のいずれか１項記載の複合基板。
  5. 　前記単結晶半導体薄膜が単結晶シリコンであることを特徴とする請求項１～４のいずれか１項記載の複合基板。
  6. 　更に、化学気相成長法で形成された窒化珪素被覆層を前記無機絶縁性焼結体基板とシリコン被覆層との間に有することを特徴とする請求項１～５のいずれか１項記載の複合基板。
  7. 　前記シリコン被覆層と単結晶半導体薄膜との間に、酸化シリコン、窒化珪素、窒化アルミニウム及びＳＩＡＬＯＮから選ばれた材料からなる中間絶縁層を少なくとも一層有することを特徴とする請求項１～６のいずれか１項記載の複合基板。
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