WO2015165218A1 - 电压比较器 - Google Patents

电压比较器 Download PDF

Info

Publication number
WO2015165218A1
WO2015165218A1 PCT/CN2014/088469 CN2014088469W WO2015165218A1 WO 2015165218 A1 WO2015165218 A1 WO 2015165218A1 CN 2014088469 W CN2014088469 W CN 2014088469W WO 2015165218 A1 WO2015165218 A1 WO 2015165218A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
drain
source
gate
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/088469
Other languages
English (en)
French (fr)
Inventor
詹昶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Huiding Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Huiding Technology Co Ltd filed Critical Shenzhen Huiding Technology Co Ltd
Priority to EP14891116.7A priority Critical patent/EP3096454B1/en
Priority to KR1020167018348A priority patent/KR101826456B1/ko
Publication of WO2015165218A1 publication Critical patent/WO2015165218A1/zh
Priority to US15/203,796 priority patent/US9742387B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/0038—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a voltage comparator with low static power consumption.
  • Figure 1 shows a conventional voltage comparator circuit.
  • the power consumption of the circuit is determined by the size of the tail current source IB.
  • the tail current source IB is generally composed of an NMOS transistor, and an additional bias circuit is required to provide the gate voltage, so the actual power consumption of the circuit is greater.
  • the Chinese patent CN201210242224.4's fully differential high-speed low-power comparator has the advantages of high output slew rate and high speed, but its power consumption is as high as 56uW, and the value of this power consumption does not have the bias circuit required by the comparator. Calculated, so the actual circuit power consumption will be greater.
  • the time domain comparator of the low-power feedback control structure of the Chinese patent CN200910242582.3 is characterized by digital logic control to reduce static power consumption, but its power consumption is 9uW, and the value of this power consumption has not been compared.
  • the digital sequential circuit required by the device is calculated, and the same actual circuit consumes more power.
  • the voltage comparator of the Chinese patent CN201010601379.3 is characterized by utilizing the subthreshold operating characteristics of the transistor to reduce the power consumption of the circuit under the condition of ensuring a certain circuit delay, and the power consumption thereof is 2 uW;
  • the circuit may have self-biasing capability, but the comparator has four power-consuming branches, so if you want to reduce its operating current to below 100nA, then each branch is averaged.
  • the power consumption will be as low as 25nA and the reliability of the circuit will be reduced.
  • the present invention provides a voltage comparator comprising a first branch, a second branch and a third branch, the first branch comprising a first transistor, a second transistor and a third transistor, the first transistor
  • the source is connected to the power source, the gate is connected to the drain thereof, the drain is connected to the drain of the second transistor, the gate of the second transistor is connected to the first input terminal, the source is connected to the drain of the third transistor, and the source of the third transistor is grounded.
  • the drain is connected to the gate;
  • the second branch includes a fourth transistor, a fifth transistor and a sixth transistor, the fourth transistor source is connected to the power source, the gate is connected to the drain thereof, and the drain is connected to the drain of the fifth transistor;
  • the fifth transistor gate is connected to the second input terminal, the source is connected to the sixth transistor drain; the sixth transistor source is grounded, the drain is connected to the gate thereof;
  • the third branch includes the seventh transistor and the eighth transistor, the seventh transistor
  • the source is connected to the power source, the gate is connected to the node of the first transistor and the second transistor, the drain is connected to the output of the voltage comparator and the drain of the eighth transistor, and the seventh transistor forms a current with the first transistor.
  • Eighth transistor gate node of the fifth transistor and the sixth transistor, a drain connected to the voltage comparator output, a source grounded, the sixth transistor and the eighth transistor form a current mirror.
  • the voltage comparator further includes a first resistor, one end of the first resistor is connected to the second input end, and the other end is grounded.
  • the first transistor, the fourth transistor, and the seventh transistor are PMOS
  • the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the eighth transistor are NMOS.
  • one end of the first resistor is connected to the second input end, and the other end is connected to the power source.
  • the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are PMOS, and the third transistor, the sixth transistor, and the eighth transistor are NMOS.
  • the embodiment of the invention further provides a voltage comparator comprising a first branch, a second branch and a third branch, the first branch comprising a first transistor, a second transistor and a third transistor, the first transistor source
  • the pole is connected to the power source, the gate is connected to the drain thereof, the drain is connected to the drain of the second transistor; the gate of the second transistor is connected to the first input terminal, the source is connected to the drain of the third transistor; the source of the third transistor is grounded and drained
  • the pole is connected to its gate; the second branch includes a fourth transistor, a fifth transistor, and a sixth transistor.
  • the fourth transistor source is connected to the power source, the gate is connected to the drain thereof, the drain is connected to the drain of the fifth transistor, the fifth transistor gate is connected to the second input terminal, the source is connected to the sixth transistor drain, and the sixth transistor source is connected.
  • the pole is grounded, the drain is connected to the gate thereof;
  • the third branch includes a seventh transistor and an eighth transistor, the seventh transistor source is connected to the power source, the gate is connected to the nodes of the fourth transistor and the fifth transistor, and the drain is compared with the voltage
  • the output of the device is connected to the drain of the eighth transistor, the seventh transistor and the fourth transistor form a current mirror; the gate of the eighth transistor is connected to the node of the second transistor and the third transistor, and the drain is connected to the output of the voltage comparator, the source
  • the pole is grounded, and the eighth transistor and the third transistor form a current mirror.
  • the voltage comparator further includes a first resistor, one end of the first resistor is connected to the second input end, and the other end is grounded.
  • the first transistor, the fourth transistor, and the seventh transistor are PMOS
  • the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the eighth transistor are NMOS.
  • one end of the first resistor is connected to the second input terminal, and the other end is connected to the power source.
  • the first transistor, the fourth transistor, and the seventh transistor are PMOS
  • the second transistor, the third transistor, the fifth transistor, the sixth transistor, and the eighth transistor are NMOS.
  • the embodiment of the invention further provides a voltage comparator comprising a first branch, a second branch, a third branch and a fourth branch, the first branch comprising a first transistor, a second transistor and a third transistor
  • the first transistor source is connected to the power source, the gate is connected to the drain thereof, and the drain is connected to the second transistor drain; the second transistor gate is connected to the first input terminal, the source is connected to the third transistor drain; the third transistor The source is grounded, the drain is connected to the gate thereof, the second branch includes a fourth transistor, a fifth transistor and a sixth transistor, the fourth transistor source is connected to the power source, the gate is connected to the drain thereof, and the drain and the fifth transistor are drained.
  • a fifth transistor is connected to the second input terminal, the source is connected to the sixth transistor drain; the sixth transistor source is grounded, the drain is connected to the gate; and the third branch includes the seventh transistor and the eighth transistor
  • the seventh transistor source is connected to the power source, the gate is connected to the nodes of the first transistor and the second transistor, the drain is connected to the voltage comparator output terminal and the eighth transistor drain, and the seventh transistor and the first transistor are configured.
  • the fourth branch includes a ninth transistor and a tenth transistor, the ninth transistor The source is connected to the power source, the gate is connected to the gate of the fourth transistor, the drain is connected to the drain of the tenth transistor, the gate of the tenth transistor is connected to the gate of the eighth transistor, the drain is connected to the gate thereof, and the source is grounded.
  • the voltage comparator further includes a first resistor, one end of the first resistor is connected to the second input end, and the other end is grounded.
  • the first transistor, the fourth transistor, the seventh transistor, and the ninth transistor are PMOS
  • the second transistor, the third transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor are NMOS.
  • one end of the first resistor is connected to the second input terminal, and the other end is connected to the power source.
  • the first transistor, the second transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the ninth transistor are PMOS, and the third transistor, the sixth transistor, the eighth transistor, and the tenth transistor are NMOS.
  • the voltage comparator provided by the embodiment of the present invention has the beneficial effects that: first, the circuit has a self-biasing capability without a special bias circuit; second, in the case of the same power supply voltage, static The power consumption is relatively low; third, the circuit has fewer power consumption branches and higher reliability under low power consumption.
  • FIG. 1 is a circuit diagram of a voltage comparator in the prior art
  • FIG. 2 is a circuit diagram of a voltage comparator according to Embodiment 1 of the present invention.
  • FIG. 3 is a circuit diagram of a voltage comparator according to Embodiment 2 of the present invention.
  • FIG. 4 is a circuit diagram of a voltage comparator according to Embodiment 3 of the present invention.
  • FIG. 5 is a circuit diagram of a voltage comparator according to Embodiment 4 of the present invention.
  • FIG. 6 is a circuit diagram of a voltage comparator according to Embodiment 5 of the present invention.
  • FIG. 7 is a circuit diagram of a voltage comparator according to Embodiment 6 of the present invention.
  • the present invention provides a voltage comparator including a first branch A1, a second branch A2, and a third branch A3.
  • the first branch includes a first transistor M1, a second transistor M2, and a first
  • the three transistor M3 has a source connected to the power source VDD, a gate connected to the drain thereof, and a drain connected to the drain of the second transistor M2.
  • the second transistor M2 is connected to the first input terminal VR, and the source is connected to the drain of the third transistor M3.
  • the third transistor M3 has a source connected to VSS and a drain connected to the gate.
  • the first branch A1 has a self-biasing function that does not require an external input bias signal to control its current level.
  • the current of the A1 branch is proportional to VR, because the higher the VR, the smaller the on-resistance of the second transistor M2, and the larger the current of the first branch A1.
  • the second branch A2 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the fourth transistor M has a source connected to the power supply VDD, a gate connected to the drain thereof, and a drain connected to the drain of the fifth transistor M5.
  • the fifth transistor M5 is connected to the second input terminal VIN, and the source is connected to the drain of the sixth transistor M6.
  • the sixth transistor M6 has a source connected to VSS and a drain connected to its gate.
  • the first branch A2 also has a self-biasing function whose current magnitude is proportional to VIN.
  • the third branch A3 includes a seventh transistor M7 and a eighth transistor M8.
  • the source of the seventh transistor M7 is connected to the power source VDD, and the gate is connected to the nodes of the first transistor M1 and the second transistor M2, and the drain and voltage comparator outputs are connected.
  • VO is connected to the drain of the eighth transistor M8, and the seventh transistor M7 and the first transistor M1 constitute a current mirror.
  • the gate of the eighth transistor M8 is connected to the nodes of the fifth transistor M5 and the sixth transistor M6, the drain is connected to the voltage comparator output terminal VO, the source is grounded to VSS, and the eighth transistor M8 and the sixth transistor M6 form a current mirror.
  • the voltage comparator further includes a first resistor R1.
  • One end of the first resistor R1 is connected to the second input terminal VIN, and the other end is grounded to VSS.
  • the first resistor R1 is used to pull VIN down to 0V when the second input terminal VIN is floating.
  • the first transistor M1, the fourth transistor M4, and the seventh transistor M7 are PMOS
  • the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are NMOS. .
  • the first transistor M1 If the voltage of VIN is 0, the first transistor M1 is turned off, and the current of the second branch A2 is 0; if VIN is left floating, the first resistor R1 pulls VIN down to 0V, and the second branch A2 still has 0 current.
  • VIN When VIN>0, the first resistor R1 will consume current from VIN, and when VIN turns M1 on, the current consumed by the second branch A2 will be proportional to VIN.
  • the extremely low static power consumption voltage comparator of the embodiment is applied to the power supply voltage detection of the portable electronic device.
  • the voltage comparator can only be realized when the external power supply is not turned on.
  • the first path A1 consumes current and the power consumption can be below 0.2uW.
  • the increased power consumption includes the current of the second branch A2, the current of the first resistor R1, and the current on M7 and M8. However, due to the presence of the external power supply, these increased power consumption Does not consume battery power.
  • the circuit when the circuit is in the working state, there are four power consumption branches (three branches of A1, A2, and A3 and a branch of the first resistor), and the current flowing through the whole circuit is 320nA, and the average flow flows through the A1 branch.
  • the current of the circuit is 80nA.
  • the circuit When the circuit is in static state, only the first branch A1 is turned on. Since the first branch A1 adopts a self-biased design, the current of the first branch A1 is still 80nA, and the other branch currents are 0, the static power consumption of the entire circuit is 80nA*VDD. In the case where VDD is the same, the static power consumption of the circuit of this embodiment is relatively low. At the same time, the circuit has fewer power consumption branches and higher reliability under low power consumption.
  • the voltage comparator in this embodiment is different from the first embodiment in that one end of the first resistor R1 is connected to the second input terminal VIN, and the other end is connected to the power source VDD.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are PMOS
  • the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are NMOS.
  • a voltage comparator disclosed in this embodiment includes a first branch A1, a second branch A2, and a third branch A3.
  • the first branch A1 includes a first transistor M1 and a second transistor. M2 And the third transistor M3, the source of the first transistor M1 is connected to the power source VDD, the gate is connected to the drain thereof, and the drain is connected to the drain of the second transistor M2.
  • the second transistor M2 is connected to the first input terminal VR, and the source is connected to the drain of the third transistor M3.
  • the third transistor M3 has a source connected to VSS and a drain connected to its gate.
  • the second branch A2 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the fourth transistor M4 has a source connected to the power supply VDD, a gate connected to the drain thereof, and a drain connected to the drain of the fifth transistor M5.
  • the fifth transistor M5 is connected to the second input terminal VIN, and the drain is connected to the drain of the sixth transistor M6.
  • the sixth transistor M6 has a source connected to VSS and a drain connected to its gate.
  • the third branch A3 includes a seventh transistor M7 and a eighth transistor M8.
  • the seventh transistor M7 is connected to the power source VDD, and the gate is connected to the nodes of the fourth transistor M4 and the fifth transistor M5, and the drain and voltage comparator outputs are connected.
  • VO is connected to the drain of the eighth transistor M8, and the seventh transistor M7 and the fourth transistor M4 form a current mirror.
  • the gate of the eighth transistor M8 is connected to the node of the second transistor M2 and the third transistor M3, the drain is connected to the voltage comparator output terminal VO, the source is grounded, and the eighth transistor M8 and the third transistor M3 form a current mirror.
  • the voltage comparator further includes a first resistor R1. One end of the first resistor R1 is connected to the second input terminal VIN, and the other end is grounded to VSS.
  • the first transistor M1, the fourth transistor M4, and the seventh transistor M7 are PMOS
  • the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are NMOS.
  • the difference from the first embodiment is that one end of the first resistor R1 is connected to the second input terminal VIN, and the other end is connected to the power source VDD.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7 are PMOS
  • the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are NMOS.
  • the embodiment of the present invention discloses a voltage comparator including a first branch A1, a second branch A2, a third branch A3, and a fourth branch A4.
  • the first branch A1 includes the first A transistor M1, a second transistor M2 and a third transistor M3, the source of the first transistor M1 is connected to the power supply VDD, the gate is connected to the drain thereof, and the drain is connected to the drain of the second transistor M2.
  • Gate of the second transistor M2 The first input terminal VR has a source connected to the drain of the third transistor M3.
  • the third transistor M3 has a source connected to VSS and a drain connected to its gate.
  • the second branch A2 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.
  • the fourth transistor M4 has a source connected to the power supply VDD, a gate connected to the drain thereof, and a drain connected to the drain of the fifth transistor M5.
  • the fifth transistor M5 is connected to the second input terminal VIN, and the source is connected to the drain of the sixth transistor M6.
  • the sixth transistor M6 has a source connected to the ground and a drain connected to the gate.
  • the third branch includes a seventh transistor M7 and a eighth transistor M8.
  • the source of the seventh transistor M7 is connected to the power source, the gate is connected to the node of the first transistor M1 and the second transistor M2, and the drain and the voltage comparator output terminal VO are
  • the eighth transistor M8 is connected to the drain, and the seventh transistor M7 and the first transistor M1 form a current mirror.
  • the drain of the eighth transistor M8 is connected to the voltage comparator output terminal VO, the source is grounded, and the node of the drains of the seventh transistor M7 and the eighth transistor M8 is the output terminal VO.
  • the fourth branch includes a ninth transistor M9 and a tenth transistor M10.
  • the ninth transistor M9 has a source connected to the power supply VDD, a gate connected to the fourth transistor M4, and a drain connected to the drain of the tenth transistor M10.
  • the gate of the tenth transistor M10 is connected to the gate of the eighth transistor M8, the drain is connected to its gate, and the source is grounded to VSS.
  • the voltage comparator further includes a first resistor R1.
  • One end of the first resistor R1 is connected to the second input terminal VIN, and the other end is grounded to VSS.
  • the first transistor M1, the fourth transistor M4, the seventh transistor M7, and the ninth transistor M9 are PMOS, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8.
  • the tenth transistor M10 is an NMOS.
  • the embodiment is different from the fifth embodiment in that one end of the first resistor R1 is connected to the second input terminal VIN, and the other end is connected to the power source VDD.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 are PMOS
  • the tenth transistor M10 is an NMOS.
  • the voltage comparator provided by the embodiment of the present invention has the beneficial effects that: first, the circuit has a self-biasing capability without a special bias circuit; second, in the case of the same power supply voltage, static The power consumption is relatively low; third, the circuit has fewer power consumption branches and higher reliability under low power consumption.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本发明适用于电子技术领域，提供了一种电压比较器，包括第一支路、第二支路和第三支路，第一支路和第二支路均具备自偏置能力，无需专门的偏置电路，在电源电压相同的情况下，静态功耗相对较低，电路的耗电支路少，低功耗下的可靠性高。

Description

电压比较器 技术领域
本发明涉及电子技术领域，尤其涉及一种低静态功耗的电压比较器。
背景技术
低功耗技术在便携式电子设备中已经受到越来越多的关注，例如，对于智能手机和平板电脑而言，静态功耗已经成为这些产品的关键指标。因为这些产品都是以电池作为供电电源，功耗的降低就意味着待机时间的增加、使用寿命的延长，最终会带给用户更好的使用体验。
如图1所示，图1给出了普通电压比较器电路，电路的功耗由尾电流源IB的大小决定。该电路的缺点有两个：第一，在被测电压VIN＝第一输入端VR的平衡状态下，IB将均匀的分布于M1和M2所在的支路，也就是说0.5*IB大小的电流就足够支持M2支路工作。但是，如果VIN导致M1完全关断，一般情况下IB将全部流过M2，很显然，多余的0.5*IB电流被浪费掉了。第二，尾电流源IB一般由NMOS管构成，需要额外的偏置电路来提供栅极电压，因此电路的实际功耗会更大。
中国专利CN201210242224.4的全差分高速低功耗比较器，其优点是输出摆率高，速度快，但其功耗高达56uW，并且这个功耗的数值还没有把比较器所需的偏置电路计算在内，所以实际电路的功耗会更大。又例如中国专利CN200910242582.3的低功耗反馈控制结构的时域比较器，其特点在于通过数字逻辑控制来降低静态功耗，但其功耗为9uW，并且这个功耗的数值还没有把比较器所需的数字时序电路计算在内，一样的实际电路的功耗会更大。再例如中国专利CN201010601379.3的电压比较器，其特点在于利用晶体管的亚阈值工作特性，以达到在保证一定电路延时的条件下，降低电路的功耗，其功耗为2uW；此外，虽然该电路可能具备自偏置能力，但是该比较器有四条耗电支路，因此如果希望将其工作电流降低至100nA以下，则平均每条支路 的功耗将低至25nA，电路的可靠性降低。
发明内容
本发明的主要目的在于提供一种电压比较器，不需要额外的偏置电路或者时钟，进一步降低了静态功耗。
为达以上目的，本发明提出一种电压比较器，包括第一支路、第二支路和第三支路，第一支路包括第一晶体管、第二晶体管和第三晶体管，第一晶体管源极连接电源，栅极与其漏极连接，漏极与第二晶体管漏极连接；第二晶体管栅极连接第一输入端，源极与第三晶体管漏极连接；第三晶体管源极接地，漏极与栅极连接；第二支路包括第四晶体管、第五晶体管和第六晶体管，第四晶体管源极连接电源，栅极与其漏极连接，漏极与第五晶体管漏极连接；第五晶体管栅极连接第二输入端，源极与第六晶体管漏极连接；第六晶体管源极接地，漏极与其栅极连接；第三支路包括第七晶体管和第八晶体管，第七晶体管源极连接电源，栅极与第一晶体管和第二晶体管的节点连接，漏极与电压比较器输出端和第八晶体管漏极连接，第七晶体管与第一晶体管构成电流镜；第八晶体管栅极与第五晶体管和第六晶体管的节点连接，漏极连接电压比较器输出端，源极接地，第八晶体管与第六晶体管构成电流镜。
其中，电压比较器还包括第一电阻，第一电阻一端与第二输入端连接，另一端接地。
优选地，第一晶体管、第四晶体管和第七晶体管为PMOS，第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
另一实施例中，第一电阻一端与第二输入端连接，另一端连接电源。
优选地，第一晶体管、第二晶体管、第四晶体管、第五晶体管和第七晶体管为PMOS，第三晶体管、第六晶体管和第八晶体管为NMOS。
本发明实施例还提供了一种电压比较器，包括第一支路、第二支路和第三支路，第一支路包括第一晶体管、第二晶体管和第三晶体管，第一晶体管源极连接电源，栅极与其漏极连接，漏极与第二晶体管漏极连接；第二晶体管栅极连接第一输入端，源极与第三晶体管漏极连接；第三晶体管源极接地，漏极与其栅极连接；第二支路包括第四晶体管、第五晶体管和第六晶体管， 第四晶体管源极连接电源，栅极与其漏极连接，漏极与第五晶体管漏极连接；第五晶体管栅极连接第二输入端，源极与第六晶体管漏极连接；第六晶体管源极接地，漏极与其栅极连接；第三支路包括第七晶体管和第八晶体管，第七晶体管源极连接电源，栅极与第四晶体管和第五晶体管的节点连接，漏极与电压比较器输出端和第八晶体管漏极连接，第七晶体管与第四晶体管构成电流镜；第八晶体管的栅极与第二晶体管和第三晶体管的节点连接，漏极连接电压比较器输出端，源极接地，第八晶体管与第三晶体管构成电流镜。
其中，电压比较器还包括第一电阻，第一电阻一端与第二输入端连接，另一端接地。
优选地，第一晶体管、第四晶体管和第七晶体管为PMOS，第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
另一实施例中，第一电阻一端与第二输入端连接，另一端接电源。
优选地，第一晶体管、第四晶体管和第七晶体管为PMOS，第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
本发明实施例还提供了一种电压比较器，包括第一支路、第二支路、第三支路和第四支路，第一支路包括第一晶体管、第二晶体管和第三晶体管，第一晶体管源极连接电源，栅极与其漏极连接，漏极与第二晶体管漏极连接；第二晶体管栅极接第一输入端，源极与第三晶体管漏极连接；第三晶体管源极接地，漏极与其栅极连接；第二支路包括第四晶体管、第五晶体管和第六晶体管，第四晶体管源极连接电源，栅极与其漏极连接，漏极与第五晶体管漏极连接；第五晶体管栅极连接第二输入端，源极与第六晶体管漏极连接；第六晶体管源极接地，漏极与栅极连接；第三支路包括第七晶体管和第八晶体管，第七晶体管源极连接电源，栅极与第一晶体管和第二晶体管的节点连接，漏极与电压比较器输出端和第八晶体管漏极连接，第七晶体管与第一晶体管构成电流镜；第八晶体管漏极连接电压比较器输出端，源极接地，第七晶体管和第八晶体管漏极的节点为输出端；第四支路包括第九晶体管和第十晶体管，第九晶体管源极连接电源，栅极与第四晶体管栅极连接，漏极与第十晶体管漏极连接；第十晶体管栅极与第八晶体管栅极连接，漏极与其栅极连接，源极接地。
其中，电压比较器还包括第一电阻，第一电阻一端与第二输入端连接，另一端接地。
优选地，第一晶体管、第四晶体管、第七晶体管和第九晶体管为PMOS，第二晶体管、第三晶体管、第五晶体管、第六晶体管、第八晶体管和第十晶体管为NMOS。
另一实施例中，第一电阻一端与第二输入端连接，另一端接电源。
优选地，第一晶体管、第二晶体管、第四晶体管、第五晶体管、第七晶体管和第九晶体管为PMOS，第三晶体管、第六晶体管、第八晶体管和第十晶体管为NMOS。
与现有技术相比，本发明实施例所提供的电压比较器，有益效果在于：第一，电路具备自偏置能力无需专门的偏置电路；第二，在电源电压相同的情况下，静态功耗相对较低；第三，电路的耗电支路少，低功耗下的可靠性高。
附图说明
图1为现有技术中的一种电压比较器电路图；
图2为本发明实施例一提供的一种电压比较器电路图；
图3为本发明实施例二提供的一种电压比较器电路图；
图4为本发明实施例三提供的一种电压比较器电路图；
图5为本发明实施例四提供的一种电压比较器电路图；
图6为本发明实施例五提供的一种电压比较器电路图；
图7为本发明实施例六提供的一种电压比较器电路图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
如图2所示，本发明提出一种电压比较器，包括第一支路A1、第二支路A2和第三支路A3，第一支路包括第一晶体管M1、第二晶体管M2和第三晶体管M3，第一晶体管M1源极连接电源VDD，栅极与其漏极连接，漏极与第二晶体管M2漏极连接。第二晶体管M2栅极连接第一输入端VR，源极与第三晶体管M3漏极连接。第三晶体管M3源极接地VSS，漏极与栅极连接。第一支路A1具有自偏置功能，无需外部输入偏置信号来控制其电流大小。A1支路的电流与VR成正比，这是因为VR越高，第二晶体管M2的导通电阻越小，第一支路A1的电流越大。
第二支路A2包括第四晶体管M4、第五晶体管M5和第六晶体管M6，第四晶体管M源极连接电源VDD，栅极与其漏极连接，漏极与第五晶体管M5漏极连接。第五晶体管M5栅极连接第二输入端VIN，源极与第六晶体管M6漏极连接。第六晶体管M6源极接地VSS，漏极与其栅极连接。同样的，第一支路A2也具有自偏置功能，其电流大小与VIN成正比。
第三支路A3包括第七晶体管M7和第八晶体管M8，第七晶体管M7源极连接电源VDD，栅极与第一晶体管M1和第二晶体管M2的节点连接，漏极与电压比较器输出端VO和第八晶体管M8漏极连接，第七晶体管M7与第一晶体管M1构成电流镜。第八晶体管M8栅极与第五晶体管M5和第六晶体管M6的节点连接，漏极连接电压比较器输出端VO，源极接地VSS，第八晶体管M8与第六晶体管M6构成电流镜。
本实施例中，当VIN<VR时，M7镜像的电流大于M8镜像的电流，输出VO为高电平；当VIN>VR时，M7镜像的电流小于M8镜像的电流，输出VO为低电平。
进一步地，电压比较器还包括第一电阻R1，第一电阻R1一端与第二输入端VIN连接，另一端接地VSS。第一电阻R1用于在第二输入端VIN悬空时，将VIN下拉至0V。优选地，本实施例中第一晶体管M1、第四晶体管M4和第七晶体管M7为PMOS，第二晶体管M2、第三晶体管M3、第五晶体管M5、第六晶体管M6和第八晶体管M8为NMOS。
假设VR为参考电压，VIN为被测电压，通过VR的电压值以及M2、M4和M6的尺寸设计，可实现当VDD＝2.5V时，将第一支路A1的功耗设计为低 至80nA以下。
若VIN的电压为0，则第一晶体管M1截止，第二支路A2电流为0；若VIN悬空，则第一电阻R1将VIN下拉至0V，第二支路A2电流依然为0。当VIN>0时，第一电阻R1将从VIN消耗电流，并且当VIN使M1导通后，第二支路A2消耗的电流将与VIN成正比。
当VIN＝0V或悬空时，第二支路A2的电流为0，因此M8镜像M3的电流也为0；若此时VR为参考电压，并且VDD＝2.5V时，第一支路A1的功耗低至80nA以下，那么虽然M7镜像M6的电流，但是M7的电流必须流经M8，而此时M8的电流为0，因此M7的电流也被强制为0。所以，此时本实施例电压比较器的最低静态功耗可以在0.2uW以下。
本实施例的极低静态功耗的电压比较器应用于便携式电子设备的电源电压检测中，VR接电池电源，VIN接外部电源，则可以实现当外部电源未接通时，电压比较器仅仅有第一支路A1消耗电流，且功耗可以在0.2uW以下。当有外部电源接入时，增加的功耗部分包括第二支路A2的电流、第一电阻R1的电流、M7和M8上的电流，然而此时由于外部电源的存在，这些增加的耗电都不会消耗电池的电量。本实施例中，电路处于工作状态时有四条耗电支路(A1、A2、A3三条支路+第一电阻所在的支路)，流过整个电路的电流为320nA，平均后流过A1支路的电流为80nA，电路处于静态时，只有第一支路A1导通，由于第一支路A1采用的是自偏置设计，第一支路A1的电流仍为80nA，其他支路电流为0，整个电路的静态功耗为80nA*VDD。在VDD相同的情况下，本实施例电路的静态功耗相对较低。同时，电路的耗电支路少，低功耗下的可靠性高。
实施例二
如图3所示，本实施例中电压比较器与实施例一不同之处在于，第一电阻R1一端与第二输入端VIN连接，另一端连接电源VDD。本实施例中第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5和第七晶体管M7为PMOS，第三晶体管M3、第六晶体管M6和第八晶体管M8为NMOS。
实施例三
如图4所示，本实施例公开的一种电压比较器，包括第一支路A1、第二支路A2和第三支路A3，第一支路A1包括第一晶体管M1、第二晶体管M2 和第三晶体管M3，第一晶体管M1源极连接电源VDD，栅极与其漏极连接，漏极与第二晶体管M2漏极连接。第二晶体管M2栅极连接第一输入端VR，源极与第三晶体管M3漏极连接。第三晶体管M3源极接地VSS，漏极与其栅极连接。
第二支路A2包括第四晶体管M4、第五晶体管M5和第六晶体管M6，第四晶体管M4源极连接电源VDD，栅极与其漏极连接，漏极与第五晶体管M5漏极连接。第五晶体管M5栅极连接第二输入端VIN，漏极与第六晶体管M6漏极连接。第六晶体管M6源极接地VSS，漏极与其栅极连接。
第三支路A3包括第七晶体管M7和第八晶体管M8，第七晶体管M7源极连接电源VDD，栅极与第四晶体管M4和第五晶体管M5的节点连接，漏极与电压比较器输出端VO和第八晶体管M8漏极连接，第七晶体管M7与第四晶体管M4构成电流镜。第八晶体管M8的栅极与第二晶体管M2和第三晶体管M3的节点连接，漏极连接电压比较器输出端VO，源极接地，第八晶体管M8与第三晶体管M3构成电流镜。
进一步地，电压比较器还包括第一电阻R1，第一电阻R1一端与第二输入端VIN连接，另一端接地VSS。
本实施例中第一晶体管M1、第四晶体管M4和第七晶体管M7为PMOS，第二晶体管M2、第三晶体管M3、第五晶体管M5、第六晶体管M6和第八晶体管M8为NMOS。
实施例四
如图5所示，与实施例一不同之处在于，第一电阻R1一端与第二输入端VIN连接，另一端连接电源VDD。本实施例中第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5和第七晶体管M7为PMOS，第三晶体管M3、第六晶体管M6和第八晶体管M8为NMOS。
实施例五
如图6所示，本发明实施例公开了一种电压比较器，包括第一支路A1、第二支路A2、第三支路A3和第四支路A4，第一支路A1包括第一晶体管M1、第二晶体管M2和第三晶体管M3，第一晶体管M1源极连接电源VDD，栅极与其漏极连接，漏极与第二晶体管M2漏极连接。第二晶体管M2栅极接 第一输入端VR，源极与第三晶体管M3漏极连接。第三晶体管M3源极接地VSS，漏极与其栅极连接。
第二支路A2包括第四晶体管M4、第五晶体管M5和第六晶体管M6，第四晶体管M4源极连接电源VDD，栅极与其漏极连接，漏极与第五晶体管M5漏极连接。第五晶体管M5栅极连接第二输入端VIN，源极与第六晶体管M6漏极连接。第六晶体管M6源极接地，漏极与栅极连接。
第三支路包括第七晶体管M7和第八晶体管M8，第七晶体管M7源极连接电源，栅极与第一晶体管M1和第二晶体管M2的节点连接，漏极与电压比较器输出端VO和第八晶体管M8漏极连接，第七晶体管M7与第一晶体管M1构成电流镜。第八晶体管M8漏极连接电压比较器输出端VO，源极接地，第七晶体管M7和第八晶体管M8漏极的节点为输出端VO。
第四支路包括第九晶体管M9和第十晶体管M10，第九晶体管M9源极连接电源VDD，栅极与第四晶体管M4栅极连接，漏极与第十晶体管M10漏极连接。第十晶体管M10栅极与第八晶体管M8栅极连接，漏极与其栅极连接，源极接地VSS。
进一步地，电压比较器还包括第一电阻R1，第一电阻R1一端与第二输入端VIN连接，另一端接地VSS。本实施例中第一晶体管M1、第四晶体管M4、第七晶体管M7和第九晶体管M9为PMOS，第二晶体管M2、第三晶体管M3、第五晶体管M5、第六晶体管M6、第八晶体管M8和第十晶体管M10为NMOS。
实施例六
如图7所示，本实施例与实施例五不同之处在于，第一电阻R1一端与第二输入端VIN连接，另一端接电源VDD。本实施例中第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5、第七晶体管M7和第九晶体管M9为PMOS，第三晶体管M3、第六晶体管M6、第八晶体管M8和第十晶体管M10为NMOS。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
工业实用性
与现有技术相比，本发明实施例所提供的电压比较器，有益效果在于：第一，电路具备自偏置能力无需专门的偏置电路；第二，在电源电压相同的情况下，静态功耗相对较低；第三，电路的耗电支路少，低功耗下的可靠性高。

Claims (15)

  1. 一种电压比较器，包括第一支路、第二支路和第三支路，所述第一支路包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管源极连接电源，栅极与其漏极连接，漏极与所述第二晶体管漏极连接；所述第二晶体管栅极连接第一输入端，源极与第三晶体管漏极连接；第三晶体管源极接地，漏极与栅极连接；所述第二支路包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管源极连接电源，栅极与其漏极连接，漏极与所述第五晶体管漏极连接；所述第五晶体管栅极连接第二输入端，源极与第六晶体管漏极连接；所述第六晶体管源极接地，漏极与其栅极连接；所述第三支路包括第七晶体管和第八晶体管，所述第七晶体管源极连接电源，栅极与所述第一晶体管和第二晶体管的节点连接，漏极与电压比较器输出端和所述第八晶体管漏极连接，所述第七晶体管与所述第一晶体管构成电流镜；所述第八晶体管栅极与所述第五晶体管和第六晶体管的节点连接，漏极连接电压比较器输出端，源极接地，所述第八晶体管与所述第六晶体管构成电流镜。
  2. 根据权利要求1所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端接地。
  3. 根据权利要求2所述的电压比较器，其中，所述第一晶体管、第四晶体管和第七晶体管为PMOS，所述第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
  4. 根据权利要求1所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端连接电源。
  5. 根据权利要求4所述的电压比较器，其中，所述第一晶体管、第二晶体管、第四晶体管、第五晶体管和第七晶体管为PMOS，所述第三晶体管、第六晶体管和第八晶体管为NMOS。
  6. 一种电压比较器，其中，包括第一支路、第二支路和第三支路，所述第一支路包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管源极连接电源，栅极与其漏极连接，漏极与所述第二晶体管漏极连接；所述第二晶体管栅极连接第一输入端，源极与所述第三晶体管漏极连接；所述第三晶 体管源极接地，漏极与其栅极连接；所述第二支路包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管源极连接电源，栅极与其漏极连接，漏极与所述第五晶体管漏极连接；所述第五晶体管栅极连接第二输入端，源极与所述第六晶体管漏极连接；所述第六晶体管源极接地，漏极与其栅极连接；所述第三支路包括第七晶体管和第八晶体管，所述第七晶体管源极连接电源，栅极与所述第四晶体管和第五晶体管的节点连接，漏极与电压比较器输出端和所述第八晶体管漏极连接，所述第七晶体管与所述第四晶体管构成电流镜；所述第八晶体管的栅极与所述第二晶体管和第三晶体管的节点连接，漏极连接电压比较器输出端，源极接地，所述第八晶体管与所述第三晶体管构成电流镜。
  7. 根据权利要求6所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端接地。
  8. 根据权利要求7所述的电压比较器，其中，所述第一晶体管、第四晶体管和第七晶体管为PMOS，所述第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
  9. 根据权利要求6所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端接电源。
  10. 根据权利要求9所述的电压比较器，其中，所述第一晶体管、第四晶体管和第七晶体管为PMOS，所述第二晶体管、第三晶体管、第五晶体管、第六晶体管和第八晶体管为NMOS。
  11. 一种电压比较器，其中，包括第一支路、第二支路、第三支路和第四支路，所述第一支路包括第一晶体管、第二晶体管和第三晶体管，所述第一晶体管源极连接电源，栅极与其漏极连接，漏极与所述第二晶体管漏极连接；所述第二晶体管栅极接第一输入端，源极与所述第三晶体管漏极连接；所述第三晶体管源极接地，漏极与其栅极连接；所述第二支路包括第四晶体管、第五晶体管和第六晶体管，所述第四晶体管源极连接电源，栅极与其漏极连接，漏极与所述第五晶体管漏极连接；所述第五晶体管栅极连接第二输入端，源极与所述第六晶体管漏极连接；所述第六晶体管源极接地，漏极与 栅极连接；所述第三支路包括第七晶体管和第八晶体管，所述第七晶体管源极连接电源，栅极与所述第一晶体管和第二晶体管的节点连接，漏极与电压比较器输出端和所述第八晶体管漏极连接，所述第七晶体管与所述第一晶体管构成电流镜；所述第八晶体管漏极连接电压比较器输出端，源极接地，所述第七晶体管和所述第八晶体管漏极的节点为输出端；所述第四支路包括第九晶体管和第十晶体管，所述第九晶体管源极连接电源，栅极与所述第四晶体管栅极连接，漏极与所述第十晶体管漏极连接；所述第十晶体管栅极与所述第八晶体管栅极连接，漏极与其栅极连接，源极接地。
  12. 根据权利要求11所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端接地。
  13. 根据权利要求12所述的电压比较器，其中，所述第一晶体管、第四晶体管、第七晶体管和第九晶体管为PMOS，所述第二晶体管、第三晶体管、第五晶体管、第六晶体管、第八晶体管和第十晶体管为NMOS。
  14. 根据权利要求11所述的电压比较器，其中，还包括第一电阻，所述第一电阻一端与第二输入端连接，另一端接电源。
  15. 根据权利要求14所述的电压比较器，其中，所述第一晶体管、第二晶体管、第四晶体管、第五晶体管、第七晶体管和第九晶体管为PMOS，所述第三晶体管、第六晶体管、第八晶体管和第十晶体管为NMOS。
PCT/CN2014/088469 2014-04-28 2014-10-13 电压比较器 Ceased WO2015165218A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP14891116.7A EP3096454B1 (en) 2014-04-28 2014-10-13 Voltage comparator
KR1020167018348A KR101826456B1 (ko) 2014-04-28 2014-10-13 전압 비교기
US15/203,796 US9742387B2 (en) 2014-04-28 2016-07-07 Voltage comparator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410174425.4A CN104158516B (zh) 2014-04-28 2014-04-28 电压比较器
CN201410174425.4 2014-04-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/203,796 Continuation US9742387B2 (en) 2014-04-28 2016-07-07 Voltage comparator

Publications (1)

Publication Number Publication Date
WO2015165218A1 true WO2015165218A1 (zh) 2015-11-05

Family

ID=51883944

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088469 Ceased WO2015165218A1 (zh) 2014-04-28 2014-10-13 电压比较器

Country Status (5)

Country Link
US (1) US9742387B2 (zh)
EP (1) EP3096454B1 (zh)
KR (1) KR101826456B1 (zh)
CN (1) CN104158516B (zh)
WO (1) WO2015165218A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117278004A (zh) * 2023-11-21 2023-12-22 拓尔微电子股份有限公司 比较电路

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109379074A (zh) * 2018-11-21 2019-02-22 灿芯半导体(上海)有限公司 一种电平转换电路
CN110445482B (zh) * 2019-08-06 2020-11-27 电子科技大学 一种低功耗高摆率的比较器
CN113364278B (zh) * 2020-04-08 2022-07-12 澜起电子科技(昆山)有限公司 开关电流源电路及开关电流源快速建立方法
CN114448424B (zh) * 2022-01-14 2023-05-23 电子科技大学 一种自带偏置的低电压比较器
CN116094501B (zh) 2022-09-09 2025-09-16 深圳市汇顶科技股份有限公司 基于运放的迟滞比较器和芯片
CN115622534B (zh) * 2022-12-20 2023-03-14 苏州贝克微电子股份有限公司 一种提高运算放大器阻抗的结构及方法
CN116032217A (zh) * 2022-12-23 2023-04-28 上海类比半导体技术有限公司 振荡器结构及包括振荡器结构的模数转换系统
CN117792351A (zh) * 2023-12-20 2024-03-29 思瑞浦微电子科技(上海)有限责任公司 比较器电路和组合比较器电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511537B2 (en) * 2006-11-07 2009-03-31 Freescale Semiconductor, Inc. Comparator circuit for reducing current consumption by suppressing glitches during a transitional period
CN102571044A (zh) * 2010-12-22 2012-07-11 无锡华润上华半导体有限公司 电压比较器
CN102769447A (zh) * 2012-07-12 2012-11-07 东南大学 全差分高速低功耗比较器
US20130194039A1 (en) * 2012-01-30 2013-08-01 Semiconductor Technology Academic Research Center Differential amplifier circuit with ultralow power consumption provided with adaptive bias current generator circuit
JP2013187695A (ja) * 2012-03-07 2013-09-19 Sony Corp コンパレータおよびａｄ変換器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146613A (ja) * 1984-08-10 1986-03-06 Nec Corp レベル検出回路
US4818897A (en) * 1987-09-25 1989-04-04 Texas Instruments Incorporated Fast one way amplifier stage
JP2002084145A (ja) 2000-09-08 2002-03-22 Nec Corp Ｍｏｓ線形トランスコンダクタンスアンプ
JP5117950B2 (ja) 2008-07-18 2013-01-16 ラピスセミコンダクタ株式会社 データ読出回路及び半導体記憶装置
CN101764613B (zh) * 2009-12-18 2012-05-16 清华大学 低功耗反馈控制结构的时域比较器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511537B2 (en) * 2006-11-07 2009-03-31 Freescale Semiconductor, Inc. Comparator circuit for reducing current consumption by suppressing glitches during a transitional period
CN102571044A (zh) * 2010-12-22 2012-07-11 无锡华润上华半导体有限公司 电压比较器
US20130194039A1 (en) * 2012-01-30 2013-08-01 Semiconductor Technology Academic Research Center Differential amplifier circuit with ultralow power consumption provided with adaptive bias current generator circuit
JP2013187695A (ja) * 2012-03-07 2013-09-19 Sony Corp コンパレータおよびａｄ変換器
CN102769447A (zh) * 2012-07-12 2012-11-07 东南大学 全差分高速低功耗比较器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117278004A (zh) * 2023-11-21 2023-12-22 拓尔微电子股份有限公司 比较电路
CN117278004B (zh) * 2023-11-21 2024-02-06 拓尔微电子股份有限公司 比较电路

Also Published As

Publication number Publication date
US9742387B2 (en) 2017-08-22
EP3096454B1 (en) 2020-02-26
CN104158516B (zh) 2017-01-11
EP3096454A1 (en) 2016-11-23
US20160315604A1 (en) 2016-10-27
KR20160096676A (ko) 2016-08-16
EP3096454A4 (en) 2018-03-21
CN104158516A (zh) 2014-11-19
KR101826456B1 (ko) 2018-02-06

Similar Documents

Publication Publication Date Title
WO2015165218A1 (zh) 电压比较器
CN108649939A (zh) 电源检测电路及方法
US8159302B2 (en) Differential amplifier circuit
TWI470929B (zh) 電力開啓重置電路
JP2007026337A (ja) 電圧レギュレータ
EP3462274B1 (en) Semiconductor devices for sensing voltages
CN104113211B (zh) 一种应用于能量获取系统的低功耗迟滞电压检测电路
CN106656148A (zh) 一种防止电流倒灌的双向io电路
JP2011086989A (ja) パワーオンリセット回路
CN101312343A (zh) 用于在低电压域断电时防止电流泄漏的设备和方法
WO2016098593A1 (ja) 電源監視回路、パワーオンリセット回路、および半導体装置
CN204089754U (zh) 一种小面积低功耗高速电流比较器
CN105763177B (zh) 一种迟滞比较器
CN109975600A (zh) 一种零静态功耗的欠压检测电路
JP6288822B2 (ja) 半導体回路内の電力を制御するためのシステムおよび方法
CN114144742A (zh) 跨域功率控制电路
JP5468882B2 (ja) Ｃｍｏｓ入力バッファ回路
TW201214952A (en) Differential amplifier
US7804329B2 (en) Internal charge transfer for circuits
CN110580096A (zh) 一种可降低功耗的微控制单元及其控制方法
JP2005164357A (ja) 電圧検出回路
WO2021135661A1 (zh) 一种掉电检测电路
JP5603479B2 (ja) Ｃｍｏｓ入力バッファ回路
CN119675641B (zh) 一种低功耗上电复位电路
JP2006352204A (ja) 電位検出回路及びそれを備える半導体集積回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14891116

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20167018348

Country of ref document: KR

Kind code of ref document: A

REEP Request for entry into the european phase

Ref document number: 2014891116

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014891116

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE