WO2019041840A1 - 一种存储单元和静态随机存储器 - Google Patents

一种存储单元和静态随机存储器 Download PDF

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Publication number
WO2019041840A1
WO2019041840A1 PCT/CN2018/084100 CN2018084100W WO2019041840A1 WO 2019041840 A1 WO2019041840 A1 WO 2019041840A1 CN 2018084100 W CN2018084100 W CN 2018084100W WO 2019041840 A1 WO2019041840 A1 WO 2019041840A1
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Prior art keywords
read
mos transistor
line
bit
word line
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Ceased
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PCT/CN2018/084100
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English (en)
French (fr)
Inventor
池思杰
季秉武
赵坦夫
周云明
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to KR1020207008686A priority Critical patent/KR20200041989A/ko
Priority to KR1020227025331A priority patent/KR20220108197A/ko
Priority to EP18849945.3A priority patent/EP3667669B1/en
Priority to JP2020512869A priority patent/JP6919950B2/ja
Publication of WO2019041840A1 publication Critical patent/WO2019041840A1/zh
Priority to US16/807,594 priority patent/US11004502B2/en
Anticipated expiration legal-status Critical
Priority to US17/226,614 priority patent/US11475943B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of storage, and in particular, to a storage unit and a static random access memory (SRAM).
  • SRAM static random access memory
  • FIG. 1 is a schematic structural diagram of a memory cell of a conventional SRAM.
  • the memory cell adopts an ordinary six-tube unit composed of six metal oxide semiconductor (MOS) field effect transistors, and the MOS field effect transistor is simply referred to as a MOS transistor.
  • the memory cell includes two inverting gates and two MOS transistors. Among them, two inverting gates are composed of four MOS tubes, and two inverting gates in the figure constitute a latch for storing data, and two MOS tubes in the figure are used for gated access. There are two stable states, 0 and 1, for the latch connected by two inverting gate loops. Wherein, A and B are two oppositely stored memory bits.
  • bit_line WL
  • bit line bit_line, BL
  • Read Pull WL high and read the bit from BL.
  • Write Pull WL high, pull high or pull BL low, because BL's driving ability is stronger than the memory unit, it will force to cover the original state.
  • both bit and nbit represent bit lines, bit line bits are used to read the data of the memory bit A, and bit line nbit is used to read the data of the memory bit B, and the data of the memory cells read by the two are opposite.
  • FIG. 2 is a schematic diagram of a conventional SRAM memory array.
  • the memory array includes 3 x 3 of memory cells as shown in FIG.
  • Embodiments of the present invention provide a storage unit and a static random access memory, which can implement reading of a read word line and a read bit line, thereby being able to acquire data of a certain address with respect to a diagonally symmetric address of the matrix, which is fast. And power consumption and workload are low.
  • a memory unit including a latch, the latch providing a first memory bit; the memory unit further comprising a first MOS transistor; a gate of the first MOS transistor The first storage bit is connected to the first storage bit, the source of the first MOS transistor is connected to the first read line, and the drain of the first MOS transistor is connected to the second read line; in the first state, the first a read line is a read word line, and the second read line is a read bit line; in the second state, the second read line is a read word line, and the first read line is Read the bit line.
  • a MOS transistor is added, and a gate of the MOS transistor is connected to a storage bit, and a source and a drain of the MOS transistor are respectively connected to the first
  • the read line and the second read line are based on the characteristics of the MOS transistor itself, and any one of the first read line and the second read line can be used as a read bit line, and the other is used as a read word line, thereby realizing
  • the read word line and the read bit line are interchangeable, and by changing the bottommost hardware storage unit, it is possible to quickly acquire data of a certain address with respect to a diagonally symmetric address of the matrix, instead of writing an algorithm at the code level,
  • writing algorithms in the code of a digital circuit can greatly increase the speed and greatly reduce power consumption and workload, usually one to two beats (clock cycle), and digital circuit code Implementation may take thousands of beats.
  • the first MOS transistor is an NMOS transistor or a PMOS transistor.
  • the latch further provides a second storage bit;
  • the storage unit further includes a second MOS transistor; a gate of the second MOS transistor is connected to the second storage bit, A source of the second MOS transistor is connected to the first read line, and a drain of the second MOS transistor is connected to the second read line.
  • the data of the two storage bits having the opposite states are respectively read by the pair of MOS transistors, so that the accuracy of reading the data can be improved.
  • the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor; or the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor .
  • a static random access memory comprising: a plurality of memory cells; the memory cell comprising a latch, the latch providing a first memory bit; the memory cell further comprising a first MOS transistor; a gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second Reading the line; in the first state, the first read line is a read word line, the second read line is a read bit line; in the second state, the second read line is Reading a word line, the first read line is a read bit line; the plurality of memory cells form a rectangular memory array having the same number of rows and columns; the memory cells of the same row in the memory array are connected to the same The first read line; the memory cells of the same column in the memory array are connected to the same second read line.
  • a memory cell of a static random access memory is based on a structure of a conventional latch capable of providing a memory bit, and a MOS transistor is added, and a gate of the MOS transistor is connected to a memory bit, and a source of the MOS transistor The drains are respectively connected to the first read line and the second read line. Based on the characteristics of the MOS transistor itself, any one of the first read line and the second read line can be used as the read bit line, and the other is read.
  • the word line is taken to realize the interchangeability between the read word line and the read bit line, and the bottommost hardware storage unit is changed to quickly acquire data of a certain address about the diagonal symmetric address of the matrix, instead of the code.
  • the layer write algorithm which is equivalent to a hardware accelerator, can greatly increase the speed and greatly reduce the power consumption and workload compared to writing algorithms in the code of digital circuits, usually one to two beats (clock cycle). This is done, and digital circuit code implementations may require thousands of beats.
  • the first MOS transistor is an NMOS transistor or a PMOS transistor.
  • the latch further provides a second storage bit;
  • the storage unit further includes a second MOS transistor; a gate of the second MOS transistor is connected to the second storage bit, A source of the second MOS transistor is connected to the first read line, and a drain of the second MOS transistor is connected to the second read line.
  • the data of the two storage bits having the opposite states are respectively read by the pair of MOS transistors, so that the accuracy of reading the data can be improved.
  • the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor; or the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor .
  • each of the storage units is connected to a control signal; when the control signal is a first sequence, the storage unit is regarded as the first state; when the control signal In the second sequence, the memory unit is considered to be the second state. According to this embodiment, switching of the read state of the memory cell of the static random access memory by the control signal is simple and fast.
  • the first sequence has a length of 1 bit; the second sequence has a length of 1 bit; the first sequence is 0 and the second sequence is 1, or the A sequence is 1 and the second sequence is 0.
  • switching of the read state of the memory cells of the static random access memory by the 1-bit control signal is simple and fast.
  • the static random access memory further includes: a first decoder, a second decoder, a first word line driver, a second word line driver, a first sense amplifier, and a second sense amplifier And an inverter; the control signal is coupled to an enable end of the first decoder, an enable end of the first word line driver, and an enable end of the first sense amplifier; the first decoding The input end of the device inputs an address value, the first output end of the first decoder outputs a line number, and the second output end of the first decoder outputs a column number; the first output end of the first decoder is connected a control end of the first sense amplifier, an input end of the first sense amplifier is connected to the first read line; a second output end of the first decoder is connected to the first word line driver a control terminal, an output end of the first word line driver is connected to the second read line, and a control end of the first sense amplifier is configured to control the first sense amplifier to amplify data of at least one input
  • two sets of decoders, word line drivers and sense amplifiers are provided, and the connections of the two sets of decoders, word line drivers and sense amplifiers are different, and a set of decoders and word line drivers are controlled by the control signals.
  • the sense amplifier works to achieve the interchange of the read word line and the read bit line.
  • the static random access memory further includes: a decoder, a word line driver, a sense amplifier, the same number of first selectors as the number of rows of the storage array, and the storage array The number of columns is the same number of second selectors; the input of the decoder inputs an address value, the first output of the decoder outputs a line number, and the second output of the decoder outputs a column number; the decoding The first output end of the device is connected to the control end of the word line driver, and the control end of the word line driver is configured to control at least one output end of the word line driver to output a first logic state, the second of the decoder An output terminal is connected to the control terminal of the sense amplifier, and a control terminal of the sense amplifier is configured to control the sense amplifier to amplify data of at least one input terminal; the control signal is connected to the first selector and a control end of the second selector; a first port of the first selector is connected to the first read line, a second
  • a chip comprising: the static random access memory of the second aspect above.
  • the chip is used for convolution kernel decomposition in a convolutional neural network.
  • FIG. 1 is a schematic structural diagram of a memory cell of a conventional SRAM
  • FIG. 2 is a schematic diagram of a storage array of a conventional SRAM
  • FIG. 3 is a schematic structural diagram of a storage unit of an SRAM according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another storage unit of an SRAM according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another storage unit of an SRAM according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of reading a storage unit during a conventional reading according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of reading a storage array during conventional reading according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of reading a storage unit during a read sequence according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of reading a storage array during a read sequence according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a control circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of another control circuit according to an embodiment of the present invention.
  • Figure 12 is a schematic diagram of an image matrix and a convolution kernel matrix
  • Figure 13 is a schematic diagram of convolution calculation between a 5 x 5 image matrix and a 3 x 3 convolution kernel matrix.
  • Embodiments of the present invention provide a memory unit including a latch, the latch providing a first storage bit; the memory unit further includes a first MOS transistor; and the first MOS transistor a gate is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line; in the first state, the The first read line is a read word line, and the second read line is a read bit line; in the second state, the second read line is a read word line, the first read line To read the bit line.
  • the latch may be, but not limited to, a latch formed by cyclically connecting two inverting gates. Based on the latches included in a typical memory cell, the original bit lines and word lines corresponding to the latch are no longer used to read data.
  • the first MOS transistor can be an NMOS transistor or a PMOS transistor.
  • the latch further provides a second memory bit;
  • the memory cell further includes a second MOS transistor; a gate of the second MOS transistor is coupled to the second memory bit, the second MOS A source of the tube is coupled to the first read line, and a drain of the second MOS tube is coupled to the second read line.
  • the data of the two storage bits having the opposite states are respectively read by the pair of MOS transistors, so that the accuracy of reading the data can be improved.
  • the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor; or the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.
  • a MOS transistor is added, and a gate of the MOS transistor is connected to a storage bit, and a source and a drain of the MOS transistor are respectively connected to the first
  • the read line and the second read line are based on the characteristics of the MOS transistor itself, and any one of the first read line and the second read line can be used as a read bit line, and the other is used as a read word line, thereby realizing
  • the read word line and the read bit line are interchangeable, and by changing the bottommost hardware storage unit, it is possible to quickly acquire data of a certain address with respect to a diagonally symmetric address of the matrix, instead of writing an algorithm at the code level,
  • writing algorithms in the code of a digital circuit can greatly increase the speed and greatly reduce power consumption and workload, usually one to two beats (clock cycle), and digital circuit code Implementation may take thousands of beats.
  • FIG. 3 is a schematic structural diagram of a storage unit of an SRAM according to an embodiment of the present invention. If the two reverse gates are designed according to the structure of the four MOS tubes of the prior art, the memory unit in the embodiment of the present invention can be regarded as a 7-tube unit, and one of the conventional 6-tube units is added.
  • the MOS tube in the circle as shown in the figure makes the SRAM have two modes of conventional reading and sequential reading.
  • the structure of the memory cell shown in FIG. 3 is specifically described below.
  • the memory cell includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor 31, and a sixth MOS tube 32 (fifth MOS tube, sixth MOS tube is also called write MOS tube) and seventh MOS tube 33;
  • the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are not shown in FIG. 3, and the first MOS transistor and the second MOS transistor constitute a first inversion gate 34, The third MOS transistor and the fourth MOS transistor constitute a second inverting gate 35; the first inverting gate 34 and the second inverting gate 35 are connected end to end to form a latch, the first counter
  • the output of the phase gate 34 is the first storage bit Q
  • the output of the second inverter gate 35 is the second storage bit.
  • WWL write word line
  • WBL write bit line negate
  • the first write bit line is denoted as WBL
  • the second write bit line is denoted as WBLN
  • the fifth MOS transistor 31 and the sixth MOS transistor are made through the write word line 32 is turned on, for example, the write word line WWL is logic 1
  • the logic state of the first write bit line WBL is a logic state of the data
  • the data is written into the second memory bit
  • the logic state of the second write bit line WBLN is the logic state of the data, the data is written into the first storage bit Q;
  • the first state and the second state are only used to distinguish two different read states, and the first state and the second state are not limited in the embodiment of the present invention.
  • the first read line in the first state, is a read word line, the second read line is a read bit line; in the second state, the second read line is a read a word line, the first read line being a read bit line.
  • the second read line is a read word line, the first read line is a read bit line; in the second state, the first read line is a read A word line is taken, and the second read line is a read bit line.
  • a gate of the seventh MOS transistor 33 is connected to the first storage bit Q and the second storage bit
  • One of the storage bits, one of the source and the drain of the seventh MOS transistor 33 is connected to the first read line L1, and the other of the source and the drain of the seventh MOS transistor 33 is connected a second read line L2;
  • the first read line L1 is a read bit line (RBL_H, wherein H is used to identify the first read state, first The read state may be referred to as a first state
  • the second read line L2 is a read word line (RWL_H);
  • the first read line L1 is Reading a word line (RWL_V, wherein V is used to identify a second read state, the second read state may be simply referred to as a second state), and the second read line L2 is a read bit line (RBL_V);
  • the read word line RWL_H or RWL_V
  • the first read state may be referred to as a conventional read
  • the second read state may be referred to as a sequential read.
  • WBL and WBLN are two positive and negative write bit lines for writing stored data; WWL is a write word for gated access when writing data; RBL_H is a read bit line for conventional reading, for Read the stored data; RWL_H is the read word line for the conventional read, and is used to read the gated access when the data is stored; RWL_V is the read word line when the read data is read, and is used to read the stored data.
  • RBL_V is the read bit line when reading in reverse order, used to read the stored data
  • the read bit line in the traditional read is the read word line when the read is read, in the traditional read
  • the read word line is the read bit line when it is read in sequence
  • Q For the storage bit.
  • the peripheral circuit can be set with a 1-bit control signal, such as T_EN, and the read mode is controlled by T_EN for conventional read or sequential read.
  • the seventh MOS transistor 33 is an NMOS transistor.
  • the seventh MOS transistor 33 of FIG. 3 can also be replaced with a PMOS transistor, such as the memory cell shown in FIG.
  • a MOS transistor such as the memory cell shown in FIG. 5, may be added to the memory cell shown in FIG. 3 or FIG.
  • the memory unit further includes an eighth MOS transistor 36; a gate of the eighth MOS transistor 36 is connected to the first storage bit Q and the second storage bit Another memory bit (for example, when the seventh MOS transistor 33 is connected to the first memory bit Q, the eighth MOS transistor 36 is connected to the second memory bit One of the source and the drain of the eighth MOS transistor 36 is connected to the first read line L1, and the other of the source and the drain of the eighth MOS transistor 36 is connected to the a second read line L2 (for example, a source of the eighth MOS transistor 36 is connected to the first read line L1, and a drain of the eighth MOS transistor 36 is connected to the second read line L2); referring to FIG.
  • the seventh MOS transistor 33 is a PMOS transistor and the eighth MOS transistor 36 is an NMOS transistor. It can be understood that the seventh MOS transistor 33 is an NMOS transistor and the eighth MOS transistor 36 is a PMOS transistor. . According to this embodiment, the data of the two storage bits having the opposite states are respectively read by the pair of MOS transistors, so that the accuracy of reading the data can be improved.
  • the storage unit is connected to the control signal; when the control signal is in the first sequence, the storage unit is in the first read state, that is, L1 is a read bit line. L2 is a read word line, and the control circuit controls the peripheral circuit to pull the level of L2 to read data from L1; when the control signal is the second sequence, the memory unit is in the second The read state, that is, L1 is the read word line, and L2 is the read bit line.
  • the control circuit controls the peripheral circuit to pull up the level of L1, and the data can be read from L2. According to this embodiment, switching of the read state of the memory cell is controlled by the control signal, which is simple and fast.
  • the first sequence has a length of 1 bit; the second sequence has a length of 1 bit; the first sequence is 0 and the second sequence is 1, or the A sequence is 1 and the second sequence is 0.
  • switching of the read state of the memory cell by the 1-bit control signal is simple and fast.
  • the embodiment of the present invention further provides a static random access memory, where the static random access memory includes: a plurality of foregoing storage units (for example, the storage unit shown in FIG. 3, FIG. 4 or FIG. 5);
  • the storage unit constitutes a rectangular storage array having the same number of rows and columns; the storage units of the same row in the storage array have the same first read line; the storage units of the same column in the storage array have the same second Read the line.
  • the static random access memory includes: a plurality of foregoing storage units (for example, the storage unit shown in FIG. 3, FIG. 4 or FIG. 5);
  • the storage unit constitutes a rectangular storage array having the same number of rows and columns; the storage units of the same row in the storage array have the same first read line; the storage units of the same column in the storage array have the same second Read the line.
  • the storage unit of the static random access memory is based on the structure of the conventional memory unit, and a MOS transistor is added.
  • the newly added MOS transistor is the seventh MOS transistor, because the gate of the seventh MOS transistor Connecting a storage bit, the source and the drain of the seventh MOS transistor are respectively connected to the first read line and the second read line, and based on characteristics of the MOS tube itself, in the first read line and the second read line Either one can be used as a read bit line, and the other can be used as a read word line, thereby realizing interchangeability between the read word line and the read bit line.
  • a fast acquisition of an address can be realized.
  • Data about diagonally symmetric addresses of a matrix, rather than writing algorithms at the code level, is equivalent to a hardware accelerator, which can greatly increase the speed compared to writing algorithms in the code of a digital circuit, usually one to two beats (clock Cycles can be done, and digital circuit code implementations can take thousands of beats and dramatically reduce power consumption and workload.
  • each of the memory cells is coupled to a control signal; when the control signal is in a first sequence, the memory cell is in the first read state; and when the control signal is in a second sequence The memory unit is in the second read state. According to this embodiment, switching of the read state of the memory cells of the static random access memory by the control signal is simple and fast.
  • the first sequence has a length of 1 bit; the second sequence has a length of 1 bit; the first sequence is 0 and the second sequence is 1, or the first sequence is 1 And the second sequence is zero.
  • switching of the read state of the memory cells of the static random access memory by the 1-bit control signal is simple and fast.
  • only the control signal is 1 bit as an example for description.
  • FIG. 6 is a schematic diagram of memory cell reading during conventional reading.
  • the SRAM reading mode is conventional reading: the vertical reading bit is Line RBL_H, traversing is the read word line RWL_H.
  • the read word line RWL_H is kept at 1, if the value stored in the node Q is 0, the added MOS transistor is turned off, then the data read from the read bit line RBL_H is 0; if the value stored in the node Q is 1, the added When the MOS transistor is turned on, the data read from the read bit line RBL_H is 1.
  • FIG. 7 is a schematic diagram of memory array reading during conventional reading. Assuming that the data stored in the memory cell with the word line number 0 and the bit line number 2 is read, the data of (RBL_H2, RWL_H0), that is, the data of the rightmost memory cell of the first row is read.
  • FIG. 8 is a schematic diagram of memory cell reading during sequential read.
  • the SRAM read mode is read in sequence: the horizontal becomes read
  • the bit line RBL_V is taken up and becomes the read word line RWL_V.
  • the value of the word line and the bit line sent from the outside is not changed, but the word line bit line itself is changed, that is, the word line bit line is interchanged.
  • FIG. 9 is a schematic diagram of the storage array reading during the sequential reading. It is assumed that the data stored in the memory cell with the word line number 0 and the bit line number 2 is still to be read, but as shown in FIG.
  • the data of (RBL_V2, RWL_V0) is read, that is, the lowermost memory cell of the first column.
  • the stored data that is, the data of the storage unit of the conventionally read storage unit in Fig. 7 with respect to the diagonally symmetric position of the matrix. In this way, only one beat (ie, one clock cycle) can be used to read data of a storage address with respect to the diagonally symmetric storage address of the storage array, thereby greatly improving the speed and greatly reducing power consumption. And the workload.
  • each of the storage units is connected to a control signal; when the control signal is in a first sequence, the storage unit is in the first read state; when the control signal In the second sequence, the memory unit is in the second read state. According to this embodiment, switching of the read state of the memory cells of the static random access memory by the control signal is simple and fast.
  • the first sequence has a length of 1 bit; the second sequence has a length of 1 bit; the first sequence is 0 and the second sequence is 1, or the A sequence is 1 and the second sequence is 0.
  • switching of the read state of the memory cells of the static random access memory by the 1-bit control signal is simple and fast.
  • the switching of the static random access memory between the first read state and the second read state may be implemented by controlling a control circuit at the periphery of the storage array by a control signal.
  • FIG. 10 is a schematic diagram of a control circuit according to an embodiment of the present invention.
  • the static random access memory further includes a control circuit having the following structure in addition to the storage array: a first decoder 1001, a second decoder 1002, and a first word line driver 1003.
  • a second word line driver 1004 a first sense amplifier 1005, a second sense amplifier 1006, and an inverter 1007;
  • the control signal T_EN is coupled to the enable end (a1) of the first decoder 1001, the An enable terminal (a1) of the first word line driver 1003 and an enable terminal (a1) of the first sense amplifier 1005;
  • an input terminal (a2) of the first decoder 1001 inputs an address value, the a first output end (a3) of a decoder 1001 outputs a line number, a second output end (a4) of the first decoder 1001 outputs a column number; and a first output end (a3) of the first decoder 1001
  • Connecting the control terminal (a3) of the first sense amplifier 1005, the input terminals (a10, a11, a12) of the first sense amplifier 1005 are connected to the first read line (ie, the vertical line L10, L11, L12);
  • the second output terminal (a4) of the first decoder 1001 is connected to
  • two sets of decoders, word line drivers and sense amplifiers are provided, and the connections of the two sets of decoders, word line drivers and sense amplifiers are different, and a set of decoders and word line drivers are controlled by the control signals.
  • the sense amplifier works to achieve the interchange of the read word line and the read bit line.
  • FIG. 11 is a schematic diagram of another control circuit according to an embodiment of the present invention.
  • the static random access memory includes a control circuit including a decoder 1101, a word line driver 1102, a sense amplifier 1103, and the The number of rows of the storage array is the same number of first selectors 1104, the same number of second selectors 1105 as the number of columns of the storage array; the input end (c1) of the decoder 1101 inputs an address value, the decoder a first output end (c2) of 1101 outputs a line number, a second output end (c3) of the decoder 1101 outputs a column number; a first output end (c2) of the decoder 1101 is connected to the word line driver 1102 Control terminal (c2), the control terminal (c2) of the word line driver 1102 is configured to control at least one output terminal (c10, c11, c12) of the word line driver 1102 to output a logic 1, the decoder 1101 a second output terminal (c3) is coupled to the control
  • the static random access memory may be disposed in a chip having a specific function, or may be independent of the above chip.
  • the above chip can be a chip that requires a large amount of fast matrix calculation.
  • custom SRAM in the Convolutional Neural Network (CNN) chip can quickly decompose the convolution kernel.
  • the SRAM in the embodiment of the present invention can also be used as an SRAM of some encryption chips.
  • CNN With the intelligentization of the chip, based on the standard single instruction multiple data (SIMD), CNN can further reduce the data communication on the bus due to its special multiplexing mechanism.
  • SIMD single instruction multiple data
  • the concept of reuse is particularly important in very large neural networks.
  • the parameter size of the convolution kernel can be as large as 3 ⁇ 3 ⁇ 512, and it is a problem worthy of study to reasonably decompose these super large convolutions into effective hardware.
  • the SRAM that can be read in the embodiment of the present invention can eliminate the extra data in the convolution network, and reduce the CNN. Handling power consumption and providing ideas on the underlying hardware for large convolutional structures.
  • Convolutional networks are named for "convolution" operations.
  • the fundamental purpose of convolution is to extract features from the input image.
  • Convolution uses a small square matrix of data to learn image features that preserve the spatial relationship between pixels.
  • each picture is a matrix of pixel values.
  • the matrix on the left in Figure 12 is the image matrix, which is a special case of the grayscale image (the pixel value of the conventional grayscale image is 0-255).
  • the matrix on the right is a convolution kernel matrix, which is a 3 x 3 matrix.
  • FIG. 13 is a schematic diagram of convolution calculation between a 5 ⁇ 5 image matrix and a 3 ⁇ 3 convolution kernel matrix: each 3 ⁇ 3 submatrix in the left image matrix is multiplied by a 3 ⁇ 3 convolution kernel matrix, and then The sum obtained by summing the results of the respective positions is placed in a new matrix, that is, the matrix on the right side of Fig. 13, which is a new image matrix generated after the convolution operation of the original image matrix and the convolution kernel matrix.
  • the 3x3 matrix in Fig. 12 and Fig. 13 is also called “filter”, “convolution kernel” or “feature detector”.
  • the matrix obtained by sliding the filter and the dot multiplication matrix on the original image is called “convolution feature”, " Incentive Mapping or Feature Mapping.
  • the filter is a feature detector for the original input picture. Considering the picture as a matrix, after convolving with different convolution kernel matrices, a new picture will be obtained, and different convolution kernel matrices will have different effects.
  • Convolution kernel decomposition for example, decomposes a 2-dimensional convolution kernel with respect to diagonal symmetry into two one-dimensional convolution kernels.
  • the convolution (set to C) of the image matrix (set to A) and a two-dimensional convolution kernel matrix can be approximated by an image matrix and two one-dimensional convolution kernel matrices (set to S1, S2) for convolutional calculations. ,which is:
  • S1 and S2 Equivalent to the two-dimensional convolution kernel C as S1 and S2 is called the decomposition of the convolution kernel, and S1 and S2 are one-dimensional matrices symmetrically about the two-dimensional matrix C diagonally.

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Abstract

一种存储单元和静态随机存储器，该存储单元包括：锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线。本存储单元和静态随机存储器的存储单元能够实现读取字线和读取位线互换。

Description

一种存储单元和静态随机存储器
本申请要求于2017年09月04日提交中国专利局、申请号为201710785410.5、申请名称为“一种存储单元和静态随机存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及存储领域，尤其涉及一种存储单元和静态随机存储器(Static Random Access Memory，SRAM)。
背景技术
图1为传统的SRAM的存储单元结构示意图。该存储单元采用普通的六管单元，由6个金属-氧化物-半导体(metal oxide semiconductor，MOS)场效应晶体管构成，MOS场效应晶体管简称为MOS管。参照图1，该存储单元包括两个反相门和两个MOS管。其中，两个反相门由4个MOS管构成，图中的两个反相门构成锁存器，用于存储数据，而图中的两个MOS管用于门控访问。由两个反相门循环相连的锁存器存在两种稳定状态，0和1。其中，A和B为两个状态相反的存储位，例如，当存储位A为逻辑0时，存储位B为逻辑1；当存储位A为逻辑1时，存储位B为逻辑0。使用字线(word_line，WL)来控制存储单元的门控访问，使用位线(bit_line，BL)来进行存储单元的读写。读：拉高WL，从BL中读出位即可。写：拉高WL，拉高或者拉低BL，由于BL的驱动能力比存储单元强，会强制覆盖原来的状态。图1中，bit和nbit均代表位线，位线bit用于读取存储位A的数据，位线nbit用于读取存储位B的数据，通过两者读取的存储单元的数据相反。
图2为传统的SRAM的存储阵列示意图。该存储阵列包括3×3的图1所示的存储单元。针对传统的SRAM进行数据读取时，通常只能读取某一地址的数据，如果想要获取该地址关于矩阵对角线对称地址的数据，需要通过在SRAM外围数字电路的代码中写入算法来处理，这种方式速度慢且功耗和工作负载均较高。
发明内容
本发明实施例提供了一种存储单元和静态随机存储器，能够实现读取字线和读取位线互换，从而能够获取某一地址关于矩阵对角线对称地址的数据，这种方式速度快且功耗和工作负载均较低。
第一方面，提供了一种存储单元，所述存储单元包括锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线。
本发明实施例，以传统的能够提供存储位的锁存器的结构为基础，增加了一个MOS管，该MOS管的栅极连接存储位，该MOS管的源极和漏极分别连接第一读取线和第二读 取线，基于MOS管本身的特性，第一读取线和第二读取线中的任一个均可作为读取位线，另一个作为读取字线，从而实现读取字线和读取位线的可互换，通过改变最底层的硬件存储单元来实现快速的获取某一地址关于矩阵对角线对称地址的数据，而不是在代码层面写入算法，相当于一个硬件加速器，相比在数字电路的代码中写入算法，能极大地提升速度，并极大地降低功耗和工作负载，通常一到两拍(时钟周期)即可完成，而数字电路代码实现可能需要上千拍。
在一种可能的实施方式中，所述第一MOS管为NMOS管或PMOS管。
在一种可能的实施方式中，所述锁存器还提供第二存储位；所述存储单元还包括第二MOS管；所述第二MOS管的栅极连接所述第二存储位，所述第二MOS管的源极连接所述第一读取线，所述第二MOS管的漏极连接所述第二读取线。根据该实施方式，通过一对MOS管分别读取状态相反的两个存储位的数据，能够提高读取数据的准确性。
在一种可能的实施方式中，所述第一MOS管为NMOS管且所述第二MOS管为PMOS管；或，所述第一MOS管为PMOS管且所述第二MOS管为NMOS管。
第二方面，提供了一种静态随机存储器，所述静态随机存储器包括：多个存储单元；所述存储单元包括锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线；所述多个存储单元构成行列数相同的矩形的存储阵列；所述存储阵列中同一行的所述存储单元连接相同的所述第一读取线；所述存储阵列中同一列的所述存储单元连接相同的所述第二读取线。
本发明实施例，静态随机存储器的存储单元以传统的能够提供存储位的锁存器的结构为基础，增加了一个MOS管，该MOS管的栅极连接存储位，该MOS管的源极和漏极分别连接第一读取线和第二读取线，基于MOS管本身的特性，第一读取线和第二读取线中的任一个均可作为读取位线，另一个作为读取字线，从而实现读取字线和读取位线的可互换，通过改变最底层的硬件存储单元来实现快速的获取某一地址关于矩阵对角线对称地址的数据，而不是在代码层面写入算法，相当于一个硬件加速器，相比在数字电路的代码中写入算法，能极大地提升速度，并极大地降低功耗和工作负载，通常一到两拍(时钟周期)即可完成，而数字电路代码实现可能需要上千拍。
在一种可能的实施方式中，所述第一MOS管为NMOS管或PMOS管。
在一种可能的实施方式中，所述锁存器还提供第二存储位；所述存储单元还包括第二MOS管；所述第二MOS管的栅极连接所述第二存储位，所述第二MOS管的源极连接所述第一读取线，所述第二MOS管的漏极连接所述第二读取线。根据该实施方式，通过一对MOS管分别读取状态相反的两个存储位的数据，能够提高读取数据的准确性。
在一种可能的实施方式中，所述第一MOS管为NMOS管且所述第二MOS管为PMOS管；或，所述第一MOS管为PMOS管且所述第二MOS管为NMOS管。
在一种可能的实施方式中，每个所述存储单元与控制信号相连接；当所述控制信号为第一序列时，将所述存储单元视为所述第一状态；当所述控制信号为第二序列时，将所述存储单元视为所述第二状态。根据该实施方式，通过控制信号来控制静态随机存储器的 存储单元的读取状态的切换，简单快速。
在一种可能的实施方式中，所述第一序列的长度为1bit；所述第二序列的长度为1bit；所述第一序列为0且所述第二序列为1，或，所述第一序列为1且所述第二序列为0。根据该实施方式，通过1bit控制信号来控制静态随机存储器的存储单元的读取状态的切换，简单快速。
在一种可能的实施方式中，所述静态随机存储器还包括：第一解码器、第二解码器、第一字线驱动器、第二字线驱动器、第一读出放大器、第二读出放大器和反相器；所述控制信号连接所述第一解码器的使能端、所述第一字线驱动器的使能端和所述第一读出放大器的使能端；所述第一解码器的输入端输入地址值，所述第一解码器的第一输出端输出行号，所述第一解码器的第二输出端输出列号；所述第一解码器的第一输出端连接所述第一读出放大器的控制端，所述第一读出放大器的输入端连接所述第一读取线；所述第一解码器的第二输出端连接所述第一字线驱动器的控制端，所述第一字线驱动器的输出端连接所述第二读取线，所述第一读出放大器的控制端用于控制所述第一读出放大器对至少一个输入端的数据进行放大处理，所述第一字线驱动器的控制端用于控制所述第一字线驱动器的至少一个输出端输出第一逻辑状态；所述控制信号连接所述反相器的输入端，所述反相器的输出端连接所述第二解码器的使能端、所述第二字线驱动器的使能端和所述第二读出放大器的使能端；所述第二解码器的输入端输入地址值，所述第二解码器的第一输出端输出行号，所述第二解码器的第二输出端输出列号；所述第二解码器的第一输出端连接所述第二读出放大器的控制端，所述第二读出放大器的输入端连接所述第二读取线；所述第二解码器的第二输出端连接所述第二字线驱动器的控制端，所述第二字线驱动器的输出端连接所述第一读取线，所述第二读出放大器的控制端用于控制所述第二读出放大器对至少一个输入端的数据进行放大处理，所述第二字线驱动器的控制端用于控制所述第二字线驱动器的至少一个输出端输出所述第一逻辑状态。根据该实施方式，设置两组解码器、字线驱动器和读出放大器，两组解码器、字线驱动器和读出放大器的连线不同，通过控制信号控制其中的一组解码器、字线驱动器和读出放大器工作，从而实现读取字线和读取位线的互换。
在一种可能的实施方式中，所述静态随机存储器还包括：解码器、字线驱动器、读出放大器、与所述存储阵列的行数相同数目个第一选择器、与所述存储阵列的列数相同数目个第二选择器；所述解码器的输入端输入地址值，所述解码器的第一输出端输出行号，所述解码器的第二输出端输出列号；所述解码器的第一输出端连接所述字线驱动器的控制端，所述字线驱动器的控制端用于控制所述字线驱动器的至少一个输出端输出第一逻辑状态，所述解码器的第二输出端连接所述读出放大器的控制端，所述读出放大器的控制端用于控制所述读出放大器对至少一个输入端的数据进行放大处理；所述控制信号连接所述第一选择器和所述第二选择器的控制端；所述第一选择器的第一端口连接所述第一读取线，所述第一选择器的第二端口连接所述第二读取线，所述第一选择器的第三端口连接所述字线驱动器的输出端；其中，所述第一选择器的控制端用于控制所述第一选择器的第一端口与所述第一选择器的第三端口联通，或所述第一选择器的第二端口与所述第一选择器的第三端口联通；所述第二选择器的第一端口连接所述第二读取线，所述第二选择器的第二端口连接所述第一读取线，所述第二选择器的第三端口连接所述读出放大器的输入端；其中，所述第二选择器的控制端用于控制所述第二选择器的第一端口与所述第二选择器的第三 端口联通，或所述第二选择器的第二端口与所述第二选择器的第三端口联通。根据该实施方式，通过选择器切换电路的连接方式，从而实现读取字线和读取位线的互换。
第三方面，提供了一种芯片，该芯片包括：上述第二方面的静态随机存储器。
在一种可能的实施方式中，该芯片用于卷积神经网络中的卷积核分解。
附图说明
图1为传统的SRAM的存储单元结构示意图；
图2为传统的SRAM的存储阵列示意图；
图3为本发明实施例提供的一种SRAM的存储单元结构示意图；
图4为本发明实施例提供的另一种SRAM的存储单元结构示意图；
图5为本发明实施例提供的又一种SRAM的存储单元结构示意图；
图6为本发明实施例提供的传统读取时的存储单元读取示意图；
图7为本发明实施例提供的传统读取时的存储阵列读取示意图；
图8为本发明实施例提供的转序读取时的存储单元读取示意图；
图9为本发明实施例提供的转序读取时的存储阵列读取示意图；
图10为本发明实施例提供的一种控制电路示意图；
图11为本发明实施例提供的另一种控制电路示意图；
图12为图像矩阵和卷积核矩阵的示意图；
图13为5×5图像矩阵和3×3卷积核矩阵之间的卷积计算示意图。
具体实施方式
本发明实施例，提供了一种存储单元，所述存储单元包括锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线。
其中，所述锁存器可以但不限于为由两个反相门循环相连构成的锁存器。基于通常的存储单元中包括的锁存器，该锁存器对应的原有的位线和字线不再用于读取数据。
可以理解的是，所述第一MOS管可以为NMOS管或PMOS管。
在一个示例中，所述锁存器还提供第二存储位；所述存储单元还包括第二MOS管；所述第二MOS管的栅极连接所述第二存储位，所述第二MOS管的源极连接所述第一读取线，所述第二MOS管的漏极连接所述第二读取线。根据该实施方式，通过一对MOS管分别读取状态相反的两个存储位的数据，能够提高读取数据的准确性。
在一个示例中，所述第一MOS管为NMOS管且所述第二MOS管为PMOS管；或，所述第一MOS管为PMOS管且所述第二MOS管为NMOS管。
本发明实施例，以传统的能够提供存储位的锁存器的结构为基础，增加了一个MOS管，该MOS管的栅极连接存储位，该MOS管的源极和漏极分别连接第一读取线和第二读取线，基于MOS管本身的特性，第一读取线和第二读取线中的任一个均可作为读取位线，另一个作为读取字线，从而实现读取字线和读取位线的可互换，通过改变最底层的硬件存 储单元来实现快速的获取某一地址关于矩阵对角线对称地址的数据，而不是在代码层面写入算法，相当于一个硬件加速器，相比在数字电路的代码中写入算法，能极大地提升速度，并极大地降低功耗和工作负载，通常一到两拍(时钟周期)即可完成，而数字电路代码实现可能需要上千拍。
图3为本发明实施例提供的一种SRAM的存储单元结构示意图。如果两个反向门是按照现有技术的4个MOS管的结构设计的话，那么本发明实施例中的该存储单元可以被视为一种7管单元，在传统的6管单元上增加一个如图所示圆圈中的MOS管，使得该SRAM有传统读取和转序读取两种模式。
下面对图3所示的存储单元的结构进行具体说明，所述存储单元包括：第一MOS管、第二MOS管、第三MOS管、第四MOS管、第五MOS管31、第六MOS管32(第五MOS管、第六MOS管又称写MOS管)和第七MOS管33；
其中，第一MOS管、第二MOS管、第三MOS管、第四MOS管在图3中未示出，所述第一MOS管和所述第二MOS管组成第一反相门34，所述第三MOS管和所述第四MOS管组成第二反相门35；所述第一反相门34和所述第二反相门35首尾相连构成锁存器，所述第一反相门34的输出端为第一存储位Q，所述第二反相门35的输出端为第二存储位
Figure PCTCN2018084100-appb-000001
所述第五MOS管31的源极和漏极中的一极与所述第二存储位
Figure PCTCN2018084100-appb-000002
相连，所述第六MOS管32的源极和漏极中的一极与所述第一存储位Q相连；所述第五MOS管31的栅极和所述第六MOS管32的栅极连接写字线(write word line，WWL)，所述第五MOS管31的源极和漏极中的另一极连接第一写位线(write bit line，WBL)，所述第六MOS管32的源极和漏极中的另一极连接第二写位线(write bit line negate，WBLN)，由于第二写位线与第一写位线的逻辑状态相反，因此本发明实施例中将第一写位线记为WBL，将第二写位线记为WBLN；当将数据写入所述存储单元时，通过所述写字线使所述第五MOS管31和所述第六MOS管32导通，例如，所述写字线WWL为逻辑1，所述第一写位线WBL的逻辑状态为所述数据的逻辑状态，将所述数据写入所述第二存储位
Figure PCTCN2018084100-appb-000003
或，所述第二写位线WBLN的逻辑状态为所述数据的逻辑状态，将所述数据写入所述第一存储位Q；
可以理解的是，第一状态和第二状态仅用以区分两种不同的读取状态，本发明实施例中并不限定第一状态和第二状态。例如，在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线。还可以，在第一状态下，所述第二读取线为读取字线，所述第一读取线为读取位线；在第二状态下，所述第一读取线为读取字线，所述第二读取线为读取位线。
所述第七MOS管33的栅极连接所述第一存储位Q和所述第二存储位
Figure PCTCN2018084100-appb-000004
中的一个存储位，所述第七MOS管33的源极和漏极中的一极连接第一读取线L1，所述第七MOS管33的源极和漏极中的另一极连接第二读取线L2；当所述存储单元处于第一读取状态时，所述第一读取线L1为读取位线(RBL_H，其中，H用于标识第一读取状态，第一读取状态可简称为第一状态)，所述第二读取线L2为读取字线(RWL_H)；当所述存储单元处于第二读取状态时，所述第一读取线L1为读取字线(RWL_V，其中，V用于标识第二读取状态，第二读取状态可简称为第二状态)，所述第二读取线L2为读取位线(RBL_V)；当从所述存储单元读取数据时，将所述读取字线(RWL_H或RWL_V)设置为逻辑1，从 所述读取位线(RBL_H或RBL_V)读取所述第一存储位Q和所述第二存储位
Figure PCTCN2018084100-appb-000005
中的一个存储位存储的数据。
其中，可以将第一读取状态称为传统读取，将第二读取状态称为转序读取。WBL和WBLN为正反两路写位线，用于写入存储数据；WWL为写字线，用于写入存储数据时的门控访问；RBL_H为传统读取时的读取位线，用于读出存储数据；RWL_H为传统读取时的读取字线，用于读出存储数据时的门控访问；RWL_V为转序读取时的读取字线，用于读出存储数据时的门控访问；RBL_V为转序读取时的读取位线，用于读出存储数据；传统读取时的读取位线即是转序读取时的读取字线，传统读取时的读取字线即是转序读取时的读取位线；Q和
Figure PCTCN2018084100-appb-000006
为存储位。外围电路可以设置一个1比特(bit)的控制信号，比如T_EN，通过T_EN控制读取方式为传统读取或转序读取。
图3中，所述第七MOS管33为NMOS管。
本发明的另一个实施例中，图3中的所述第七MOS管33还可以用PMOS管来代替，如图4所示的存储单元。
本发明的又一个实施例中，可在图3或图4所示的存储单元的基础上再增加一个MOS管，如图5所示的存储单元。所述存储单元还包括第八MOS管36；所述第八MOS管36的栅极连接所述第一存储位Q和所述第二存储位
Figure PCTCN2018084100-appb-000007
中的另一个存储位(例如，当第七MOS管33连接第一存储位Q时，第八MOS管36连接第二存储位
Figure PCTCN2018084100-appb-000008
)，所述第八MOS管36的源极和漏极中的一极连接所述第一读取线L1，所述第八MOS管36的源极和漏极中的另一极连接所述第二读取线L2(例如，第八MOS管36的源极连接所述第一读取线L1，第八MOS管36的漏极连接所述第二读取线L2)；参照图5，所述第七MOS管33为PMOS管且所述第八MOS管36为NMOS管，可以理解的是，还可以所述第七MOS管33为NMOS管且所述第八MOS管36为PMOS管。根据该实施方式，通过一对MOS管分别读取状态相反的两个存储位的数据，能够提高读取数据的准确性。
在一种可能的实施方式中，所述存储单元与控制信号相连接；当所述控制信号为第一序列时，所述存储单元处于所述第一读取状态，即L1为读取位线，L2为读取字线，通过控制信号控制外围电路拉高L2的电平，从L1中读出数据即可；当所述控制信号为第二序列时，所述存储单元处于所述第二读取状态，即L1为读取字线，L2为读取位线，通过控制信号控制外围电路拉高L1的电平，从L2中读出数据即可。根据该实施方式，通过控制信号来控制存储单元的读取状态的切换，简单快速。
在一种可能的实施方式中，所述第一序列的长度为1bit；所述第二序列的长度为1bit；所述第一序列为0且所述第二序列为1，或，所述第一序列为1且所述第二序列为0。根据该实施方式，通过1bit控制信号来控制存储单元的读取状态的切换，简单快速。
本发明实施例还提供了一种静态随机存储器，所述静态随机存储器包括：多个前面所述的存储单元(例如，图3、图4或图5所示的存储单元)；所述多个存储单元构成行列数相同的矩形的存储阵列；所述存储阵列中同一行的存储单元具有相同的所述第一读取线；所述存储阵列中同一列的存储单元具有相同的所述第二读取线。下面的描述中仅以图3所示的存储单元为例进行说明，其他的存储单元构成的静态随机存储器情况类似，因此不做赘述。
本发明实施例，静态随机存储器的存储单元以传统存储单元的结构为基础，增加了 一个MOS管，这个新增的MOS管即所述第七MOS管，由于所述第七MOS管的栅极连接存储位，所述第七MOS管的源极和漏极分别连接第一读取线和第二读取线，基于MOS管本身的特性，第一读取线和第二读取线中的任一个均可作为读取位线，另一个作为读取字线，从而实现读取字线和读取位线的可互换，通过改变最底层的硬件存储单元来实现快速的获取某一地址关于矩阵对角线对称地址的数据，而不是在代码层面写入算法，相当于一个硬件加速器，相比在数字电路的代码中写入算法，能极大地提升速度，通常一到两拍(时钟周期)即可完成，而数字电路代码实现可能需要上千拍，并极大地降低功耗和工作负载。
在一个示例中，每个所述存储单元与控制信号相连接；当所述控制信号为第一序列时，所述存储单元处于所述第一读取状态；当所述控制信号为第二序列时，所述存储单元处于所述第二读取状态。根据该实施方式，通过控制信号来控制静态随机存储器的存储单元的读取状态的切换，简单快速。
在一个示例中，所述第一序列的长度为1bit；所述第二序列的长度为1bit；所述第一序列为0且所述第二序列为1，或，所述第一序列为1且所述第二序列为0。根据该实施方式，通过1bit控制信号来控制静态随机存储器的存储单元的读取状态的切换，简单快速。本发明实施例中仅以控制信号为1bit为例进行说明。
图6为传统读取时的存储单元读取示意图。当读取数据时，若控制信号T_EN＝0，该控制信号驱动控制电路拉高L2的电平并从L1读取数据，此时SRAM读取方式为传统读取：竖着的是读取位线RBL_H，横着的是读取字线RWL_H。使读取字线RWL_H保持为1，如果节点Q存储的值为0，增加的MOS管关闭，那么从读取位线RBL_H读取的数据为0；如果节点Q存储的值为1，增加的MOS管打开，那么从读取位线RBL_H读取的数据为1。图7为传统读取时的存储阵列读取示意图。假设要读取字线编号为0，位线编号为2的存储单元存储的数据，则读取了(RBL_H2,RWL_H0)的数据，即第一排最右边的存储单元的数据。
图8为转序读取时的存储单元读取示意图。当读取数据时，若控制信号T_EN＝1，该控制信号驱动控制电路拉高L1的电平并从L2读取数据，此时SRAM读取方式为转序读取：横着的变成了读取位线RBL_V，竖着变成了读取字线RWL_V。本发明实施例中，并不改变外部送过来的字线和位线的值，而是改变字线位线本身，即互换字线位线。图9为转序读取时的存储阵列读取示意图。假设仍然要读取字线编号为0，位线编号为2的存储单元存储的数据，但是如图9，这时候读取了(RBL_V2,RWL_V0)的数据，即第一列最下面的存储单元存储的数据，即图7中传统读取的存储单元关于矩阵对角线对称位置的存储单元的数据。通过这种方式只需要一拍(即一个时钟周期)就可以读取到某一存储地址关于存储阵列的对角线对称的存储地址的数据，从而能极大地提升速度，并极大地降低功耗和工作负载。
在一种可能的实施方式中，每个所述存储单元与控制信号相连接；当所述控制信号为第一序列时，所述存储单元处于所述第一读取状态；当所述控制信号为第二序列时，所述存储单元处于所述第二读取状态。根据该实施方式，通过控制信号来控制静态随机存储器的存储单元的读取状态的切换，简单快速。
在一种可能的实施方式中，所述第一序列的长度为1bit；所述第二序列的长度为1bit； 所述第一序列为0且所述第二序列为1，或，所述第一序列为1且所述第二序列为0。根据该实施方式，通过1bit控制信号来控制静态随机存储器的存储单元的读取状态的切换，简单快速。
本发明实施例中，可以通过控制信号控制存储阵列外围的控制电路来实现静态随机存储器在第一读取状态和第二读取状态之间的切换。
图10为本发明实施例提供的一种控制电路示意图，所述静态随机存储器除了包括存储阵列还包括如下结构的控制电路：第一解码器1001、第二解码器1002、第一字线驱动器1003、第二字线驱动器1004、第一读出放大器1005、第二读出放大器1006和反相器1007；所述控制信号T_EN连接所述第一解码器1001的使能端(a1)、所述第一字线驱动器1003的使能端(a1)和所述第一读出放大器1005的使能端(a1)；所述第一解码器1001的输入端(a2)输入地址值，所述第一解码器1001的第一输出端(a3)输出行号，所述第一解码器1001的第二输出端(a4)输出列号；所述第一解码器1001的第一输出端(a3)连接所述第一读出放大器1005的控制端(a3)，所述第一读出放大器1005的输入端(a10、a11、a12)连接所述第一读取线(即竖着的线L10、L11、L12)；所述第一解码器1001的第二输出端(a4)连接所述第一字线驱动器1003的控制端(a4)，所述第一字线驱动器1003的输出端(a20、a21、a22)连接所述第二读取线(即横着的线L20、L21、L22)，所述第一读出放大器1005的控制端(a3)用于控制所述第一读出放大器1005对至少一个输入端(a10、a11、a12)的数据进行放大处理，所述第一字线驱动器1003的控制端(a4)用于控制所述第一字线驱动器1003的至少一个输出端(a20、a21、a22)输出逻辑1；所述控制信号连接所述反相器1007的输入端，所述反相器1007的输出端连接所述第二解码器1002的使能端(b1)、所述第二字线驱动器1004的使能端(b1)和所述第二读出放大器1006的使能端(b1)；所述第二解码器1002的输入端(b2)输入地址值，所述第二解码器1002的第一输出端(b3)输出行号，所述第二解码器1002的第二输出端(b4)输出列号；所述第二解码器1002的第一输出端(b3)连接所述第二读出放大器1006的控制端(b3)，所述第二读出放大器1006的输入端(b20、b21、b22)连接所述第二读取线(即横着的线L20、L21、L22)；所述第二解码器1002的第二输出端(b4)连接所述第二字线驱动器1004的控制端(b4)，所述第二字线驱动器1004的输出端(b10、b11、b12)连接所述第一读取线(即竖着的线L10、L11、L12)，所述第二读出放大器1006的控制端(b3)用于控制所述第二读出放大器1006对至少一个输入端(b20、b21、b22)的数据进行放大处理，所述第二字线驱动器1004的控制端(b4)用于控制所述第二字线驱动器1004的至少一个输出端(b10、b11、b12)输出逻辑1。根据该实施方式，设置两组解码器、字线驱动器和读出放大器，两组解码器、字线驱动器和读出放大器的连线不同，通过控制信号控制其中的一组解码器、字线驱动器和读出放大器工作，从而实现读取字线和读取位线的互换。
图11为本发明实施例提供的另一种控制电路示意图，所述静态随机存储器除了包括存储阵列还包括如下结构的控制电路：解码器1101、字线驱动器1102、读出放大器1103、与所述存储阵列的行数相同数目个第一选择器1104、与所述存储阵列的列数相同数目个第二选择器1105；所述解码器1101的输入端(c1)输入地址值，所述解码器1101的第一输出端(c2)输出行号，所述解码器1101的第二输出端(c3)输出列号；所述解码器1101 的第一输出端(c2)连接所述字线驱动器1102的控制端(c2)，所述字线驱动器1102的控制端(c2)用于控制所述字线驱动器1102的至少一个输出端(c10、c11、c12)输出逻辑1，所述解码器1101的第二输出端(c3)连接所述读出放大器1103的控制端(c3)，所述读出放大器1103的控制端(c3)用于控制所述读出放大器1103对至少一个输入端(c20、c21、c22)的数据进行放大处理；所述控制信号T_EN连接所述第一选择器1104和所述第二选择器1105的控制端(k0)；所述第一选择器1104的第一端口(k1)连接所述第一读取线(即竖着的线L10、L11、L12，例如，由上至下三个第一选择器1104的第一端口(k1)分别连接L10、L11、L12)，所述第一选择器1104的第二端口(k2)连接所述第二读取线(即横着的线L20、L21、L22，例如，由上至下三个第一选择器1104的第二端口(k2)分别连接L20、L21、L22)，所述第一选择器1104的第三端口(k3)连接所述字线驱动器1102的输出端(c10、c11、c12，例如，由上之下三个第一选择器1104的第三端口(k3)分别连接c10、c11、c12)；其中，所述第一选择器1104的控制端(k0)用于控制所述第一选择器1104的第一端口(k1)与所述第一选择器1104的第三端口(k3)联通，或所述第一选择器1104的第二端口(k2)与所述第一选择器1104的第三端口(k3)联通；所述第二选择器1105的第一端口(k1)连接所述第二读取线(即横着的线L20、L21、L22)，所述第二选择器1105的第二端口(k2)连接所述第一读取线(即竖着的线L10、L11、L12)，所述第二选择器1105的第三端口(k3)连接所述读出放大器1103的输入端(c20、c21、c22，例如，由左至右三个第二选择器1105的第三端口(k3)分别连接c20、c21、c22)；其中，所述第二选择器1105的控制端(k0)用于控制所述第二选择器1105的第一端口(k1)与所述第二选择器1105的第三端口(k3)联通，或所述第二选择器1105的第二端口(k2)与所述第二选择器1105的第三端口(k3)联通。根据该实施方式，通过控制信号T_EN控制选择器切换电路的连接方式，从而实现读取字线和读取位线的互换。
本发明实施例中，静态随机存储器可以设置于具有特定功能的芯片中，也可以与上述芯片相独立。上述芯片可以为需要大量快速矩阵计算的芯片。例如，在人工智能领域，卷积神经网络(Convolutional Neural Network，CNN)芯片中定制的SRAM，可以快速实现卷积核的分解。本发明实施例中的SRAM也可以作为一些加密芯片的SRAM。
下面针对CNN芯片中定制的SRAM，进行一些效果说明。
随着芯片的智能化，在标准单指令多数据流(Single Instruction Multiple Data，SIMD)的基础上，CNN由于其特殊的复用机制，可以进一步减少总线上的数据通信。而复用的这一概念，在超大型神经网络中的显得格外重要。对于这些模型中的中后级卷积核，卷积核的参数量可以达3×3×512之巨大，合理地分解这些超大卷积到有效的硬件上成为了一个值得研究的问题。
本发明实施例中提到的这种可转序读取的SRAM，即数据的读取可以是位线和字线互换的，能省去卷积网络中额外的数据整理，减少了CNN的处理功耗，并且就大卷积的结构提供了底层硬件上的思路。
卷积网络是因为“卷积”操作而得名的。卷积的根本目的是从输入图片中提取特征。卷积用一个小方阵的数据学习图像特征，可以保留像素之间的空间关系。如上所述，每个图片都是像素值矩阵。考虑一个5×5的图像，其像素值为0和1，图12中左边的矩阵是图像矩阵，该图像矩阵为灰度图的特例(常规灰度图的像素值取值0-255)，右边的矩阵 是卷积核矩阵，该卷积核矩阵为3×3矩阵。图13为5×5图像矩阵和3×3卷积核矩阵之间的卷积计算示意图:左边图像矩阵中每一个3×3的子矩阵与3×3的卷积核矩阵相乘，然后将各个位置相乘的结果相加之和得到的值放到新的矩阵当中，即图13右边的矩阵，这个矩阵便是原始图像矩阵与卷积核矩阵进行卷积操作之后产生的新图像矩阵。
图12和图13中的3x3矩阵也叫“滤波器”、“卷积核”或“特征探测器”，在原图上滑动滤波器、点乘矩阵所得的矩阵称为“卷积特征”、“激励映射”或“特征映射”。滤波器对于原输入图片来说，是个特征探测器。将图片看作一个矩阵，与不同的卷积核矩阵进行卷积操作之后，会得到新的图片，不同的卷积核矩阵将会产生不同的效果。卷积核分解，例如将一个2维的关于对角线对称的卷积核分解成两个一维的卷积核。图像矩阵(设为A)与一个二维卷积核矩阵的卷积(设为C)计算，可以近似成图像矩阵与两个一维卷积核矩阵(设为S1，S2)进行卷积计算，即：
Figure PCTCN2018084100-appb-000009
将二维卷积核C等效为S1与S2便称为卷积核的分解，S1与S2是关于二维矩阵C对角线对称的一维矩阵。
如果使用传统的SRAM，若要对对卷积核进行分解，即要获取到某一地址关于矩阵对角线对称地址的数据，是没有办法直接获取的，是要通过在SRAM外围数字电路的代码中写入算法来处理的。将本发明实施例的SRAM应用在卷积神经网络芯片中，可以实现快速的卷积核分解，极大的降低卷积核分解这一频繁操作的功耗，同时极大地提升这一操作的速度。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。

Claims (13)

  1. 一种存储单元，其特征在于，所述存储单元包括锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；
    所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线。
  2. 如权利要求1所述的存储单元，其特征在于，所述第一MOS管为NMOS管或PMOS管。
  3. 如权利要求2所述的存储单元，其特征在于，所述锁存器还提供第二存储位；所述存储单元还包括第二MOS管；所述第二MOS管的栅极连接所述第二存储位，所述第二MOS管的源极连接所述第一读取线，所述第二MOS管的漏极连接所述第二读取线。
  4. 如权利要求3所述的存储单元，其特征在于，所述第一MOS管为NMOS管且所述第二MOS管为PMOS管；或，所述第一MOS管为PMOS管且所述第二MOS管为NMOS管。
  5. 一种静态随机存储器，其特征在于，所述静态随机存储器包括：多个存储单元；
    所述存储单元包括锁存器，所述锁存器提供第一存储位；所述存储单元还包括第一MOS管；
    所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接第一读取线，所述第一MOS管的漏极连接第二读取线；在第一状态下，所述第一读取线为读取字线，所述第二读取线为读取位线；在第二状态下，所述第二读取线为读取字线，所述第一读取线为读取位线；
    所述多个存储单元构成行列数相同的矩形的存储阵列；
    所述存储阵列中同一行的所述存储单元连接相同的所述第一读取线；
    所述存储阵列中同一列的所述存储单元连接相同的所述第二读取线。
  6. 如权利要求5所述的静态随机存储器，其特征在于，所述第一MOS管为NMOS管或PMOS管。
  7. 如权利要求6所述的静态随机存储器，其特征在于，所述锁存器还提供第二存储位；所述存储单元还包括第二MOS管；所述第二MOS管的栅极连接所述第二存储位，所述第二MOS管的源极连接所述第一读取线，所述第二MOS管的漏极连接所述第二读取线。
  8. 如权利要求7所述的静态随机存储器，其特征在于，所述第一MOS管为NMOS管且所述第二MOS管为PMOS管；或，所述第一MOS管为PMOS管且所述第二MOS管为NMOS管。
  9. 如权利要求5至8中任一项所述的静态随机存储器，其特征在于，每个所述存储单元与控制信号相连接；
    当所述控制信号为第一序列时，将所述存储单元视为所述第一状态；
    当所述控制信号为第二序列时，将所述存储单元视为所述第二状态。
  10. 如权利要求9所述的静态随机存储器，其特征在于，所述第一序列的长度为1bit； 所述第二序列的长度为1bit；所述第一序列为0且所述第二序列为1，或，所述第一序列为1且所述第二序列为0。
  11. 如权利要求9或10所述的静态随机存储器，其特征在于，所述静态随机存储器还包括：
    第一解码器、第二解码器、第一字线驱动器、第二字线驱动器、第一读出放大器、第二读出放大器和反相器；
    所述控制信号连接所述第一解码器的使能端、所述第一字线驱动器的使能端和所述第一读出放大器的使能端；
    所述第一解码器的输入端输入地址值，所述第一解码器的第一输出端输出行号，所述第一解码器的第二输出端输出列号；所述第一解码器的第一输出端连接所述第一读出放大器的控制端，所述第一读出放大器的输入端连接所述第一读取线；所述第一解码器的第二输出端连接所述第一字线驱动器的控制端，所述第一字线驱动器的输出端连接所述第二读取线，所述第一读出放大器的控制端用于控制所述第一读出放大器对至少一个输入端的数据进行放大处理，所述第一字线驱动器的控制端用于控制所述第一字线驱动器的至少一个输出端输出第一逻辑状态；
    所述控制信号连接所述反相器的输入端，所述反相器的输出端连接所述第二解码器的使能端、所述第二字线驱动器的使能端和所述第二读出放大器的使能端；
    所述第二解码器的输入端输入地址值，所述第二解码器的第一输出端输出行号，所述第二解码器的第二输出端输出列号；所述第二解码器的第一输出端连接所述第二读出放大器的控制端，所述第二读出放大器的输入端连接所述第二读取线；所述第二解码器的第二输出端连接所述第二字线驱动器的控制端，所述第二字线驱动器的输出端连接所述第一读取线，所述第二读出放大器的控制端用于控制所述第二读出放大器对至少一个输入端的数据进行放大处理，所述第二字线驱动器的控制端用于控制所述第二字线驱动器的至少一个输出端输出所述第一逻辑状态。
  12. 如权利要求9或10所述的静态随机存储器，其特征在于，所述静态随机存储器还包括：
    解码器、字线驱动器、读出放大器、与所述存储阵列的行数相同数目个第一选择器、与所述存储阵列的列数相同数目个第二选择器；
    所述解码器的输入端输入地址值，所述解码器的第一输出端输出行号，所述解码器的第二输出端输出列号；所述解码器的第一输出端连接所述字线驱动器的控制端，所述字线驱动器的控制端用于控制所述字线驱动器的至少一个输出端输出第一逻辑状态，所述解码器的第二输出端连接所述读出放大器的控制端，所述读出放大器的控制端用于控制所述读出放大器对至少一个输入端的数据进行放大处理；
    所述控制信号连接所述第一选择器和所述第二选择器的控制端；
    所述第一选择器的第一端口连接所述第一读取线，所述第一选择器的第二端口连接所述第二读取线，所述第一选择器的第三端口连接所述字线驱动器的输出端；其中，所述第一选择器的控制端用于控制所述第一选择器的第一端口与所述第一选择器的第三端口联通，或所述第一选择器的第二端口与所述第一选择器的第三端口联通；
    所述第二选择器的第一端口连接所述第二读取线，所述第二选择器的第二端口连接所 述第一读取线，所述第二选择器的第三端口连接所述读出放大器的输入端；其中，所述第二选择器的控制端用于控制所述第二选择器的第一端口与所述第二选择器的第三端口联通，或所述第二选择器的第二端口与所述第二选择器的第三端口联通。
  13. 一种存储单元，其特征在于，包括锁存器、写MOS管、写字线、写位线、第一读取线和第二读取线，所述锁存器提供第一存储位和第二存储位，所述写位线通过所述写MOS管与所述第一存储位和所述第二存储位相接，所述写字线与所述写MOS管的栅极相连以控制所述写MOS管的导通和关断，所述存储单元还包括第一MOS管，所述第一MOS管的栅极连接所述第一存储位，所述第一MOS管的源极连接所述第一读取线，所述第一MOS管的漏极连接所述第二读取线。
PCT/CN2018/084100 2017-09-04 2018-04-23 一种存储单元和静态随机存储器 Ceased WO2019041840A1 (zh)

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