WO2019043003A1 - Procédé servant à fabriquer une pluralité de puces semi-conductrices à émission de rayonnement, puce semi-conductrice à émission de rayonnement et réseau de puces semi-conductrices à émission de rayonnement - Google Patents

Procédé servant à fabriquer une pluralité de puces semi-conductrices à émission de rayonnement, puce semi-conductrice à émission de rayonnement et réseau de puces semi-conductrices à émission de rayonnement Download PDF

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Publication number
WO2019043003A1
WO2019043003A1 PCT/EP2018/073132 EP2018073132W WO2019043003A1 WO 2019043003 A1 WO2019043003 A1 WO 2019043003A1 EP 2018073132 W EP2018073132 W EP 2018073132W WO 2019043003 A1 WO2019043003 A1 WO 2019043003A1
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WIPO (PCT)
Prior art keywords
semiconductor layer
layer stack
radiation
semiconductor
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2018/073132
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German (de)
English (en)
Inventor
Martin Rudolf Behringer
Christian Müller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
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Filing date
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Publication of WO2019043003A1 publication Critical patent/WO2019043003A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/817—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
    • H10H20/818—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous within the light-emitting regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/833—Transparent materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/835—Reflective materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • One object in the present case is to specify a method for producing an improved radiation-emitting semiconductor chip, an improved semiconductor chip and an improved radiation-emitting semiconductor chip array.
  • a semiconductor chip is to be specified which has a comparatively small radiation exit area with increased efficiency. Furthermore, a should
  • radiation-emitting semiconductor chip array can be given with increased efficiency.
  • a growth substrate is first provided.
  • Growth substrate may include, for example, sapphire, gallium nitride, silicon carbide or silicon or consist of one of these materials.
  • an epitaxial semiconductor layer sequence with an active zone, which is suitable for generating electromagnetic radiation is epitaxially grown on the growth substrate.
  • the epitaxial semiconductor layer sequence is here
  • Nitride compound semiconductor material formed or comprises a nitride compound semiconductor material.
  • Compound semiconductor materials containing nitrogen such as the materials of the system In x Al y Gai x - y N with 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and x + y ⁇ 1.
  • the nitride compound semiconductor material is GaN or AlInGaN.
  • Nitride compound semiconductor material it is particularly preferred short-wave visible radiation, for example from the ultraviolet, blue or green spectral range generated in the active zone.
  • Semiconductor layer sequence applied are areas the semiconductor layer sequence between the structural elements particularly preferably freely accessible.
  • the semiconductor layer sequence is etched in the freely accessible regions, so that hexagonal or triangular
  • Semiconductor layer stack arise with side surfaces, of which at least one side surfaces parallel to an m-surface or parallel to an a-surface of the
  • Nitride compound semiconductor material runs. The
  • Side surface may also be formed by the m-surface or by the a-surface of the nitride compound semiconductor material.
  • parallel is meant here that the
  • Semiconductor layer stack preferably parallel to the a-surface.
  • the nitride compound semiconductor material such as GaN or AlInGaN, is usually hexagonal Crystal structure, in particular a
  • Nitride compound semiconductor material is in the
  • Crystal structure usually a c-surface, which is usually in the polar (OOOl) surface. On the c surface is a c-axis of the crystal structure
  • the side surfaces of the semiconductor layer stacks are the side surfaces of the semiconductor layer stacks.
  • Semiconductor layer stacks are preferably parallel to the c-face of the nitride compound semiconductor material and in the
  • Nitride compound semiconductor material formed.
  • the patterned photoresist layer with the below
  • a photoresist layer is applied over the entire surface of the semiconductor layer sequence, for example by means of spinning. Then the photoresist layer is exposed with a mask, wherein the mask has hexagonal or triangular structural elements.
  • the mask is particularly preferably adjusted such that at least one side surface of each structure element of the mask runs parallel to the m surface or parallel to the a surface of the nitride compound semiconductor material.
  • the active zone of the semiconductor layer sequence is completely severed.
  • Etched or etched using a wet-chemical etching process Particularly preferably arise in the dry ⁇ chemical etching or in the wet-chemical
  • the active zone is perpendicular to the
  • the side surfaces cover the active zone. Furthermore, it is also possible that the
  • Semiconductor layer sequence is first cut with the dry-chemical etching process and then the resulting
  • Side surfaces of the semiconductor layer stacks which are as free as possible of defects, such as steps and edges.
  • the side surfaces of the Semiconductor layer stacks do not have steps parallel to the c-axis of the nitride compound semiconductor material.
  • a mirror layer is applied to a first main surface of the semiconductor layer sequence facing away from the growth substrate.
  • the mirror layer is suitable for particularly well reflecting electromagnetic radiation that is generated in the active zone.
  • the mirror layer may, for example, have a metallic layer or consist of a metallic layer.
  • the mirror layer as a Bragg reflector
  • the mirror layer can serve as an electrical contact for the semiconductor layer sequence.
  • the mirror layer must be electrically conductive.
  • a carrier is applied to the mirror layer and the
  • the growth substrate can be removed by means of a laser lift-off method, by means of an etching process, by polishing or grinding. Alternatively, it is also possible for the growth substrate to remain in the semiconductor chips.
  • Semiconductor chip comprises, so the second main surface of the semiconductor layer stack preferably to a
  • the first main surface of the semiconductor layer stack preferably has one
  • the carrier may be, for example, a
  • Silicon carrier or a wafer with an integrated circuit act.
  • the carrier serves to mechanically stabilize the semiconductor layer sequence.
  • the semiconductor chip it is possible for the semiconductor chip to be supplied with current via the carrier.
  • an electrical contact is applied to one of the main surfaces of the semiconductor layer sequence, which faces away from the mounting surface of the semiconductor chip.
  • Contact may be, for example, a transparent contact layer, the entire surface on the second
  • Main surface of the semiconductor layer sequence is applied.
  • the electrically transparent contact layer can be any electrically transparent contact layer.
  • TCO transparent conductive oxide
  • Transparent conductive oxides are generally metal oxides, such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide or indium tin oxide (ITO), in addition to binary metal oxygen compounds, such as
  • ZnO, SnO 2 or ⁇ 2 ⁇ 3 also include ternary
  • TCOs Metal oxygen compounds such as Zn 2 SnO 4 , ZnSnO 3, Mgln 2 O 4 , GalnO 3, Zn 2 In 2 O or In 4 Sn 2 O 2 or mixtures different transparent conductive oxides to the group of TCOs.
  • the TCOs do not necessarily correspond to a stoichiometric composition and may furthermore also be p- and n-doped.
  • the transparent contact layer may also comprise graphene or consist of graphene.
  • the electrical contact is a metallic frame or comprises a metallic frame.
  • the metallic frame completely surrounds a radiation exit surface of each semiconductor chip.
  • the transparent contact layer is applied over the entire surface of the first main area or the second main area of the semiconductor layer sequence, and the metallic one
  • the semiconductor chips are singulated so that each semiconductor chip comprises a single semiconductor layer stack.
  • epitaxial semiconductor layer sequence comprises, so isolated, that several semiconductor layer stacks remain in a composite.
  • Semiconductor chip array can be realized and vice versa.
  • a radiation-emitting semiconductor chip comprises a semiconductor layer stack with an active zone.
  • the active zone is suitable for generating electromagnetic radiation.
  • the semiconductor layer stack comprises a
  • Nitride compound semiconductor material or is made of a
  • Nitride compound semiconductor material formed is particularly preferred by a
  • Nitride compound semiconductor material formed or comprises a nitride compound semiconductor material.
  • the semiconductor layer stack has a hexagonal or triangular base.
  • a base area of the semiconductor chip is defined by the base area of the semiconductor layer stack.
  • the base area of the semiconductor chip is likewise preferably hexagonal or triangular.
  • the semiconductor chip and / or the semiconductor layer stack are formed as a six-sided or three-sided prism.
  • the base area and a top surface of the six-sided prism are preferred as Hexagon trained.
  • the base surface and a top surface of the three-sided prism are preferably formed as a triangle.
  • the top surface of the prism is hereby preferably the
  • the prism is straight.
  • At least one side face of the semiconductor layer stack is formed by the m face or the a face of the nitride compound semiconductor material.
  • a side surface is preferably parallel to the a surface.
  • a side edge of the base area of the semiconductor layer stack and / or of the semiconductor chip is not larger than 30 micrometers. Particularly preferred is a
  • Semiconductor chip has this a carrier on which the semiconductor layer stack is arranged.
  • the carrier is particularly preferably different from the growth substrate.
  • a mirror layer is preferably arranged between the carrier and the semiconductor layer stack. The mirror layer is intended to electromagnetic radiation generated in the active region of the semiconductor chip to a
  • the mirror layer is designed to be electrically conductive, so that the semiconductor chip has its own Mounting surface, which is opposite to a radiation exit surface, can be electrically contacted.
  • the semiconductor chip is free of a carrier and a growth substrate.
  • the semiconductor layer stack is preferably arranged on a metallic carrier layer, for example in direct contact.
  • Carrier layer is, for example, electrodeposited.
  • the metallic carrier layer stabilizes the
  • the metallic support layer has a thickness between 2 microns inclusive and 10 microns inclusive.
  • the metallic carrier layer acts as a mirror, the electromagnetic radiation generated in the active zone of the semiconductor chip to the
  • Radiation exit surface of the semiconductor chip directs.
  • an electrical contact is disposed on one of the two main surfaces of the semiconductor layer stack, which is a transparent
  • Contact layer and / or a metallic frame comprises.
  • Semiconductor layer stacks are particularly preferably part of a semiconductor chip array.
  • a radiation-emitting semiconductor chip array preferably comprises a multiplicity of semiconductor layer stacks.
  • each semiconductor layer stack has an active zone suitable for electromagnetic radiation to create.
  • the semiconductor layer stacks preferably comprise a nitride compound semiconductor material or are formed of a nitride compound semiconductor material.
  • each semiconductor layer stack has a
  • the semiconductor layer stacks are one
  • the carrier particularly preferably has an integrated circuit for controlling the semiconductor layer stacks.
  • the carrier particularly preferably has an integrated circuit for controlling the semiconductor layer stacks.
  • Semiconductor layer stack particularly preferably electrically connected via the main surface facing the mounting surface electrically connected to the integrated circuit.
  • the semiconductor layer stacks are particularly preferably over their main sides facing the radiation exit area
  • Semiconductor layer stack a hexagonal or a
  • Semiconductor layer stack further layers applied, of which the outermost layer at least partially the radiation exit surface of the semiconductor chip array
  • the metallic frame alone or together with the transparent contact layer serves as an electrical contact for the semiconductor layer stack. Particularly preferred are the
  • the metallic frame adjacent semiconductor layer stack electrically conductively interconnect is preferably formed metallic.
  • the semiconductor chip array can, for example, in one
  • individual semiconductor layer stacks are particularly preferably switched on and off, for example using a carrier with an integrated circuit.
  • the emission characteristics of the headlamp can be adjusted as desired, such as dipped beam,
  • the semiconductor chip array is used as a structured light source in a display or in a spotlight for a stage lighting. Again, it may be useful and desirable to have parts of
  • Switch semiconductor chip arrays arbitrarily on or off to change the radiation characteristic desired.
  • Semiconductor chips such as with edge lengths less than or equal to 30 microns or even less than or equal to 1 microns, form hexagonal or triangular and the side surfaces of the semiconductor chip on the crystal surfaces of
  • Radiation-emitting semiconductor chips are produced which have few or no defects on their side surfaces
  • Edge regions therefore comprise a comparatively large proportion of the surface of the semiconductor chip.
  • Figure 14 shows a schematic plan view of a
  • a radiation-emitting semiconductor chip according to a
  • Figure 15 shows a schematic plan view of a
  • FIG. 16 shows a schematic sectional representation of a radiation-emitting semiconductor chip array according to one exemplary embodiment.
  • Figure 17 shows a schematic plan view of the
  • FIG. 18 shows a schematic plan view of one
  • a growth substrate 1 is provided, to which an epitaxial growth element 1 is provided
  • FIG. 1 shows a sectional view through the
  • the epitaxial semiconductor layer sequence 2 represents.
  • the epitaxial semiconductor layer sequence 2 is in the present case formed from a nitride compound semiconductor material and has an active zone 3 which is suitable for
  • the active zone 3 is suitable for blue light
  • the growth substrate 1 is
  • a sapphire wafer for example, a sapphire wafer.
  • a mask is preferably used which has hexagonal structural elements (not
  • the photoresist layer 4 is patterned into hexagonal structural elements 5, which leaves areas of the epitaxial semiconductor layer sequence 2 free.
  • the nitride compound semiconductor material of the epitaxial semiconductor layer sequence 2 in this case has a hexagonal crystal structure with an a-surface 6, an m-surface 7 and a c-surface 8.
  • Crystal structure is to explain the a-surface 6, the m- Surface 7 and the c-surface 8 shown schematically in Figures 7 to 9.
  • the unit cell of the hexagonal crystal structure is formed as a prism having a hexagonal base whose corners are each formed by a gallium atom 9.
  • the c-area 8 of the unit cell with the Miller indices (0001) is shown hatched in FIG.
  • the c-surface 8 forms a top surface of the prism.
  • the m-area 7 of the unit cell with the Miller indices (1100) is shown hatched in FIG.
  • the m-surface 7 forms a side surface of the prism.
  • a unit cell with the Miller indices (1120) is shown hatched in FIG.
  • the a-surface 6 is an area that runs inside the unit cell.
  • the a-surface 6 is perpendicular to the c-surface 8 and connects two corner points of the unit cell, between which a single further corner is arranged.
  • the epitaxial semiconductor layer sequence 2 has grown epitaxially in such a way that its main surfaces are arranged parallel to the c-surface 8 of the unit cell.
  • the structural elements of the mask are preferably adjusted such that at least one of their edges runs parallel to the m-surface 7 or parallel to the a-surface 6. In this way, structural elements 5 in the
  • Photoresist layer 4 generated, which also extend parallel to the m-surface 7 or parallel to the a-surface 6.
  • Semiconductor layer sequence 2 through the freely accessible Etched areas in the photoresist layer 4, for example by dry etching and / or wet chemical etching, so that semiconductor layer stack 10 arise on the growth substrate 1, which are completely separated from each other.
  • the semiconductor layer stacks 10 have a hexagonal
  • Base area up. Furthermore, at least one runs
  • Mirror layer 12 can be applied, which is adapted to radiation generated in the active zone 3 to
  • FIGS. 12 and 13 wherein FIG. 12 is a schematic sectional view and FIG. 13 is a schematic sectional view
  • the composite can be singulated so that individual
  • Radiation-emitting semiconductor chips are formed, each of which comprises a single semiconductor layer stack 10.
  • semiconductor chip comprising a single semiconductor layer stack 10 is schematically shown in FIG. 14, for example shown.
  • the semiconductor chip has like the
  • Semiconductor layer stack 10 has a hexagonal base. At least one side surface 11 of the
  • Semiconductor layer stack 10 is parallel to the a-surface 6 or parallel to the m-surface 7 of the
  • Semiconductor layer stack 10 is arranged.
  • semiconductor layer stacks 10 is singled so that a radiation-emitting semiconductor chip array is formed comprising a plurality of semiconductor layer stacks 10.
  • a radiation-emitting semiconductor chip array is shown schematically, for example, in FIG.
  • the semiconductor layer stacks 10 of the semiconductor chip array according to the exemplary embodiment of FIG. 15 each have a hexagonal base surface, wherein a side surface 11 of each semiconductor layer stack 10 is parallel to the a surface 6 or parallel to the m surface 7 of FIG. 15
  • Nitride compound semiconductor material is arranged.
  • the radiation-emitting semiconductor chip array according to the exemplary embodiment of FIGS. 16 and 17 has a
  • common carrier 13 which comprises an integrated circuit.
  • An electrical control element 15 of the integrated circuit is, for example, below the
  • a mirror layer 12 is arranged on the first main surface of the semiconductor layer stack 10 .
  • Semiconductor layer stack 10 completely rotates.
  • adjacent semiconductor layer stacks 10 are electrically conductively connected via the metal frames 16 by way of webs 17.
  • the electrical controls 15 of the integrated circuit of the carrier 13 the
  • Embodiment of Figure 20 semiconductor layer stack 10 with a triangular base.
  • Semiconductor layer stacks 10 are straight as triangular
  • Semiconductor layer stack 10 is preferably arranged with respect to a hexagonal semiconductor layer stack 10, each based on a nitride compound semiconductor material.
  • Semiconductor layer stack 10 in this case connects two corners of the hexagonal semiconductor layer stack 10, between which another corner of the hexagonal
  • Semiconductor layer stack 10 is arranged.

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Abstract

L'invention concerne un procédé servant à fabriquer une pluralité de puces semi-conductrices à émission de rayonnement, comprenant les étapes consistant à : fournir un substrat de croissance (1) ; faire croître par épitaxie une succession de couches semi-conductrices (2) épitaxiales comprenant une zone active (3) qui est adaptée pour générer un rayonnement électromagnétique, sur le substrat de croissance (1), la succession de couches semi-conductrices (2) comprenant un matériau semi-conducteur à base d'un composé nitrure ; appliquer une couche de laque photosensible (4) structurée comprenant des éléments structurels (5) hexagonaux ou triangulaires sur la succession de couches semi-conductrices (2), des zones de la succession de couches semi-conductrices (2) étant librement accessibles entre les éléments structurels (5), et ; graver la succession de couches semi-conductrices (2) dans les zones librement accessibles de manière à faire apparaître des empilements de couches semi-conductrices (2) hexagonaux ou triangulaires comprenant des faces latérales (11), parmi lesquelles au moins une face latérale (11) s'étend de manière parallèle par rapport à une face m (7) ou de manière parallèle par rapport à une face a (6) du matériau semi-conducteur à base de composé nitrure. Les empilements de couches semi-conductrices sont réalisés sous la forme de prismes hexagonaux ou triangulaires, et la zone active est à la verticale sur les faces latérales de l'empilement de couches semi-conductrices.
PCT/EP2018/073132 2017-08-31 2018-08-28 Procédé servant à fabriquer une pluralité de puces semi-conductrices à émission de rayonnement, puce semi-conductrice à émission de rayonnement et réseau de puces semi-conductrices à émission de rayonnement Ceased WO2019043003A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102017120037.1A DE102017120037A1 (de) 2017-08-31 2017-08-31 Verfahren zur Herstellung einer Vielzahl strahlungsemittierender Halbleiterchips, strahlungsemittierender Halbleiterchip und strahlungsemittierender Halbleiterchip-Array
DE102017120037.1 2017-08-31

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WO2019043003A1 true WO2019043003A1 (fr) 2019-03-07

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EP1553640A1 (fr) * 2002-08-01 2005-07-13 Nichia Corporation Dispositif semi-conducteur a luminescence, procede de fabrication de ce dernier et appareil a luminescence comprenant ce dispositif
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US20100120237A1 (en) * 2008-11-10 2010-05-13 Stanley Electric Co., Ltd. Method of manufacturing semiconductor devices
DE112011102068T5 (de) * 2010-06-18 2013-03-28 Soraa, Inc. Dreieckförmig oder rautenförmig geformte gallium- und stickstoffhaltige anordnung für optische bauelemente

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US7952109B2 (en) * 2006-07-10 2011-05-31 Alcatel-Lucent Usa Inc. Light-emitting crystal structures
US7973321B2 (en) * 2007-11-05 2011-07-05 Rohm Co., Ltd. Nitride semiconductor light emitting device having ridge parts
DE102013104273A1 (de) * 2013-04-26 2014-10-30 Osram Opto Semiconductors Gmbh Anordnung mit säulenartiger Struktur und einer aktiven Zone

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340507A (ja) * 1998-05-26 1999-12-10 Matsushita Electron Corp 半導体発光素子およびその製造方法
EP1553640A1 (fr) * 2002-08-01 2005-07-13 Nichia Corporation Dispositif semi-conducteur a luminescence, procede de fabrication de ce dernier et appareil a luminescence comprenant ce dispositif
DE10245628A1 (de) * 2002-09-30 2004-04-15 Osram Opto Semiconductors Gmbh Elektromagnetische Strahlung emittierender Halbleiterchip und Verfahren zu dessen Herstellung
WO2006068297A1 (fr) * 2004-12-22 2006-06-29 Matsushita Electric Industrial Co., Ltd. Dispositif electroluminescent a semiconducteur, module d'eclairage, appareil d'eclairage, procede de fabrication d'un dispositif electroluminescent a semiconducteur, et procede de fabrication d'un element electroluminescent a semiconducteur
US20100120237A1 (en) * 2008-11-10 2010-05-13 Stanley Electric Co., Ltd. Method of manufacturing semiconductor devices
DE112011102068T5 (de) * 2010-06-18 2013-03-28 Soraa, Inc. Dreieckförmig oder rautenförmig geformte gallium- und stickstoffhaltige anordnung für optische bauelemente

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