WO2020003998A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2020003998A1
WO2020003998A1 PCT/JP2019/022997 JP2019022997W WO2020003998A1 WO 2020003998 A1 WO2020003998 A1 WO 2020003998A1 JP 2019022997 W JP2019022997 W JP 2019022997W WO 2020003998 A1 WO2020003998 A1 WO 2020003998A1
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WO
WIPO (PCT)
Prior art keywords
substrate
area
main surface
display
spacers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/022997
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English (en)
Japanese (ja)
Inventor
みどり 塚根
絵美 日向野
元希 遊津
敏行 日向野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Inc
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Japan Display Inc
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Filing date
Publication date
Application filed by Japan Display Inc filed Critical Japan Display Inc
Publication of WO2020003998A1 publication Critical patent/WO2020003998A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements

Definitions

  • the embodiment of the present invention relates to a display device.
  • a liquid crystal display device or the like is known as a display device.
  • a liquid crystal display device includes a liquid crystal display panel and a lighting device.
  • the liquid crystal display panel includes a display area and a non-display area surrounding the display area.
  • a highly reliable display device is required as a display device.
  • This embodiment provides a highly reliable display device.
  • the display device includes: A first substrate including a first main surface and a second main surface opposite to the first main surface, the first substrate being located in a display region and a non-display region outside the display region; A second substrate positioned in the display area and the non-display area, and a third substrate positioned in the non-display area; A display material comprising: a sealing material that joins the first substrate and the second substrate; and a liquid crystal layer provided in a space surrounded by the first substrate, the second substrate, and the sealing material.
  • the non-display area has a peripheral area including a first area, and a frame area located between the display area and the peripheral area and surrounding the display area, wherein the sealant and the liquid crystal layer are provided.
  • the first distance of the frame area is the same as the first distance of the display area, and at least the first distance of the first area of the first distance of the peripheral area is the display area. Is shorter than the first distance.
  • FIG. 1 is a perspective view showing a display device according to one embodiment.
  • FIG. 2 is another perspective view showing the display device.
  • FIG. 3 is a perspective view showing a lighting device of the display device.
  • FIG. 4 is an exploded plan view showing a display panel, a driving IC, and a wiring board of the display device.
  • FIG. 5 is a circuit diagram showing a display cell and a driving IC of the display panel, and also shows a circuit configuration of one pixel.
  • FIG. 6 is a cross-sectional view showing the display panel along a line VI-VI in FIG.
  • FIG. 7 is a sectional view showing a part of the display panel.
  • FIG. 8 is a cross-sectional view of the display device taken along line VIII-VIII in FIG. FIG.
  • FIG. 9 is a cross-sectional view showing the display device along the line IX-IX in FIG.
  • FIG. 10 is a sectional view showing a part of the display cell in a developed manner.
  • FIG. 11 is a cross-sectional view showing a part of a display cell according to a first modification of the embodiment in an expanded manner.
  • FIG. 12 is a cross-sectional view showing a part of a display cell according to Modification 2 of the embodiment in an expanded manner.
  • FIG. 13 is a cross-sectional view showing a part of a display cell according to Modification 3 of the embodiment in an expanded manner.
  • FIG. 14 is a cross-sectional view showing a part of a display cell according to Modification Example 4 of the above embodiment in a developed manner.
  • FIG. 15 is a cross-sectional view showing a part of a display cell according to Modification Example 5 of the above embodiment in a developed manner.
  • FIG. 1 is a perspective view showing a display device DSP according to one embodiment.
  • FIG. 2 is another perspective view showing the display device DSP.
  • FIG. 3 is a perspective view showing the illumination device IL of the display device DSP.
  • the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees.
  • the first direction X and the second direction Y correspond to directions parallel to the main surface of the substrate constituting the display device DSP
  • the third direction Z corresponds to the thickness direction of the display device DSP.
  • the direction toward the tip of the arrow indicating the third direction Z is referred to as “up”, and the direction from the tip of the arrow to the opposite direction is referred to as “down”.
  • the second member may be in contact with the first member or may be located away from the first member. It may be. Viewing the XY plane defined by the first direction X and the second direction Y from the tip side of the arrow indicating the third direction Z is referred to as plan view.
  • the display device DSP includes a lighting device IL, a display panel PNL, a driving IC $ DD as a first driver, a wiring board F1, and the like.
  • the display panel PNL includes a display area DA and a non-display area NDA outside the display area DA.
  • the lighting device IL has a plate-like shape.
  • the illumination device IL is configured to emit light to at least the display area DA of the display panel PNL.
  • the illumination device IL includes an upper surface MU, a first side surface MS1, and a first corner C1a extending linearly between the upper surface MU and the first side surface MS1.
  • the lighting device IL includes a lower surface MB opposite to the upper surface MU, a second side surface MS2 provided continuously from the first side surface MS1, and a third side surface MS3 opposite to the first side surface MS1. , A fourth side surface MS4 opposite to the second side surface MS2.
  • the first side surface MS1, the second side surface MS2, the third side surface MS3, and the fourth side surface MS4 have a rectangular shape.
  • the upper surface MU and the lower surface MB have, for example, a rectangular shape as a square.
  • Each of the upper surface MU and the lower surface MB has a pair of long sides extending in the first direction X and a pair of short sides extending in the second direction Y.
  • the illumination device IL includes a first corner C1b linearly extending between the upper surface MU and the second side surface MS2, and a first corner C1b linearly extending between the upper surface MU and the third side surface MS3.
  • a second corner C2d extending linearly between the fourth side surface MS4 and the lower surface MB.
  • the first corners C1a, C1c and the second corners C2a, C2c extend in the first direction X, and the first corners C1b, C1d and the second corners C2b, C2d extend in the second direction Y. I have.
  • the illumination device IL includes a light guide LG and a light source unit LU that emits light toward the light guide LG.
  • the light source unit LU has a fourth side surface MS4.
  • the light guide LG includes a light guide plate located at least in the display area DA.
  • the light guide LG includes a light guide plate, a frame portion having a first side surface MS1, a second side surface MS2, and a third side surface MS3, and a light reflection plate having a lower surface MB.
  • the frame portion and the light reflection plate surround the light guide plate together with the light source unit LU.
  • the surface of the frame portion on the light guide plate side may have light reflectivity similarly to the light reflection plate.
  • the configuration of the illumination device IL is not limited to the above configuration, and can be variously modified.
  • the illumination device IL may be formed without the frame portion and the light reflection plate.
  • the light guide plate may have a first side surface MS1, a second side surface MS2, a third side surface MS3, a lower surface MB, and the like.
  • the display area DA of the display panel PNL faces the upper surface MU of the lighting device IL.
  • the non-display area NDA of the display panel PNL is bent along the illumination device IL, and faces the upper surface MU, the first side surface MS1, the second side surface MS2, the third side surface MS3, the fourth side surface MS4, and the lower surface MB.
  • the drive IC #DD and the wiring board F1 face the lower surface MB.
  • the drive IC #DD is mounted on the non-display area NDA of the display panel PNL, and the wiring board F1 is connected to the non-display area NDA of the display panel PNL.
  • the non-display area NDA of the display panel PNL has a frame area FA and a peripheral area AP.
  • the frame area FA is located between the display area DA and the peripheral area AP, surrounds the display area DA, and faces the upper surface MU of the lighting device IL.
  • the non-display area NDA of the display panel PNL has four peripheral areas AP1, AP2, AP3, and AP4 extending independently of each other.
  • Each of the peripheral regions AP1, AP2, AP3, and AP4 faces one corresponding side surface MS and the lower surface MB of the lighting device IL.
  • the extension amount (length) of each of the peripheral regions AP2, AP3, and AP4 may be shorter than the example shown in FIG. In this case, each of the peripheral areas AP2, AP3, and AP4 only needs to face one corresponding side surface MS of the illumination device IL, and does not have to face the lower surface MB.
  • FIG. 4 is an exploded plan view showing the display panel PNL, the driving IC DD, and the wiring board F1 of the display device DSP.
  • the display panel PNL has a display cell CL for displaying an image.
  • the display cell CL has a first substrate SUB1 and a second substrate SUB2.
  • the driving IC DD is mounted on the first substrate SUB1, and the wiring substrate F1 is connected to the first substrate SUB1.
  • the second substrate SUB2 is overlaid on the first substrate SUB1 except for a region for the drive IC DD and the wiring substrate F1.
  • the display cell CL has an octagonal shape in plan view.
  • the display cell CL includes a display area DA, a frame area FA, and peripheral areas AP1, AP2, AP3, and AP4.
  • the peripheral area AP1 includes a first area AP1a, a second area AP1b, a third area AP1c, and a fourth area AP1d.
  • the peripheral areas AP2, AP3, and AP4 also include first to fourth areas.
  • the code corresponding to the first area is suffixed with a
  • the code corresponding to the second area is suffixed with b
  • the code corresponding to the third area is suffixed with c
  • the symbol “d” is added to the end of the code corresponding to the area.
  • the first and third regions are hatched.
  • the driving IC #DD is located in the fourth area AP1d of the peripheral area AP1, and the wiring board F1 is physically fixed to the fourth area AP1d.
  • the first to fourth areas are arranged in order from the frame area FA side.
  • the first to fourth areas are arranged in the second direction Y.
  • the first to fourth areas are arranged in the first direction X.
  • the first area AP1a extends along the first corner C1a (in the first direction X), and the third area AP1c extends along the second corner C2a (in the first direction X).
  • the first area AP2a extends along the first corner C1b (in the second direction Y), and the third area AP2c extends along the second corner C2b (in the second direction Y).
  • the first area AP3a extends along the first corner C1c (in the first direction X)
  • the third area AP3c extends along the second corner C2c (in the first direction X).
  • Extends In the peripheral area AP4, the first area AP4a extends along the first corner C1d (in the second direction Y), and the third area AP4c extends along the second corner C2d (in the second direction Y).
  • FIG. 5 is a circuit diagram showing the display cell CL and the driving IC DD, and also shows a circuit configuration of one pixel PX. Note that, here, an example of a circuit diagram is shown, and the circuit diagram is not limited to the circuit diagram shown in FIG.
  • the display cell CL has a plurality of pixels PX, a plurality of scanning lines G (G1 to Gn), and a plurality of signal lines S (S1 to Sm) in the display area DA. And an electrode CE.
  • the plurality of pixels PX are arranged in a matrix in the first direction X and the second direction Y.
  • each of the scanning lines G extends in the first direction X
  • each of the signal lines S extends in the second direction Y.
  • the display cell CL has a scanning line driving circuit GD as a second driver and a signal line driving circuit SD as a third driver.
  • Each of the scanning lines G extends to the non-display area NDA and is connected to the scanning line driving circuit GD.
  • the scanning line driving circuit GD may be provided also in the peripheral area AP4, and may drive a plurality of scanning lines G using two scanning line driving circuits GD.
  • Each of the signal lines S extends to the non-display area NDA and is connected to the signal line driving circuit SD.
  • the common electrode CE is shared by a plurality of pixels PX.
  • the scanning line driving circuit GD, the signal line driving circuit SD, and the common electrode CE are electrically connected to the driving IC $ DD.
  • the signal line drive circuit SD may be incorporated in the drive IC $ DD without being independent from the drive IC $ DD.
  • the drive IC #DD is electrically connected to a pad group (OLB pad group) PG for outer lead bonding (Outer Lead Bonding) of the display cell CL.
  • the wiring board F1 is electrically connected to the OLB pad group PG.
  • Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like.
  • the switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S.
  • the pixel electrode PE is electrically connected to the switching element SW.
  • the pixel electrode PE of each pixel PX faces the common electrode CE.
  • the liquid crystal layer LC is driven by an electric field generated between the pixel electrode PE and the common electrode CE.
  • the storage capacitor CS is coupled to the pixel electrode PE.
  • the storage capacitor CS is formed, for example, between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.
  • the display cell CL of the present embodiment is a liquid crystal display cell
  • the display panel PNL is a liquid crystal display panel
  • the display device DSP is a liquid crystal display device.
  • the pixel PX is provided in a display mode using a vertical electric field along a normal line of the main surface of the first substrate SUB1.
  • a display mode using an oblique electric field inclined in an oblique direction a display mode using a horizontal electric field along the main surface of the first substrate SUB1, and a combination of the vertical electric field, the horizontal electric field, and the oblique electric field are appropriately combined.
  • the main surface of the first substrate SUB1 is a surface parallel to the XY plane defined by the first direction X and the second direction Y.
  • FIG. 6 is a cross-sectional view showing the display panel PNL along the line VI-VI in FIG.
  • the display cell CL includes a first substrate SUB1, a second substrate SUB2, a sealing material SL, and a liquid crystal layer LC.
  • the first substrate SUB1 includes a first main surface 1 and a second main surface 2 opposite to the first main surface, and is located in the display area DA and the non-display area NDA.
  • the second substrate SUB2 is opposed to the first substrate SUB1 with a predetermined gap.
  • the second substrate SUB2 includes a third main surface 3 facing the second main surface 2 with a gap therebetween, and a fourth main surface 4 opposite to the third main surface, and includes a display area DA and a non-display area NDA. It is located in.
  • the second substrate SUB2 has a light shielding layer LS in the non-display area NDA.
  • the sealing material SL is provided between the first substrate SUB1 and the second substrate SUB2, is located in the non-display area NDA, surrounds the display area DA, and joins the first substrate SUB1 and the second substrate SUB2. .
  • the liquid crystal layer LC is provided in a space surrounded by the first substrate SUB1, the second substrate SUB2, and the sealing material SL. The boundary between the sealing material SL and the liquid crystal layer LC is located in the frame area FA.
  • the display panel PNL includes, in addition to the display cell CL, a first optical film OF1, a second optical film OF2, an adhesive layer AD1 interposed between the display cell CL and the first optical film OF1, and a display cell CL. And an adhesive layer AD2 interposed between the second optical film OF2.
  • the first optical film OF1 includes the first polarizing plate PL1, and is bonded to the first substrate SUB1 by the bonding layer AD1.
  • the second optical film OF2 includes a second polarizing plate PL2, and is bonded to the second substrate SUB2 by an adhesive layer AD2.
  • the first optical film OF1 and the second optical film OF2 may include not only the polarizing plate PL but also other optical functional layers such as a retardation plate.
  • the first optical film OF1 faces the entire first substrate SUB1.
  • the second optical film OF2 faces the entire area of the second substrate SUB2.
  • the first optical film OF1 and the second optical film OF2 only need to face at least the display area DA of the display cell CL.
  • FIG. 7 is a sectional view showing a part of the display panel PNL.
  • the illustrated configuration example of the pixel PX corresponds to an example in which a display mode using a horizontal electric field is applied.
  • the first substrate SUB1 includes an insulating substrate 10, insulating layers 11 to 16, a lower light-shielding layer US, a semiconductor layer SC, a switching element SW, a common electrode CE, a pixel electrode PE, and an alignment film AL1.
  • the insulating substrate 10 is formed of a resin material such as polyimide as an organic insulating material, and is a substrate having flexibility and light transmittance. Insulating substrate 10 includes first main surface 1.
  • the insulating layer 11 is disposed on the insulating substrate 10.
  • the lower light-shielding layer US is located on the insulating layer 11 and is covered by the insulating layer 12.
  • the first substrate SUB1 may be formed without the insulating layer 11, and in this case, the lower light-shielding layer US is located on the insulating substrate 10.
  • the semiconductor layer SC is located on the insulating layer 12 and is covered by the insulating layer 13.
  • the semiconductor layer SC is formed of, for example, polycrystalline silicon, but may be formed of amorphous silicon or an oxide semiconductor.
  • the gate electrodes GE1 and GE2 are located on the insulating layer 13 and are covered by the insulating layer 14.
  • the gate electrodes GE1 and GE2 are electrically connected to one of the scanning lines G shown in FIG.
  • the source electrode SE and the drain electrode DE are located on the insulating layer 14 and are covered by the insulating layer 15.
  • the source electrode SE is electrically connected to one of the signal lines S shown in FIG.
  • the source electrode SE is in contact with the semiconductor layer SC via a contact hole CH1 penetrating the insulating layers 13 and.
  • the drain electrode DE is in contact with the semiconductor layer SC via a contact hole CH2 penetrating through the insulating layers 13 and 14.
  • the common electrode CE is located on the insulating layer 15 and is covered by the insulating layer 16.
  • the pixel electrode PE is located on the insulating layer 16 and is covered with the alignment film AL1. Part of the pixel electrode PE is opposed to the common electrode CE via the insulating layer 16.
  • the common electrode CE and the pixel electrode PE are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the pixel electrode PE is in contact with the drain electrode DE via a contact hole CH3 penetrating the insulating layers 15 and 16 at a position overlapping the opening of the common electrode CE.
  • the insulating layers 11 to 14 and the insulating layer 16 are inorganic insulating layers formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure. Or a multilayer structure.
  • the insulating layer 15 is an organic insulating layer formed of an organic insulating material such as an acrylic resin as a resin.
  • the second substrate SUB2 includes the insulating substrate 20, the insulating layer 21, the light shielding layer BM, the color filter layer CF, the overcoat layer OC, and the alignment film AL2.
  • the insulating substrate 20 is a substrate formed of a resin material such as polyimide as an organic insulating material and having flexibility and light transmittance.
  • Insulating substrate 20 includes fourth main surface 4.
  • the insulating layer 21 is, for example, an inorganic insulating layer of silicon oxide, silicon nitride, silicon oxynitride, or the like, and may have a single-layer structure or a multilayer structure. Note that the second substrate SUB2 may be formed without the insulating layer 21. In this case, the light shielding layer BM and the color filter layer CF are located on the side of the insulating substrate 20 facing the first substrate SUB1.
  • the light shielding layer BM and the color filter layer CF are located on the side of the insulating layer 21 facing the first substrate SUB1.
  • the light shielding layer BM can be formed collectively using the same material as the light shielding layer LS shown in FIG.
  • the light-blocking layer BM is arranged at a position facing each of wiring portions such as the signal line S, the scanning line G, and the switching element SW.
  • the color filter layer CF is arranged at a position facing the pixel electrode PE, and a part thereof overlaps the light shielding layer BM.
  • the overcoat layer OC covers the color filter layer CF.
  • the alignment film AL2 covers the overcoat layer OC.
  • the liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is held between the alignment films AL1 and AL2.
  • the liquid crystal layer LC contains liquid crystal molecules.
  • Such a liquid crystal layer LC is made of a positive liquid crystal material (having a positive dielectric anisotropy) or a negative liquid crystal material (having a negative dielectric anisotropy).
  • the thickness T10 of the insulating substrate 10 and the thickness T20 of the insulating substrate 20 are uniform over the entire display area DA, frame area FA, and peripheral area AP, respectively.
  • FIG. 8 is a cross-sectional view showing the display device DSP along the line VIII-VIII in FIG.
  • the first optical film OF1 is fixed to the display cell CL and is located between the display cell CL and the lighting device IL.
  • the first optical film OF1 is in contact with the upper surface MU, the first side surface MS1, the third side surface MS3, and the lower surface MB of the lighting device IL.
  • the first area AP1a faces the first corner C1a and is bent.
  • the second region AP1b faces the first side surface MS1.
  • the third area AP1c faces the second corner C2a and is bent.
  • the fourth area AP1d faces the lower surface MB.
  • the first area AP3a faces the first corner C1c and is bent.
  • the second region AP3b faces the third side surface MS3.
  • the third area AP3c faces the second corner C2c and is bent.
  • the fourth area AP3d faces the lower surface MB.
  • FIG. 9 is a sectional view showing the display device DSP along the line IX-IX in FIG. As shown in FIG. 9, the first optical film OF1 is further in contact with the second side surface MS2 and the fourth side surface MS4 of the lighting device IL.
  • the first area AP2a faces the first corner C1b and is bent.
  • the second area AP2b faces the second side surface MS2.
  • the third area AP2c faces the second corner C2b and is bent.
  • the fourth area AP2d faces the lower surface MB.
  • the first area AP4a faces the first corner C1d and is bent.
  • the second region AP4b faces the fourth side surface MS4.
  • the third area AP4c faces the second corner C2d and is bent.
  • the fourth area AP4d faces the lower surface MB.
  • FIG. 10 is a sectional view showing a part of the display cell CL in an expanded manner.
  • the distance from the first main surface 1 to the fourth main surface 4 is defined as a first distance D1.
  • the first distance D1 is a linear distance in the third direction Z in FIG.
  • the first distance D1 is the shortest distance from the first main surface 1 to the fourth main surface 4.
  • the first distance D1 of the frame area FA is the same as the first distance D1 of the display area DA.
  • At least the first distance D1 of the first area AP1a among the first distances D1 of the peripheral area AP1 is shorter than the first distance D1 of the display area DA.
  • the first distance D1 of the second area AP1b, the third area AP1c, and the fourth area AP1d is the same as the first distance D1 of the first area AP1a.
  • the first distance D1 of the second area AP1b is shorter than the first distance D1 of the display area DA.
  • the distance from the second main surface 2 to the third main surface 3 is defined as a second distance D2.
  • the second distance D2 is a linear distance in the third direction Z in FIG.
  • the second distance D2 is the shortest distance from the second main surface 2 to the third main surface 3.
  • the second distance D2 of the frame area FA is the same as the second distance D2 of the display area DA.
  • At least the second distance D2 of the first area AP1a among the second distances D2 of the peripheral area AP1 is shorter than the second distance D2 of the display area DA.
  • the second distance D2 of the second area AP1b, the third area AP1c, and the fourth area AP1d is the same as the second distance D2 of the first area AP1a.
  • the display cell CL has a plurality of spacers SP.
  • the spacer SP is located between the first substrate SUB1 and the second substrate SUB2, and holds a gap between the first substrate SUB1 and the second substrate SUB2.
  • the plurality of spacers SP include a plurality of first spacers SP1 located in the display area DA and the frame area FA, and a plurality of second spacers SP2 located in at least the first area AP1a of the peripheral area AP1. .
  • the spacers SP in the second region AP1b, the third region AP1c, and the fourth region AP1d are also the second spacers SP2.
  • the length L2 of the second spacer SP2 is shorter than the length L1 of the first spacer SP1.
  • the plurality of first spacers SP1 and the plurality of second spacers SP2 are fixed to one of the first substrate SUB1 and the second substrate SUB2, respectively, and the second main surface 2 or the second main surface 2, which is a main surface of the other substrate, is provided.
  • 3 is a columnar spacer that contacts the main surface 3.
  • the first spacer SP1 and the second spacer SP2 are fixed to the second substrate SUB2 and are in contact with the second main surface 2 of the first substrate SUB1. Therefore, the height (L2) of the second spacer SP2 is smaller than the height (L1) of the first spacer SP1.
  • both the first substrate SUB1 and the second substrate SUB2 are distorted.
  • only one of the first substrate SUB1 and the second substrate SUB2 may be distorted.
  • the peripheral regions AP1, AP2, AP3, and AP4 of the display panel PNL can be bent along the illumination device IL. As shown in FIG. 2, the peripheral regions AP1, AP2, AP3, and AP4 can be folded on the back surface (lower surface MB) of the display device DSP. Thereby, the frame on the surface of the display device DSP can be reduced.
  • the first distance D1 of each of the first area AP1a and the third area AP1c is shorter than the first distance D1 of the display area DA.
  • the stress applied to the display cell CL when the display panel PNL is bent, as compared with the case where the first distance D1 of each of the first area AP1a and the third area AP1c is the same as the first distance D1 of the display area DA ( Stress) can be reduced. Accordingly, in the peripheral regions AP1 such as the first region AP1a and the third region AP1c, it is possible to reduce damage, buckling, distortion, and the like of the insulating substrates 10, 20.
  • the distortion is not a desired distortion that occurs near the boundary between the frame area FA and the first area AP1a, but an undesired distortion. From the above, a highly reliable display device DSP can be obtained.
  • FIG. 11 is a cross-sectional view showing a part of a display cell CL according to Modification Example 1 of the embodiment in an expanded manner.
  • the configuration of the peripheral area AP1 of the display cell CL will be described as a representative.
  • the technique of the first modification is also applicable to the peripheral areas AP2, AP3, and AP4.
  • the first distance D1 of the second area AP1b and the first distance D1 of the fourth area AP1d may be the same as the first distance D1 of the display area DA.
  • the first distance D1 of the first area AP1a among the first distances D1 of the peripheral area AP1 is shorter than the first distance D1 of the display area DA.
  • the first distance D1 of the first area AP1a is the same as the first distance D1 of the third area AP1c.
  • the second distance D2 of the first area AP1a is shorter than the second distance D2 of the display area DA, and is equal to the second distance D2 of the third area AP1c.
  • the adjustment is performed using the spacer SP.
  • the first spacer SP1 is located in the second area AP1b and the fourth area AP1d
  • the second spacer SP2 is located in the first area AP1a and the third area AP1c.
  • FIG. 12 is a cross-sectional view showing a part of a display cell CL according to Modification 2 of the embodiment in an expanded manner.
  • the configuration of the peripheral area AP1 of the display cell CL will be described as a representative.
  • the technique of the second modification is also applicable to the peripheral areas AP2, AP3, and AP4.
  • the plurality of second spacers SP2 may be spherical spacers.
  • the second spacer SP2 is in contact with the second main surface 2 and the third main surface 3, respectively.
  • the diameter (L2) of the second spacer SP2 is less than the height (L1) of the first spacer SP1.
  • FIG. 13 is a cross-sectional view showing a part of a display cell CL according to a third modification of the embodiment in an expanded manner.
  • the configuration of the peripheral area AP1 of the display cell CL will be described as a representative.
  • the technique of the third modification is applicable to the above-described peripheral areas AP2, AP3, and AP4.
  • the first substrate SUB1 includes an insulating substrate 10 and an insulating layer 15 as an organic insulating layer.
  • illustration of the first substrate SUB1 other than the insulating substrate 10 and the insulating layer 15 is omitted.
  • wiring, pads, and circuits are provided in the peripheral area AP1 of the display cell CL. Therefore, the portion shown in FIG. 13 of the first substrate SUB1 includes another insulating layer and a conductive layer.
  • the insulating layer 15 is located closer to the second substrate SUB2 than the insulating substrate 10.
  • the insulating layer 15 includes a plurality of recesses 15a.
  • the plurality of recesses 15a are respectively recessed from the second substrate SUB2 toward the insulating substrate 10.
  • the recess 15a penetrates the insulating layer 15. Note that the recess 15 a may be recessed, and does not need to penetrate the insulating layer 15.
  • the second main surface 2 is a surface of the insulating layer 15 on the second substrate SUB2 side.
  • the second main surface 2 is a surface of the insulating substrate 10 on the second substrate SUB2 side.
  • the second main surface 2 is not limited to the example shown in FIG.
  • a layer of the first substrate SUB1 closer to the second substrate SUB2 than the insulating layer 15 may have the second main surface 2.
  • the layer on the second substrate SUB ⁇ b> 2 side with respect to the insulating substrate 10 may have the second main surface 2.
  • the plurality of spacers SP are columnar spacers, and the plurality of first spacers SP1 located in the display area DA and the frame area FA, and the plurality of first spacers located in at least the first area AP1a and the third area AP1c of the peripheral area AP1. And two spacers SP2.
  • the height (L2) of each second spacer SP2 is the same as the height (L1) of each first spacer SP1.
  • the recess 15a and the second spacer SP2 are provided not only in the first area AP1a and the third area AP1c, but also in the second area AP1b and the fourth area AP1d.
  • the first spacer SP1 and the second spacer SP2 are fixed to the second substrate SUB2 and are in contact with the second main surface 2.
  • the first spacer SP1 is in contact with the surface of the insulating layer 15 on the second substrate SUB2 side as the second main surface 2. It is desirable that all the spacers SP are fixed together to the second substrate SUB2.
  • the first spacer SP1 may be fixed to the first substrate SUB1 and may be in contact with the third main surface 3.
  • the plurality of second spacers SP2 enter the corresponding recesses 15a, respectively, and are in contact with the second main surface 2.
  • the first distance D1 of the peripheral area AP1 is shorter than the first distance D1 of the display area DA by the thickness of the insulating layer 15.
  • the second distance D2 of the peripheral area AP1 is also shorter than the second distance D2 of the display area DA by the thickness of the insulating layer 15.
  • FIG. 14 is a cross-sectional view showing a part of a display cell CL according to Modification 4 of the embodiment in an expanded manner.
  • the configuration of the peripheral area AP1 of the display cell CL will be described as a representative.
  • the technique of the fourth modification is also applicable to the peripheral areas AP2, AP3, and AP4.
  • the plurality of spacers SP include a plurality of first spacers SP1 located in the display area DA and the frame area FA, and a plurality of spacers SP located in at least the first area AP1a and the third area AP1c of the peripheral area AP1.
  • the second spacer SP2 In the direction in which the second main surface 2 and the third main surface 3 face each other, the length L2 of each second spacer SP2 is the same as the length L1 of each first spacer SP1.
  • the second distance D2 of the frame area FA and the second distance D2 of at least the first area AP1a and the third area AP1c of the peripheral area AP1 are the same as the second distance D2 of the display area DA, respectively.
  • the insulating layer 15 is located in the display area DA and the frame area FA, and is not located in at least the first area AP1a and the third area AP1c of the peripheral area AP1. In the present embodiment, the insulating layer 15 is not located in the second area AP1b and the fourth area AP1d.
  • the second spacer SP2 is also provided in the second area AP1b and the fourth area AP1d. In the display area DA and the frame area FA, the first spacer SP1 faces the insulating layer 15.
  • the first distance D1 of the peripheral area AP1 is shorter than the first distance D1 of the display area DA by the thickness of the insulating layer 15.
  • the second distance D2 of the peripheral area AP1 is the same as the second distance D2 of the display area DA.
  • the same effect as the above embodiment can be obtained.
  • the above-described first modification (FIG. 11) and the third modification (FIG. 13) may be combined.
  • the first distance D1 of the second region AP1b and the fourth region AP1d is shorter than the first distance D1 of the display region DA by the thickness of the insulating layer 15.
  • the first distance D1 between the first area AP1a and the third area AP1c is equal to the difference between the height (L2) of the second spacer SP2 and the height (L1) of the first spacer SP1. It is shorter than the first distance D1 of the four areas AP1d.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

Dispositif d'affichage à fiabilité élevée. Ce dispositif d'affichage est pourvu d'un premier substrat, d'un second substrat et d'une cellule d'affichage ayant un matériau d'étanchéité et une couche de cristaux liquides. La frontière entre le matériau d'étanchéité et la couche de cristaux liquides est située dans une région de cadre. Une première distance de la région de cadre est la même que la première distance d'une région d'affichage. La première distance d'au moins une première région parmi les premières distances de régions périphériques est inférieure à la première distance de la région d'affichage.
PCT/JP2019/022997 2018-06-27 2019-06-10 Dispositif d'affichage Ceased WO2020003998A1 (fr)

Applications Claiming Priority (2)

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JP2018121866A JP2020003601A (ja) 2018-06-27 2018-06-27 表示装置
JP2018-121866 2018-06-27

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WO2020003998A1 true WO2020003998A1 (fr) 2020-01-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021149322A1 (fr) * 2020-01-21 2021-07-29 株式会社ジャパンディスプレイ Substrat flexible

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000122039A (ja) * 1998-10-21 2000-04-28 Toshiba Corp 液晶表示装置
JP2004151549A (ja) * 2002-10-31 2004-05-27 Seiko Epson Corp 電気光学パネル、電気光学装置、電子機器及び電気光学パネルの製造方法
US20160266672A1 (en) * 2013-08-13 2016-09-15 Polyera Corporation Optimization of Electronic Display Areas
US9684209B2 (en) * 2014-09-30 2017-06-20 Samsung Display Co., Ltd. Curved liquid crystal display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000122039A (ja) * 1998-10-21 2000-04-28 Toshiba Corp 液晶表示装置
JP2004151549A (ja) * 2002-10-31 2004-05-27 Seiko Epson Corp 電気光学パネル、電気光学装置、電子機器及び電気光学パネルの製造方法
US20160266672A1 (en) * 2013-08-13 2016-09-15 Polyera Corporation Optimization of Electronic Display Areas
US9684209B2 (en) * 2014-09-30 2017-06-20 Samsung Display Co., Ltd. Curved liquid crystal display

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021149322A1 (fr) * 2020-01-21 2021-07-29 株式会社ジャパンディスプレイ Substrat flexible
JP2021114587A (ja) * 2020-01-21 2021-08-05 株式会社ジャパンディスプレイ フレキシブル基板
JP7573968B2 (ja) 2020-01-21 2024-10-28 株式会社ジャパンディスプレイ フレキシブル基板

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