WO2020009020A1 - Transistor à effet de champ à effet tunnel - Google Patents

Transistor à effet de champ à effet tunnel Download PDF

Info

Publication number
WO2020009020A1
WO2020009020A1 PCT/JP2019/025825 JP2019025825W WO2020009020A1 WO 2020009020 A1 WO2020009020 A1 WO 2020009020A1 JP 2019025825 W JP2019025825 W JP 2019025825W WO 2020009020 A1 WO2020009020 A1 WO 2020009020A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
ingaassb
inp
effect transistor
tunnel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2019/025825
Other languages
English (en)
Japanese (ja)
Inventor
学 満原
拓也 星
杉山　弘樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of WO2020009020A1 publication Critical patent/WO2020009020A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]

Definitions

  • the present invention relates to a planar type tunnel field effect transistor.
  • IT devices such as network devices, servers, PCs, and mobile terminals are required to have a performance capable of processing a large amount of data at high speed.
  • IoT Internet of Things
  • power consumption of the IT device in the total power will increase sharply with the high performance of the IT device.
  • MOSFETs field-effect transistors
  • the power consumption of the MOSFET is proportional to the square of the drive voltage. Therefore, if the MOSFET can be operated at a low drive voltage, the power consumption of the IT device can be reduced as a result.
  • an on state and an off state are switched by changing a drain current according to a gate voltage.
  • a gate voltage In order to reduce the drive voltage of the MOSFET, it is important to rapidly change the drain current with a small gate voltage.
  • the gate voltage required to increase the drain current by one digit is used as an important performance index, and this physical quantity is called an S value (unit: mV / decade). The lower the S value, the lower the drive voltage can be expected, which leads to lower power consumption of the MOSFET.
  • MOSFETs In MOSFETs, studies are underway to reduce the S value by examining the device structure and channel material. At present, the most widespread field-effect transistor is a MOSFET, and the on / off operation is switched by changing the drain current by raising and lowering the energy position of a conduction band serving as a current path by a gate voltage. . With this MOSFET, it is difficult in principle to realize an S value smaller than 0.6 mV / decade. Therefore, it is difficult to dramatically reduce the power consumption of the MOSFET.
  • tunnel field effect transistor Since the tunnel field effect transistor (TFET) operates on a principle different from that of the MOSFET described above, the S value can be made smaller than 0.6 mV / decade. By using this tunnel field effect transistor, an on / off operation can be realized with a drive voltage smaller than that of a MOSFET. Therefore, in recent years, research and development of tunnel field effect transistors have been energetically advanced. Several device structures have been studied for the tunnel field effect transistor. Among them, a planar tunnel field effect transistor is a particularly promising structure because it has an element structure similar to that of a MOSFET and a MOSFET can be applied to a manufacturing process in many cases.
  • the planar type tunnel field effect transistor has a structure similar to the MOSFET as described above.
  • the tunnel field effect transistor includes, for example, a channel region 301 made of a compound semiconductor, a source region 302, and a drain region 303 formed at a predetermined interval from the source region 302.
  • the source region 302 is formed by making the channel layer 301 p-type
  • the drain region 303 is formed by making the channel layer 301 n-type.
  • a channel region 304 is formed in a region of the channel layer 301 between the source region 302 and the drain region 303.
  • the source region 302, the channel region 304, and the drain region 303 are arranged in this order in a gate length direction on a plane parallel to the surface of the channel layer 301.
  • a source electrode 305 is formed in connection with the source region 302, and a drain electrode 306 is formed in connection with the drain region 303. Further, a gate electrode 308 is formed over the channel region 304 with a gate insulating layer 307 interposed therebetween.
  • the difference between the tunnel field effect transistor and the MOSFET is the conductivity type of the source region and the drain region.
  • a MOSFET n-type MOSFET
  • the source region and the drain region are both n-type doped.
  • the tunnel field effect transistor n-type TFET
  • the source region 302 is p-type and the drain region 303 is n-type.
  • the tunnel field effect transistor has a pn junction, and this pn junction becomes a tunnel junction.
  • the interface between the channel region 304 and the source region 302 becomes the tunnel junction region 311.
  • an electric field applied to the tunnel junction region 311 is controlled by a gate voltage, so that a current flowing to the drain region 303 is changed to perform an on / off operation.
  • One of the important performance indicators of a tunnel field effect transistor is the ratio of the current in the on state to that in the off state. Specifically, assuming that the current in the on state is the on current and the off current in the off state, the higher the ratio of the on current to the off current (I ON / I OFF ), the better the device characteristics.
  • I ON / I OFF the ratio of the on current to the off current
  • the off-state current also increases, so that I ON / I OFF does not always increase. Therefore, it is difficult to obtain a high I ON / I OFF even if the tunnel field effect transistor is manufactured using only a material having a small band gap.
  • the band gap of ⁇ ⁇ ⁇ ⁇ InP ( ⁇ 1.35 eV) is larger than that of silicon ( ⁇ 1.12 eV), and high-quality products are commercially available as substrates. Further, it is relatively easy to grow a material such as InGaAs having a smaller band gap than silicon on InP using the substrate as InP. For this reason, studies are being made to apply InGaAs grown on an InP substrate or a quantum well made of InGaAs to the channel layer of a tunnel field effect transistor, and good device characteristics have been confirmed in the manufactured device (non-device). Patent Document 2, Non-Patent Document 3).
  • GaAsSb is a material that can be lattice-matched to InP and has a band gap as small as InGaAs.
  • a crystal having a large Sb composition ratio is difficult to grow (see Non-Patent Document 4), there are not many devices using GaAsSb at present.
  • the band gap of the material used for the channel region can be made smaller than InGaAs lattice matching with InP.
  • One of the methods is a method disclosed in Non-Patent Document 3 in which an InGaAs quantum well having a large In composition ratio is used for a channel layer. When using an InGaAs quantum well, it is necessary to increase the In composition ratio and increase the layer thickness in order to reduce the band gap.
  • the present invention has been made to solve the above problems, and has as its object to improve the device characteristics of a planar tunnel field effect transistor.
  • a tunnel field effect transistor includes a channel layer including an InGaAsSb layer formed of InGaAsSb formed on an InP layer formed of InP, a first conductivity type source region formed in the channel layer, and a source region.
  • a second conductivity type drain region formed in the channel layer at a predetermined interval, a source electrode formed in connection with the source region, a drain electrode formed in connection with the drain region, and a source region.
  • a gate electrode formed on a channel region between the drain region and the drain region, and the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
  • the channel layer may have a quantum well structure in which an InGaAsSb layer is a well layer and a layer made of InGaAs or InGaAsSb is a barrier layer.
  • the well layer may have a thickness of 4 nm or more and 20 nm or less, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less.
  • the barrier layer is preferably made of InGaAsSb, has a smaller lattice constant than InP, and has a tensile strain.
  • FIG. 1 is a sectional view showing a configuration of the tunnel field effect transistor according to the first embodiment of the present invention.
  • FIG. 2 is a characteristic diagram showing a result obtained by calculating a change in band gap according to the Sb composition ratio of InGaAsSb.
  • FIG. 3 shows the calculation of the tunnel current density for each of the case where the channel layer is composed of Si, the case where the channel layer is composed of InGaAs lattice-matched to InP, and the case where the channel layer is composed of InGaAsSb lattice-matched to InP.
  • FIG. 9 is a characteristic diagram showing the result of comparison.
  • FIG. 4 is a characteristic diagram in which a part of each result of the case where the channel layer shown in FIG.
  • FIG. 3 is a characteristic diagram showing electric field intensity dependence of current density.
  • FIG. 8 is a characteristic chart showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.1 when the lattice strain (compression strain) is changed.
  • FIG. 9 is a graph showing the results obtained by using the calculation method described in Non-Patent Document 7 to determine the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 when the lattice strain (compression strain) is changed.
  • FIG. FIG. 10 is a sectional view showing a layer structure of a multiple quantum well structure actually manufactured.
  • FIG. 10 is a sectional view showing a layer structure of a multiple quantum well structure actually manufactured.
  • FIG. 11 is a characteristic diagram showing a comparison between a measurement result (experiment) of an X-ray diffraction pattern of the manufactured multiple quantum well structure and a simulation result.
  • FIG. 12 is a characteristic diagram showing a photoluminescence emission spectrum at room temperature of the manufactured multiple quantum well structure.
  • FIG. 13 is a cross-sectional view showing a configuration of the tunnel field effect transistor.
  • FIG. 14 is a band diagram showing a change in band gap near the tunnel junction region in the ON state (solid line) and the OFF state (dotted line) of the tunnel field effect transistor.
  • This tunnel field effect transistor includes an InP layer 102 made of InP formed on a substrate 101, and a channel layer 103 formed on the InP layer 102.
  • the channel layer 103 includes an InGaAsSb layer made of InGaAsSb.
  • the channel layer 103 is an InGaAsSb layer.
  • the InGaAsSb layer has a composition ratio of Sb in the group V element of 0.01 to 0.3.
  • a source region 104 and a drain region 105 are formed at predetermined intervals.
  • the source region 104 has a first conductivity type (for example, p-type), and the drain region 105 has a second conductivity type (for example, n-type).
  • a source electrode 107 is formed so as to be electrically connected to the source region 104, and a drain electrode 108 is formed so as to be electrically connected to the drain region 105.
  • the first conductivity type may be n-type and the second conductivity type may be p-type.
  • a gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105.
  • the gate electrode 109 is formed over the channel region 106 of the channel layer 103 with the gate insulating layer 110 interposed.
  • the gate electrode 109 may be a Schottky connection with the channel layer 103.
  • the source region 104, the channel region 106, and the drain region 105 are arranged in the gate length direction on the plane parallel to the surface of the channel layer 103 in this order.
  • the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121.
  • an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
  • an InP layer 102 having a thickness of 0.1 ⁇ m and an InGaAsSb layer (channel layer 103) having a thickness of 0.1 ⁇ m are epitaxially grown on a substrate 101 made of semi-insulating InP.
  • an InP surface protection layer having a thickness of 20 nm is grown on the InGaAsSb layer. Note that the InP surface protective layer is not shown in FIG. 1 since it is completely removed by etching at the element stage.
  • TIn trimethylindium
  • TAGa triethylgallium
  • PH 3 phosphine
  • AsH 3 arsine
  • TDMASb trisdimethylaminoantimony
  • MOMBE organometallic molecular beam epitaxy
  • the Sb composition ratio of the channel layer 103 is set to 0.15, and the group III composition is adjusted so as to substantially match lattice with InP.
  • an epiwafer is prepared in which only the channel layer 103 shown in FIG. 1 is replaced with InGaAs which is substantially lattice-matched to InP.
  • the band gap is 0.69 eV for InGaAsSb and 0.74 eV for InGaAs.
  • Si is ion-implanted only into a region to be a drain, and a necessary heat treatment is performed to activate the Si, thereby forming a drain region 105.
  • ALD atomic layer deposition
  • the wafer is heated in a metal organic vapor phase epitaxy (MOVPE) apparatus while supplying phosphine and diethyl zinc (DEZn), so that part of the InGaAsSb is made p-type and the source region 104 is formed.
  • MOVPE metal organic vapor phase epitaxy
  • a gate insulating layer 110 is formed in a region to be a gate by depositing an insulating material by an atomic layer deposition method, a metal to be a gate electrode 109 is deposited by an electron beam deposition apparatus. By using a lift-off process, metal deposited on portions other than the gate electrode 109 is removed. In FIG. 1, the length of the gate electrode 109 in the horizontal direction (gate length direction) is 1 ⁇ m. After removing the insulating film deposited over the regions to be the source electrode and the drain electrode, the source electrode 107 and the drain electrode 108 are formed by a lift-off process. Thereafter, a heat treatment necessary for electrode formation is performed.
  • the planar-type tunneling electric field transistor using InGaAsSb for the channel layer 103 in the first embodiment shown in FIG. 1 has a drain current of 1.0 m under the condition that the source voltage is 60 mV and (gate voltage ⁇ threshold voltage) is 1 V. 7 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 55 mV / dec. It is.
  • the drain current of the tunnel electric field transistor using InGaAs for comparison as the channel layer under the same voltage condition is 1.3 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 63 mV / dec. . It is. From these results, it can be seen that in the planar tunneling electric field transistor, by changing the channel layer from InGaAs to InGaAsSb, the drain current can be increased and the S value can be reduced.
  • the metalorganic molecular beam epitaxy method is used as the crystal growth method.
  • InGaAsSb on InP can be crystallized by using another growth method such as the metalorganic vapor phase epitaxy method or the molecular beam epitaxy method. Can grow. Therefore, it is apparent that the tunnel electric field transistor using InGaAsSb as the channel layer 103 in Embodiment 1 can be manufactured by any crystal growth method that can grow InGaAsSb.
  • the band gap can be made smaller than that of InGaAs.
  • the Sb composition ratio of InGaAsSb is 0.15
  • the Sb composition ratio is 0.01 or more and 0.3 or less
  • InGaAsSb can be relatively easily crystal-grown. Therefore, needless to say, the present invention is effective even when InGaAsSb that does not lattice-match with InP is used, and when InGaAsSb having an Sb composition ratio other than 0.15 is used for the channel layer.
  • the source region 104 and the drain region 105 are formed by doping, Zn diffusion and ion implantation of Si are used, respectively.
  • Various doping methods other than the above are known. For this reason, the doping method is not limited to the above method.
  • the Sb composition of the channel layer 103 in the tunnel field effect transistor according to the first embodiment will be described.
  • a structure in which a material having a small bandgap is stacked as a channel layer on a layer having a large bandgap or a substrate is useful for improving device characteristics of a planar tunnel field effect transistor.
  • a structure in which InGaAs is grown on an InP layer (InP substrate) has been used.
  • InGaAsSb is useful as a material having a small band gap. This is because the band gap of InGaAsSb can be reduced even when the lattice constant is the same as that of InGaAs. In addition, in InGaAsSb, it is easy to obtain good crystallinity if the Sb composition ratio is small.
  • InGaAsSb also contains Sb as a group V element, but when the Sb composition ratio is small, a high-quality crystalline film can be grown (see Non-Patent Document 5). Further, InGaAsSb has an advantage that the band gap can be made smaller than that of InGaAs even if the Sb composition ratio is small, as described below.
  • FIG. 2 shows a result obtained by calculating a change in band gap depending on the Sb composition ratio of InGaAsSb.
  • the case where the lattice mismatch with InP is 0% is the band gap of InGaAsSb in the case of lattice matching with InP.
  • the bandgap of InGaAsSb lattice-matched to InP is such that when the Sb composition ratio is increased, the Sb composition ratio decreases from 0 to 0.25, is almost constant from 0.25 to 0.30, and is 0.30. It increases when it gets bigger. That is, in the case of InGaAsSb, when the Sb composition ratio is 0.30 or less, an effect of reducing the band gap by increasing the Sb composition ratio is observed.
  • InGaAsSb The above-mentioned Sb composition ratio of InGaAsSb needs to determine an effective composition ratio range in consideration of not only the band gap but also the ease of crystal growth.
  • the crystal growth of a group III-V compound semiconductor is greatly affected by the group V elements contained and their composition ratios.
  • InGaAsSb can be considered as a mixed crystal of an As-based material (InGaAs) and an Sb-based material (GaAsSb).
  • InGaAs on the InP layer can grow a crystal having good crystallinity relatively easily.
  • GaAsSb on the InP layer is more difficult to grow as compared with InGaAs.
  • One of the major factors is that Sb tends to remain on the surface during crystal growth, and the range of the raw material supply amount and growth temperature for obtaining good crystallinity is narrow (see Non-Patent Document 4).
  • the Sb composition ratio of InGaAsSb used for the channel layer 103 is desirably 0.01 or more. From the above, it is useful that the Sb composition ratio of InGaAsSb used for the channel layer 103 is 0.01 or more and 0.3 or less.
  • InGaAsSb having a lattice constant larger than that of InP laminate mismatch with InP: + 0.2%, + 0.5%, + 1.0%, + 1.5%) as well as the case of lattice matching with InP 3 also shows a change in the band gap depending on the Sb composition ratio. From this result, even in InGaAsSb having a larger lattice constant than InP, the change in the band gap due to the Sb composition ratio has the same tendency as in the case of lattice matching with InP. That is, when the Sb composition ratio is increased beyond 0.3, the band gap also increases.
  • the Sb composition ratio is desirably 0.01 or more and 0.3 or less.
  • FIG. 3 shows the calculation method described in Non-Patent Document 1 when the channel layer is made of Si, when the channel layer is made of InGaAs lattice-matched to InP, and when the channel layer is made of InGaAs lattice-matched to InP.
  • the tunnel current density is calculated for each of the cases where the configuration is made from FIG.
  • the horizontal axis in FIG. 3 is the electric field intensity at the tunnel junction interface.
  • the calculation was performed with the reverse bias voltage applied from the outside set to 0.3V.
  • InGaAsSb cases where the Sb composition was 0.1, 0.2, 0.3, and 0.4 were examined.
  • FIG. 4 is an enlarged view showing a part of each result of the case where the channel layer shown in FIG. 3 is made of InGaAs and the case where the channel layer is made of InGaAsSb.
  • a tunnel junction having a channel layer made of InGaAsSb can obtain a larger tunnel current density than InGaAs. More specifically, in InGaAsSb, the tunnel current density changes depending on the Sb composition ratio.
  • the tunnel current density increases by increasing the Sb composition ratio of InGaAsSb from 0.1 to 0.2, but hardly changes even when it is increased from 0.2 to 0.3.
  • the Sb composition ratio is further increased from 0.3 to 0.4, the tunnel current density decreases sharply and becomes smaller than when the Sb composition ratio is 0.1. From these facts, it is understood that the Sb composition ratio of InGaAsSb used for the channel layer 103 is desirably 0.3 or less in order to increase the tunnel current density.
  • This tunnel field effect transistor includes an InP layer 102 formed on a substrate 101, and a channel layer 103 formed on the InP layer 102.
  • a source region 104 and a drain region 105 are formed at predetermined intervals.
  • the source region 104 is, for example, p-type
  • the drain region 105 is, for example, n-type.
  • a source electrode 107 is formed so as to be electrically connected, and in the drain region 105, a drain electrode 108 is formed so as to be electrically connected. Further, a gate electrode 109 is formed on the channel region 106 between the source region 104 and the drain region 105 with a gate insulating layer 110 interposed therebetween.
  • the channel layer 103 has a quantum well structure in which the InGaAsSb layer is the well layer 112 and the layer made of InGaAs or InGaAsSb is the barrier layer 111. Further, this quantum well structure is formed on an underlayer 113 made of InGaAsSb. In the second embodiment, the channel layer 103 includes the underlying layer 113 and a quantum well structure including the barrier layer 111 and the well layer 112 formed thereon.
  • the well layer 112 may have a thickness of 4 nm to 20 nm, a lattice constant larger than that of InP, and a compressive strain of 3.5% or less.
  • the barrier layer 111 may be made of InGaAsSb and have a smaller lattice constant than InP and have a tensile strain.
  • the interface between the channel region 106 and the source region 104 becomes the tunnel junction region 121.
  • an electric field applied to the tunnel junction region 121 is controlled by a gate voltage, so that a current flowing to the drain region 105 is changed to realize an on / off operation.
  • an InP layer 102 having a layer thickness of 0.1 ⁇ m is grown on a substrate 101 made of semi-insulating InP, and an InP layer 102 made of InGaAsSb lattice-matched to InP with an Sb composition ratio of 0.07 is formed thereon.
  • the stratum 113 is grown.
  • a well layer 112 made of InGaAsSb having a thickness of 12 nm, a barrier layer 111 made of InGaAsSb having a composition ratio of Sb of 0.1, a tensile strain of 1.04%, and a thickness of 3 nm are grown.
  • an InP surface protection layer having a thickness of 20 nm is grown.
  • the source region 104 and the drain region 105 are formed, the gate insulating layer 110 and the gate electrode 109 are formed, and the source electrode 107 and the drain electrode 108 are formed in the same manner as in the first embodiment.
  • the source region 104 and the drain region 105 may be formed to a depth reaching the base layer 113, for example.
  • the planar-type tunneling electric field transistor using the strain-compensated quantum well structure of InGaAsSb according to the second embodiment for the channel layer 103 has a drain current of 1.0 m under the conditions of a source voltage of 60 mV and (gate voltage-threshold voltage) of 1 V. 9 ⁇ 10 ⁇ 1 ⁇ A / ⁇ m, and the minimum value of the S value is 51 mV / dec. It is.
  • the planar-type tunnel electric field transistor according to the second embodiment has a higher drain current and a lower minimum S value than the tunnel electric field transistor according to the first embodiment.
  • the strain-compensated quantum well structure of InGaAsSb for the channel layer 103, the band gap of the channel layer 103 can be reduced, and the device characteristics of the tunnel field effect transistor can be improved.
  • the strain compensation quantum well structure is used for the channel layer 103 has been described.
  • the well layer 112 made of InGaAsSb is used, the band gap of the channel layer 103 can be reduced. Therefore, even when a strained quantum well structure in which tensile strain is not applied to the barrier layer 111 or a quantum well structure in which the barrier layer 111 is made of InGaAs is used for the channel layer 103, device characteristics are improved as described above. Is clear.
  • InGaAsSb having a larger lattice constant than InP can have a smaller band gap than InGaAsSb lattice-matched to InP even with the same Sb composition ratio.
  • InGaAsSb having a lattice constant different from that of InP is crystal-grown, the generation of crystal defects due to lattice distortion becomes a problem.
  • the thickness of the well layer is too small in the InGaAsSb strained quantum well structure, the band gap increases due to the quantum size effect. In this case, the tunnel current in the tunnel field transistor decreases.
  • a description will be given of a range of the thickness of the well layer necessary for not significantly reducing the tunnel current density in the tunnel junction using the InGaAsSb strained quantum well.
  • FIG. 6 shows a tunnel current density in a tunnel junction using the strained quantum well structure when the well layer has a thickness of 2, 4, 6, 8, 10, 12 nm in the strained quantum well structure using InGaAsSb.
  • the Sb composition of the InGaAsSb well layer was 0.1
  • the lattice mismatch with InP was + 1.5%
  • the barrier layer was InGaAsSb with an Sb composition ratio of 0.1 and lattice matching with InP.
  • FIG. 6 also shows the result of the tunnel junction using InGaAs shown in FIG. 3 for comparison.
  • a larger tunnel current density can be obtained than in the case of using InGaAs.
  • the current density of the tunnel junction using the InGaAsSb strained quantum well changes depending on the thickness of the well layer. As shown in FIG. 6, the tunnel current density when the InGaAsSb strained quantum well is used increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm. But it does not increase rapidly. This indicates that the thickness of the strained InGaAsSb quantum well layer is desirably 4 nm or more.
  • the upper limit of the thickness of the well layer may be a thickness having a quantum size effect as a quantum well, specifically, 20 nm or less.
  • FIG. 6 shows an example in which the Sb composition ratio of the well layer is 0.1 and the lattice mismatch with InP is + 1.5%, but the Sb composition ratio is other than 0.1 as described later. And the lattice mismatch with InP is other than + 1.5%, the tunnel current density is different only in absolute value, and 4 nm or more is still effective as the well layer thickness.
  • the strain quantum well structure using InGaAsSb lattice-matched to InP is described as the barrier layer, but the present invention is also effective when a barrier layer that does not lattice-match is used.
  • a quantum well using a barrier layer to which lattice strain (tensile strain) opposite to that of the well layer is applied will be described.
  • a quantum well in which a barrier layer has lattice strain opposite to that of a well layer has an effect of compensating for lattice strain in the well layer, and is therefore called a strain-compensated quantum well.
  • the well layer in the present invention (Embodiment 2) is made of InGaAsSb to which a compressive strain is applied, it is necessary to apply a tensile strain to the barrier layer in order to form a strain compensation quantum well structure.
  • InInGaAsSb tensile strain can be easily applied by increasing the Ga composition ratio.
  • InGaAsSb having a high Ga composition ratio for the barrier layer band discontinuity in the conduction band changes, and confinement of electrons in the InGaAsSb well layer increases. This increase in electron confinement is also useful for improving device characteristics as described below.
  • FIG. 7 shows the tunneling of the tunnel junction using the strain-compensated quantum well structure in the case where the thickness of the well layer is 2, 4, 6, 8, 10, and 12 nm in the strain-compensated quantum well structure using InGaAsSb.
  • the electric field strength dependence of the current density is shown.
  • the Sb composition of the InGaAsSb well layer is 0.2
  • the lattice mismatch with InP is + 144%
  • the Sb composition ratio of the barrier layer is 0.1
  • the lattice mismatch with InP is -0.87%.
  • FIG. 7 also shows the result of the tunnel junction using InGaAs for comparison, as in FIG.
  • the tendency when the strain-compensated quantum well structure is used also shows the same tendency as when the strain-quantum well structure described with reference to FIG. 6 is used.
  • the tunnel current density increases sharply by increasing the layer thickness of the well layer from 2 nm to 4 nm, but thereafter, even if the layer thickness is increased, the current density does not increase sharply. Therefore, even when the strain compensation quantum well structure is used for the channel layer, a layer thickness of 4 nm or more is effective as the well layer.
  • the result shown in FIG. 7 is an example in which tensile strain is applied to the upper and lower barrier layers above the well layer.
  • tensile strain is applied to one of the upper and lower barrier layers, the quantum size effect exists and the InGaAsSb well layer Is used to obtain a small band gap, so that the effective range of the well layer thickness described above does not change.
  • the layer thickness at which the crystal defects begin to occur is called the critical layer thickness. It is desirable that the layer thickness of the quantum well used for the tunnel electric field transistor is 4 nm or more, and in order to make the layer thickness of the well layer 4 nm or more, the compressive strain applied to the well layer needs to be a certain value or less. In other words, the lattice strain at which the critical layer thickness becomes 4 nm is the upper limit of the lattice strain that can be applied to the well layer.
  • FIG. 8 shows the results obtained by using the calculation method described in Non-Patent Document 7 for the critical layer thickness when lattice strain (compression strain) is changed for InGaAsSb having an Sb composition ratio of 0.1. I have.
  • FIG. 9 shows the result of calculating the critical layer thickness of InGaAsSb having an Sb composition ratio of 0.2 by changing the lattice strain (compression strain) using the calculation method described in Non-Patent Document 7. Is shown.
  • the thickness of the well layer is larger than the curves shown in FIGS. 8 and 9, crystal defects are likely to occur. 8 and 9, the lattice strain at which the critical layer thickness is 4 nm is + 3.5% in both cases where the Sb composition ratio of InGaAsSb is 0.1 or 0.2. Therefore, when the InGaAsSb quantum well is used for the channel layer of the tunnel electric field transistor, the compressive strain of the well layer is desirably set to + 3.5% or less.
  • FIG. 10 is a sectional view showing a layer structure of the manufactured multiple quantum well structure.
  • a buffer layer 202 of InP having a thickness of 0.1 ⁇ m is grown on an InP substrate 201.
  • FIG. 11 shows a comparison between a measurement result (experiment) and a simulation result of the X-ray diffraction pattern of the above-described multiple quantum well structure.
  • the well layer 204 may be made of InGaAsSb with a compressive strain of 1.63% and a layer thickness of 12.9 nm
  • the barrier layer 203 may be made of InGaAsSb with a tensile strain of 1.04% and a layer thickness of 19.0 nm. Do you get it.
  • FIG. 12 shows a photoluminescence emission spectrum of the above-described multiple quantum well structure at room temperature.
  • the energy of the emission peak of photoluminescence is 0.57 eV.
  • the energy of the emission peak substantially matches the band gap of the well layer. For this reason, it was confirmed that the band gap of the strain compensation quantum well structure (multiple quantum well structure) using InGaAsSb was smaller than that of InGaAs (0.74 eV) lattice-matched to InP.
  • the channel layer is configured to include the InGaAsSb layer made of InGaAsSb formed on the InP layer made of InP, the device characteristics of the planar tunnel field effect transistor Can be improved.
  • the present invention in a planar tunnel field effect transistor, it is possible to increase the current in the ON state and to operate the transistor with a small gate voltage.
  • power consumption can be reduced, and as a result, energy saving of an electronic device can be realized.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention concerne un transistor à effet de champ à effet tunnel comprenant : une couche D'InP (102) qui est constituée d'InP et formée sur un substrat ; et une couche de canal (103) qui est formée sur la couche d'InP (102). La couche de canal (103) comprend une couche D'InGaAsSb qui est constituée d'InGaAsSb. Dans la couche d'InGaAsSb, le rapport de composition de Sb dans des éléments de groupe V est de 0,01 à 0,3. Une région de source (104) et une région de drain (105) sont formées à un intervalle prescrit dans la couche de canal (103). La région de source (104) est définie comme un premier type de conductivité (par exemple, type p), et la région de drain (105) est réglée en tant que second type de conductivité (par exemple, type n).
PCT/JP2019/025825 2018-07-03 2019-06-28 Transistor à effet de champ à effet tunnel Ceased WO2020009020A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-126659 2018-07-03
JP2018126659A JP2020009799A (ja) 2018-07-03 2018-07-03 トンネル電界効果トランジスタ

Publications (1)

Publication Number Publication Date
WO2020009020A1 true WO2020009020A1 (fr) 2020-01-09

Family

ID=69060966

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/025825 Ceased WO2020009020A1 (fr) 2018-07-03 2019-06-28 Transistor à effet de champ à effet tunnel

Country Status (2)

Country Link
JP (1) JP2020009799A (fr)
WO (1) WO2020009020A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230178964A1 (en) * 2020-05-25 2023-06-08 Nippon Telegraph And Telephone Corporation Strained Quantum Well Structure, Optical Semiconductor Device, and Semiconductor Laser
JPWO2022215105A1 (fr) * 2021-04-05 2022-10-13

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278397A (ja) * 2005-03-28 2006-10-12 Nippon Telegr & Teleph Corp <Ntt> 歪量子井戸構造及びその製造方法
JP2016154202A (ja) * 2015-02-20 2016-08-25 住友化学株式会社 トンネル電界効果トランジスタおよび電界効果トランジスタの製造方法
WO2017057329A1 (fr) * 2015-09-30 2017-04-06 国立大学法人北海道大学 Transistor à effet de champ et à effet tunnel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278397A (ja) * 2005-03-28 2006-10-12 Nippon Telegr & Teleph Corp <Ntt> 歪量子井戸構造及びその製造方法
JP2016154202A (ja) * 2015-02-20 2016-08-25 住友化学株式会社 トンネル電界効果トランジスタおよび電界効果トランジスタの製造方法
WO2017057329A1 (fr) * 2015-09-30 2017-04-06 国立大学法人北海道大学 Transistor à effet de champ et à effet tunnel

Also Published As

Publication number Publication date
JP2020009799A (ja) 2020-01-16

Similar Documents

Publication Publication Date Title
US7687799B2 (en) Methods of forming buffer layer architecture on silicon and structures formed thereby
US8653561B2 (en) III-nitride semiconductor electronic device, and method of fabricating III-nitride semiconductor electronic device
US9269577B2 (en) Method for manufacturing nitride semiconductor device
US7566898B2 (en) Buffer architecture formed on a semiconductor wafer
TWI663635B (zh) 使用離子植入之使高電阻率氮化物緩衝層的半導體材料生長
JP4757370B2 (ja) エピタキシャル基板の製造方法
WO2020009020A1 (fr) Transistor à effet de champ à effet tunnel
JP6531243B2 (ja) トンネル電界効果トランジスタおよび電界効果トランジスタの製造方法
JP5875296B2 (ja) 半導体基板および絶縁ゲート型電界効果トランジスタ
CN110875182B (zh) 一种增大自旋轨道耦合的方法和自旋晶体管
JP2015008244A (ja) ヘテロ接合電界効果型トランジスタおよびその製造方法
KR102781870B1 (ko) 다중 스트레인 구조를 가지는 AlGaN/GaN 이종 접합 구조의 고전자 이동도 트랜지스터 소자
JP7140287B2 (ja) トンネル電界効果トランジスタおよびその製造方法
JP6826003B2 (ja) トンネル電界効果トランジスタ
CN108565285B (zh) 一种GaAs基高电子迁移率晶体管材料及其制备方法
JP3271619B2 (ja) 電界効果トランジスタ
CN120050969A (zh) 锑化物hemt结构、外延结构及其制备方法
WO2025186864A1 (fr) Dispositif à semi-conducteur
JP2012069767A (ja) Ｉｉｉ−ｖ族化合物半導体エピタキシャルウェハ及びその製造方法
JP2012054404A (ja) Ｉｉｉ−ｖ族化合物半導体エピタキシャルウェハ及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19829749

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19829749

Country of ref document: EP

Kind code of ref document: A1