WO2024251436A1 - Iii-v heterojunction bipolar transistor and method for producing same - Google Patents

Abstract

The invention relates to a heterojunction bipolar transistor (HBT) and to a method for producing same, the transistor comprising, on a silicon substrate (1): • a collector layer (3) made of a first III-V material; • a collector layer (4) based on a second III-V material; and • a base layer (5) based on the second III-V material; • an emitter layer (6) based on the first III-V material, wherein the base contact (50) has a central portion (50c) and a peripheral portion (50p) around the central portion (50c) such that the thickness of the peripheral portion (50p) is less than that of the central portion (50c), which thickness decreases as the peripheral portions moves further away from the central portion (50c) so as to reduce stray capacitance between the base contact (50) and the emitter contact (60). The transistor is designed for use in a CMOS process.

Description

III-V HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to microelectronic devices. It finds a particularly advantageous application in the production of HBT heterojunction bipolar transistors, for radiofrequency (RF) components.

STATE OF THE ART

In the field of telecommunications and very high speed data transmission, typically for data flows exceeding 100 Gbits/s, it is necessary to have RF components operating at high working frequencies, typically at frequencies ranging from oscillation frequencies up to THz and beyond.

For such RF components, efficient power amplification with a cut-off frequency three to five times higher than the operating frequency of the component is required. Heterojunction bipolar transistors (HBTs), based on III-V heterojunction, are the most efficient for power amplification at frequencies above 250 GHz.

Such HBT transistors are currently developed on small format substrates, typically less than 100 mm in diameter, and use architectures that are difficult to integrate industrially, based for example on submicron air bridges or materials with limited compatibility. Current HBT transistor technologies do not allow for continuous "scaling", i.e. a reduction in dimensions sufficient for the increase in performance targeted by the next generations of RF components. The compatibility of these technologies with so-called "back end of line" (BEOL) interconnection processes is also low. This limits the possibilities of integrating HBT transistors into integrated circuits based on complementary metal-oxide-semiconductor CMOS transistor technology.

The paper “A. D. Carter et al., Si/lnP Heterogeneous Integration Techniques from the Wafer-Scale (Hybrid Wafer Bonding) to the Discrete Transistor (Micro-Transfer Printing), 2018 IEEE SOI- 3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 2018, pp. 1-4” discloses an LnP-based HBT transistor integration solution comprising a BCB (Benzocyclobutan) interconnection part connected by a hybrid bonding interface to a CMOS interconnection part. This architecture remains difficult to implement. The assembly between the CMOS part and the HBT part must be carried out at the end of the process, after having carried out all the interconnection levels. Such an integration architecture limits the application possibilities. HBT transistors cannot be integrated within the CMOS part, for example between different levels of CMOS interconnections. Transmission losses between the different electronic functions of the integrated circuit, typically between the power amplification provided by the HBT transistors and the antennas or passive elements of the BEOL metal levels, are not optimized. High-frequency operation therefore remains limited.

Another solution disclosed by the paper “T. E. Kazior et al., Progress and challenges in the direct monolithic integration of 111— V devices and Si CMOS on silicon substrates, 2009 IEEE International Conference on Indium Phosphide & Related Materials, Newport Beach, CA, 2009, pp. 100- 104” consists of co-integrating portions of 11 l-V components by local epitaxy within the CMOS stack, while maintaining a separation space around these portions of II l-V components. This solution limits the densification of the components of such a co-integrated circuit. Selective growth and stress management during growth further complicate the process.

Therefore, there is a need to improve the integration of III-V HBT transistors into a CMOS integrated circuit.

An object of the present invention is to meet this need, in particular by proposing a more versatile and compact HBT transistor architecture and integration system.

Another object of the present invention is to propose a method of producing such an HBT transistor, and an integration method.

Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

SUMMARY

To achieve this objective, according to one embodiment, a heterojunction bipolar transistor is provided comprising, stacked in a z direction on a silicon-based substrate:

- a first layer in a first III-V material having a first type of conductivity with a first doping level N+, - a first mesa structure on the first layer, comprising:

• a so-called collector layer, based on a second III-V material exhibiting the first type of conductivity with a second level of N doping, and

• a so-called base layer, based on a third III-V material presenting a second type of conductivity with a first doping level P+,

- a second mesa structure on the first mesa structure, comprising an emitter layer based on a fourth III-V material having the first conductivity type with a third N doping level.

The transistor further comprises a collector contact on the first layer, at the edge of the first mesa structure, a base contact on the base layer, at the edge of the second mesa structure, an emitter contact on the emitter layer. Advantageously, the collector, base and emitter contacts are based on a conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors. According to one possibility, the conductive material is taken from W, Ti, TiN, Ni and its alloys NiSi, NiPt, and Cu.

The transistor further comprises an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer, the first and second mesa structures, and the collector, base and emitter contacts. Advantageously, the encapsulation layer is based on a dielectric material suitable for isolation of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors. According to one possibility, the dielectric material is taken from SiO2, SiN _x .

Thus, the HBT transistor can be easily and directly integrated into an integrated circuit based on CMOS transistors. In the context of the development of the present invention, it was found by simulation of the expected performances for the HBT transistor that the choice of materials suitable for BEOL type integration made it possible to achieve a cut-off frequency of the order of THz, which is compatible with the working frequencies targeted in the range 220 GHz to 325 GHz. Contrary to the prejudices of the prior art which recommends the use of BCB for the intermetallic dielectric and noble metals for the contacts to obtain the required performances, it has been shown in the context of the present invention that an HBT transistor architecture based on conductive and dielectric materials suitable for BEOL type integration was sufficient to obtain the required performances, with a performance level of the order of 80% to 85% of the reference performance level established for HBT transistors using BCB and noble metals.

The invention also relates to a method for producing a heterojunction bipolar transistor comprising at least the following steps:

- a supply of a stack comprising, in a z direction, a silicon-based substrate, a first layer made of a first III-V material having a first type of conductivity with a first doping level N+, - epitaxial formation on the first layer of a so-called collector layer, based on a second 11 lV material having the first type of conductivity with a second N doping level, and

- epitaxial formation on the collector layer of a so-called base layer, based on a third II l-V material having a second type of conductivity with a first doping level P+,

- epitaxial formation on the base layer of a so-called emitter layer, based on a fourth II l-V material exhibiting the first type of conductivity with a third doping level N,

- a first structuring in the form of a mesa of the collector and base layers, configured to form a first mesa structure having a dimension L1 in a direction y perpendicular to the direction z,

- a second mesa-shaped structuring of the emitter layer, configured to form a second mesa structure having a dimension L2 less than the dimension L1 in the y direction,

- formation of a collector contact on the first layer, preferably at the edge of the first mesa structure,

- formation of a base contact on the base layer, at the edge of the second mesa structure,

- forming an emitter contact on the emitter layer, said collector, base and emitter contacts being formed from an electrically conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors,

- a formation of at least one encapsulation layer covering the first layer, the first and second mesa structures, the collector, base and emitter contacts, said encapsulation layer being formed from a dielectric material suitable for isolation of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors.

- A planarization of at least one encapsulation layer.

Advantageously, at each building block of the manufacturing process of the HBT transistor based on 11 lV semiconductors, corresponding to the main manufacturing steps of the emitter, base, and collector contacts, wafer planarization steps are performed. These planarization steps can be included in a damascene-type approach. The planarization steps make it possible to adapt the manufacturing process of the HBT transistor to current manufacturing methods of advanced CMOS and BiCMOS silicon integrated circuits. This approach is clearly different from the III-V technologies on native substrate as taught by document US2021391321A1. It makes it possible to obtain the following advantages: compatibility with “Direct Hybrid Bonding” transfer techniques direct) from chip to functional wafer (for example a 55 nm BiCMOS wafer obtained at the BEOL "end of line"). These techniques require excellent flatness of the two parts to be bonded or bonded, typically a surface topology of less than 50 nm "peak to valley". This level of surface quality to be bonded and interconnected can only be achieved when each part is developed in BEOL CMOS technologies. This transfer by "Direct Hybrid Bonding" makes it possible to continue the process at the "end of line", which makes it possible to envisage other improvements and functionalizations of the device (post-process rear face, collector contact directly on this face for example). compatibility with the usual 200 mm and 300 mm tools and equipment used in the CMOS microelectronics industry. The device being encapsulated in a typically oxide-based encapsulation layer, the resolution for the formation of contacts can be greatly improved (up to approximately 20 nm in 300 mm CMOS technology for example). In contrast, standard III-V technologies using air bridges can only contact the emitter for a WE emitter contact dimension > 200 nm. For a WE emitter contact dimension < 200 nm, the contact recovery must be carried out via a polymer coating (polyimides, BCB resin, etc.). This technique also limits the achievable contact dimension to around 130 nm. However, this technique induces parasites. It also limits manufacturing to substrate formats smaller than 100 mm. compatibility with substrate sizes of 200 mm and 300 mm, instead of the dimensions limited to 100 mm for usual III-V substrates.

The invention also relates to an integration system and a method of integrating such an HBT transistor.

The system for integrating at least one heterojunction bipolar transistor according to the invention typically comprises, stacked in a z direction:

- a first silicon-based substrate,

- a layer comprising complementary CMOS metal-oxide-semiconductor transistors and first levels of metal interconnections connected to said CMOS transistors,

- a bonding layer comprising a hybrid bonding type interface, comprising electrical connections with the first levels of metal interconnections connected to the CMOS transistors,

- a layer comprising at least one heterojunction bipolar transistor, and second levels of metal interconnections interposed between the bonding layer and the layer comprising the at least one heterojunction bipolar transistor, said second levels of metal interconnections being electrically connected to the bonding layer and to the at least one heterojunction bipolar transistor.

The method of integrating at least one heterojunction bipolar transistor according to the invention typically comprises:

- a supply of a first stack comprising in a direction z: • a first silicon-based substrate,

• a layer comprising complementary CMOS metal-oxide-semiconductor transistors and first levels of metal interconnections connected to said CMOS transistors,

• a first part of a bonding layer comprising a hybrid bonding type interface, comprising electrical connections with the first levels of metal interconnections connected to the CMOS transistors,

- a supply of a second stack comprising in a direction z:

• a second silicon-based substrate,

• a layer comprising at least one heterojunction bipolar transistor according to the invention, and second levels of metal interconnections connected to said heterojunction bipolar transistor,

• a second part of a bonding layer comprising a hybrid bonding type interface, comprising electrical connections with said second levels of metal interconnections connected to the heterojunction bipolar transistor,

- a hybrid bonding of the second part of the bonding layer onto the first part of the bonding layer,

- removal of the second silicon-based substrate,

- a formation, on the layer comprising the at least one heterojunction bipolar transistor, of at least one third level of interconnections. According to one possibility, the at least one third level of interconnections comprises a so-called thick metal layer having a thickness at least twice as great as the different metal thicknesses of the first and second levels of metal interconnections located under the layer comprising the at least one heterojunction bipolar transistor. The thick metal layer typically has a thickness greater than or equal to 1 pm, for example of the order of 3 pm.

Thus, the integration of the HBT transistor(s) is done as close as possible to the BEOL metal levels. The amplification circuits based on HBT transistors can thus be interconnected with the components and passive elements of the CMOS circuits with reduced connection distances. Such an integration system has improved compactness. This makes it possible to limit transmission losses linked to excessively long HBT/CMOS interconnections. An RF system based on such an architecture can advantageously operate at higher frequencies. The energy efficiency, in particular the electrical efficiency of the system, is also improved.

The HBT transistor and the integration system of this HBT transistor advantageously make it possible to produce compact and optimized RF circuit architectures, presenting improved RF performances.

BRIEF DESCRIPTION OF THE FIGURES

The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of embodiments thereof which are illustrated by the following accompanying drawings in which:

[Fig.1] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] [Fig.11] [Fig.12] [Fig.13] [Fig.14] [Fig.15] [Fig.16] [Fig.17] [Fig.18] [Fig.19] [Fig.20] [Fig.21] [Fig.22] [Fig.23] [Fig.24] [Fig.25] [Fig.26] [Fig.27] [Fig.28] [Fig.29] [Fig.30] [Fig.31] [Fig.32] [Fig.33] [Fig.34] Figures 1 to 34 schematically illustrate steps of a method for producing an HBT transistor according to an embodiment of the present invention.

[Fig.35] [Fig.36] Figures 35 and 36 schematically illustrate steps of a method of producing an HBT transistor according to another embodiment of the present invention.

[Fig.37] [Fig.38] [Fig.39] Figures 37 to 39 schematically illustrate an integration method and a system for integrating an HBT transistor into a CMOS integrated circuit according to another embodiment of the present invention.

[Fig.40] Figure 40 shows an embodiment, in particular with a particular example of contact formation.

The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers and portions, and the dimensions of the patterns and structures are not representative of reality.

DETAILED DESCRIPTION

Before beginning a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

According to one example, the heterojunction bipolar transistor comprises, stacked in a z direction on a silicon-based substrate:

- a first layer in a first III-V material having a first type of conductivity with a first doping level N+,

- a first mesa structure on the first layer, comprising:

• a so-called collector layer, based on a second III-V material exhibiting the first type of conductivity with a second level of N doping, and

• a so-called base layer, based on a third III-V material presenting a second type of conductivity with a first doping level P+,

- a second mesa structure on the first mesa structure, comprising an emitter layer based on a fourth III-V material having the first conductivity type with a third N doping level.

- a collector contact on the first layer, at the edge of the first mesa structure, a base contact on the base layer, at the edge of the second mesa structure, an emitter contact on the emitter layer, the collector, base and and emitter being based on a conductive material, typically based on a conductive material taken from W, Ti, TiN, Cu, Ni and its alloys NiPt, NiSi,

- an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer, the first and second mesa structures, and the collector, base and emitter contacts, the encapsulation layer being based on a dielectric material, typically based on a dielectric material taken from SiO2, SiN, AI203, SiCO, HfO2.

According to one example, the dielectric material is taken from SiO2, SiN, AI203, SiCO, HfO2. These materials are advantageously perfectly compatible with BEOL processes in CMOS technology.

According to one example, the conductive material is taken from W, Ti, TiN, Cu, Nb, Ni and its alloys NiPt, NiSi. These materials are advantageously perfectly compatible with BEOL processes in CMOS technology.

In one example, the first and fourth III-V materials are InP-based, and the second and third III-V materials are InGaAs-based.

In another example, the second III-V material is based on InP, and the third III-V material is based on GaAsSb, and the fourth III-V material is based on InGaP and/or InP.

In one example, the first layer of a first III-V material is directly on the silicon-based substrate. In another example, an interlayer, typically a bonding layer of a dielectric or metallic material, is intercalated between the first layer of a first III-V material and the silicon-based substrate.

In one example, the base contact has a central portion and a peripheral portion around the central portion such that the peripheral portion has a thickness less than that of the central portion. The thickness of the peripheral portion of the base contact decreases away from the central portion. This typically allows a parasitic capacitance between the base contact and the emitter contact to be reduced.

In one example, the collector contact has a central portion and a peripheral portion around the central portion such that the peripheral portion has a thickness less than that of the central portion. The thickness of the peripheral portion of the collector contact decreases away from the central portion. This typically allows for reducing a parasitic capacitance between the collector contact and the base contact and/or the emitter contact.

According to one example, the method of producing a heterojunction bipolar transistor comprises at least the following steps:

- a supply of a stack comprising in a z direction a silicon-based substrate, a dielectric layer, a first layer in a first III-V material having a first type of conductivity with a first doping level N+,

- epitaxial formation on the first layer of a so-called collector layer, based on a second III-V material having the first type of conductivity with a second doping level N, and

- epitaxial formation on the collector layer of a so-called base layer, based on a third III-V material having a second type of conductivity with a first doping level P+,

- epitaxial formation on the base layer of a so-called emitter layer, based on a fourth III-V material exhibiting the first type of conductivity with a third level of N doping,

- a first structuring in the form of a mesa of the collector and base layers, configured to form a first mesa structure having a dimension L1 in a direction y perpendicular to the direction z,

- a second mesa-shaped structuring of the emitter layer, configured to form a second mesa structure having a dimension L2 less than the dimension L1 in the y direction,

- formation of a collector contact on the first layer, preferably at the edge of the first mesa structure,

- formation of a base contact on the base layer, at the edge of the second mesa structure,

- a formation of an emitter contact on the emitter layer, said collector, base and emitter contacts being formed from an electrically conductive material, typically from an electrically conductive material taken from W, Ti, TiN, Cu,

- a formation of at least one encapsulation layer covering the first layer, the first and second mesa structures, the collector, base and emitter contacts, said encapsulation layer being formed from a dielectric material, typically from a dielectric material taken from SiO2, SiN.

In one example, the formation of the first and second mesa structures is done respectively by a first etching along z of the collector and base layers, and by a second etching along z of the emitter layer. Such a production process is generally called "top-down". This allows better control of the crystalline quality of the different layers and the dimensions of the different structures.

In one example, the first and second etches each comprise a wet isotropic etching step, such that the first and second mesa structures each have inclined flanks, overhanging respectively the first layer and the base layer. This makes it possible to reduce parasitic capacitances (in particular under the collector). This makes it possible to produce self-aligned contacts.

In another example, the first and second etchings each comprise a mixed dry and wet etching step. According to one example, the following steps are performed in the following chronological order: forming the emitter contact, then forming the second mesa structure, then forming the base contact, then forming the first mesa structure, then forming the collector contact. According to one example, the following steps are performed in the following chronological order: forming the second mesa structure, then forming the base contact, then forming the emitter contact, then forming the first mesa structure, then forming the collector contact. Forming the base contact before forming the emitter contact makes it possible to obtain a low base contact thickness in a simpler manner, with a limited number of steps, typically by chemical mechanical polishing (CMP) without etching the base contact. The base contact can therefore have an upper face substantially in the same plane as a lower face of the emitter contact. This also makes it possible to limit the presence of metal during the etching of the semiconductor layers that constitute the emitter. This avoids metal contamination of the substrate or wafer.

In one example, forming the collector contact includes a first tungsten nitrogen plasma-assisted deposition to form a peripheral portion of the collector contact. Forming the collector contact further includes thinning the peripheral portion of the collector contact by preferentially etching the peripheral portion of the collector contact relative to a central portion of the collector contact. This allows the peripheral portion of the collector contact to be moved away from the base contact. Stray capacitance between the collector contact and the base contact is reduced. This also allows the peripheral portion of the collector contact to be moved away from the emitter contact. Stray capacitance between the collector contact and the emitter contact is reduced.

In one example, forming the base contact includes a first nitrogen plasma-assisted deposition of tungsten to form a peripheral portion of the base contact. Forming the base contact further includes thinning the peripheral portion of the base contact by preferentially etching the peripheral portion of the base contact relative to a central portion of the base contact. This allows the peripheral portion of the base contact to be moved away from the emitter contact. Stray capacitance between the base contact and the emitter contact is reduced.

According to one example, the integration system further comprises, on the layer comprising the at least one heterojunction bipolar transistor, at least one third level of interconnections. The layer comprising the at least one HBT transistor is thus located between the first levels of CMOS interconnections and the at least one third level of interconnections. The third level of interconnections is typically a level of CMOS interconnections.

According to an example, the third level of interconnections comprises a layer of so-called thick metal having a thickness at least twice as great as the different thicknesses of metal of the first and second levels of metal interconnections located under the layer comprising the at least one heterojunction bipolar transistor. Such a layer of thick metal comprises by example patterns of passive components, such as transmission lines, antennas, etc. According to one example, the thick metal layer is connected to the first layer of a first III-V material of the heterojunction bipolar transistor by a heat-sinking electrical connection, said heat-sinking electrical connection acting as a collector contact for the heterojunction bipolar transistor. Such an electrical connection on the back side of the HBT transistor, for the collector, makes it possible to better manage heating and heat dissipation of the HBT transistor. The significant thickness of the thick metal layer typically makes it possible to form a radiator for the collector of the HBT transistor.

According to one example, the first layer made of a first III-V material of the layer comprising the at least one heterojunction bipolar transistor is continuous and completely covers, in projection along the z direction, the first silicon-based substrate. The first layer made of a first III-V material and the first silicon-based substrate are typically of the same dimensions in the plane normal to the z direction. This typically corresponds to the use of InPoSi substrates (acronym for “InP on Silicon”) which can advantageously reach large dimensions, for example a diameter of 200 mm or even 300 mm. The possibility of designing large-sized HBT integration systems on CMOS improves the industrial implementation of this technology (less material loss and reduced cost).

In one example, the first levels of metal interconnects connected to CMOS transistors comprise between three and five layers of metal.

Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features of one aspect of the invention, for example the HBT transistor or the integration system, may be adapted mutatis mutandis to another aspect of the invention, for example the production or integration methods.

It is specified that, in the context of the present invention, the terms “on”, “surmounts”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

A layer may further be composed of several sub-layers of the same material or of different materials. The collector layer typically comprises different N-type layers, having different dopings and/or chemical compositions. The collector layer comprises for example several InP layers with decreasing doping levels (N+, N-, along the z direction) in contact with an InGaAs layer with an N- doping level. The emitter layer typically comprises different N-type layers, having different dopings and/or chemical compositions. The emitter layer comprises for example several InP layers with increasing doping levels (N-, N+, along the z direction), and optionally a heavily N+-doped InGaAs layer in contact with the emitter contact.

The base layer typically comprises a heavily P++-doped P-type InGaAs layer, for example intercalated between the N- InGaAs layer of the collector layer and the N- InP layer of the emitter layer.

A substrate, a stack, a layer, “based” on a material A, means a substrate, a stack, a layer comprising this material A only or this material A and possibly other materials, for example alloying elements and/or doping elements. Thus, an InP-based layer means, for example, an InP layer, N-doped InP, N+ doped InP, etc. An InGaAs-based layer may comprise an N- InGaAs sublayer and one or more InP sublayers.

The doping ranges associated with the different types of doping indicated in this application are as follows:

- P++ or N++ doping: greater than 5 x 10 ¹⁹ cm ^-3

- P+ or N+ doping: 1 x 10 ¹⁸ cm ^-3 to 5 x 10 ¹⁹ cm ^-3

- P or N doping: 1 x 10 ¹⁷ cm ^-3 to 1 x 10 ¹⁸ cm ^-3

- intrinsic doping: 1 x 10 ¹⁵ cm ^-3 to 1 x 10 ¹⁷ cm ^-3

A material “suitable for” a metallurgy or insulation of the interconnection levels of a CMOS integrated circuit is understood to mean a material used or usable for CMOS integration and in particular in BEOL processes. According to an example, “suitable for” means “adapted to” or “appropriate for”, or even “compatible with”, or “capable of”, or even “intended for”. A dielectric material suitable for insulation of the interconnection levels of a CMOS integrated circuit may be based on, but not limited to: SiO2, SiN, SiON, SiOC, SiOCH, SiCN AI2O3, HfO2. An electrically conductive material suitable for metallurgy of the interconnection levels of a CMOS integrated circuit may be based on, but not limited to: W, Ti, TiN, Cu, Nb, Al, Mo, Ni, NiSi, NiPt, Ni2P, Co...

The term "dielectric" refers to a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator, typically for intermetallic layers of BEOL levels. In the present invention, a dielectric material preferably has a dielectric constant of less than 7.

The present invention allows in particular the manufacture of at least one HBT II l-V transistor or a plurality of HBT lll-V transistors on an Si substrate. This substrate can be massive or "bulk" according to the English terminology, or of the semiconductor on insulator type. The Si substrate can for example be part of an InPoSi stack (acronym for "InP on Silicon").

“Selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or of a layer B, and having an etching rate of material A greater than the etching rate of material B. Selectivity is the ratio of the etching rate of material A to the etching rate of material B. It is denoted SAB. A selectivity SA of 10:1 means that the etching rate of material A is 10 times greater than the etching rate of material B.

A particular application of the invention relates to RF systems, in particular RF amplification circuits. The invention can also be implemented more broadly for different microelectronic devices or components, for example in the context of analog circuits or mixed signal circuits (digital/analog).

Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

Furthermore, the term “step” refers to the performance of a part of the process, and can designate a set of sub-steps.

Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When only one reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

In the present patent application, the thickness of a layer is taken along a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms “on”, “overtops”, “under”, “underlying” refer to positions taken along the z direction.

The terms "vertical", "vertically" refer to a direction along z. The terms "horizontal", "horizontally", "lateral" refer to a direction in the xy plane. Unless explicitly stated, thickness, height and depth are measured along z.

An element located “perpendicular to” or “in line with” another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

The terms “substantially”, “approximately”, “of the order of” mean to within 10%, and preferably to within 5%. Furthermore, the terms “between ... and ..." and equivalents mean that the limits are included, unless otherwise stated.

Figures 1 to 32 illustrate a first embodiment of the method of producing the transistor. HBT. In this embodiment, the HBT transistor is of the NPN (emitter-base-collector) type, with an InGaAs/InP heterojunction. Other configurations are perfectly conceivable. In particular, other III-V materials can be used for the junctions or heterojunctions, in a known manner. The following alloys can in particular be used for the production of the HBT transistor: InGaAs, InP, InGaP, GaAsSb. The person skilled in the art will be able to adapt the embodiment described below according to these needs.

As illustrated in Figure 1, a silicon-based substrate 1 (Si substrate) is first provided. According to one possibility, a stack of layers 3, 4, 5, 6 based on III-V materials, formed separately, can be transferred onto the silicon-based substrate 1, by SiO2-SiO2 bonding for example. The substrate

1 based on silicon thus typically comprises a first bonding layer 21 based on SiO2 and the stack thus typically comprises a second bonding layer 22 based on SiO2. In this case, the silicon-based substrate 1 and the stack based on III-V materials can be assembled by molecular bonding between the first and second bonding layers 21, 22. The first bonding layer 21 can be based on thermal SiO2. It typically has a thickness of the order of 200 nm. The second bonding layer 22 can be formed by chemical vapor deposition (CVD) on the stack of layers based on III-V materials. It typically has a thickness of the order of 100 nm. In this case of transfer of the stack of layers based on III-V materials onto the Si substrate, said stack has a lateral dimension, in the xy plane, for example a diameter, typically less than the lateral dimension, for example the diameter, of the Si substrate, as illustrated in FIG. 1.

According to another possibility, the silicon-based substrate may typically be of the InPoSi type and comprise a “massive” silicon part 1, called “bulk”, a buried oxide layer 2 called BOX (acronym for “Burned Oxide”), topped by a superficial InP layer 31. Such an InPoSi substrate may be obtained by a process called “smart cut” widely known to those skilled in the art. In this case, the stack of layers 3, 4, 5, 6 based on III-V materials may be formed directly by epitaxy on the InPoSi substrate. Advantageously, the stack of layers based on III-V materials has in this case a lateral dimension, in the xy plane, for example a diameter, substantially equal to the lateral dimension, for example the diameter, of the InPoSi substrate.

Regardless of how the stack of layers based on III-V materials is formed, either separately and then transferred by SiO2-SiO2 bonding on the Si substrate, or directly by epitaxy on the InPoSi substrate, the stack preferably comprises, along z and starting from the oxide layer

2:

- an InP-based layer 31, which may be, depending on the case, an InP-based bonding layer with the second bonding layer 22 or a superficial InP layer of an InPoSi substrate. This layer 31 typically has a thickness of the order of 50 nm.

- a layer 32 based on InGaAs, which serves as a stop layer for etching. In a known manner, an etching stop can be carried out by detection of the end of the attack, by detecting the change in the nature of the etched materials during etching and/or by taking advantage of the etching selectivity of the materials of the layer to be etched and of the stop layer. This layer 32 typically has a thickness of the order of 20 nm.

- a layer 33 based on N+ doped InP, which ensures good electrical conductivity under the collector of the HBT transistor. This layer 33 typically has a thickness of the order of 350 nm.

- a layer 34 based on N+ doped InGaAs, which ensures good electrical conductivity under the collector of the HBT transistor. This layer 34 typically acts as an interface with the collector contact of the HBT transistor. This layer 34 typically has a thickness of the order of 20 nm. The layers 33, 34 can form a layer 3 called a sub-collector.

- a layer 41 based on N+ doped InP, intended to form part of the collector. This layer 41 typically has a thickness of the order of 50 nm.

- a layer 42 based on N-doped InP, intended to form part of the collector. This layer 42 typically has a thickness of the order of 85 nm.

- a second layer 43 based on N-doped InP, intended to form part of the collector. This layer 43 typically has a thickness of the order of 25 nm.

- a layer 44 based on N-doped InGaAs, intended to form a part of the collector. This layer 44 typically has a thickness less than or equal to 20 nm, for example of the order of 10 nm or 5 nm. The layers 41, 42, 43, 44 typically form the collector layer 4. These different layers 41, 42, 43, 44 are preferably configured so that the N-type doping gradually decreases between the layer 41 and the layer 44. This makes it possible to better accommodate the variations in conductivity and the mechanical constraints within the stack. These layers 41, 42, 43, 44 are typically sized in thickness and doping so as to manage the electric field and the flow of charges in the collector.

- a layer 5 based on P++-doped InGaAs, intended to form a first P/N junction with layer 44. This layer 5 typically forms the base of the HBT transistor. It is typically directly connected to the base contact of the HBT transistor. This layer 5 typically has a thickness of the order of 28 nm. Other materials are also conceivable for this base layer 5, for example GaAsSb.

- a layer 61 based on N-doped InP, intended to form a second P/N junction with layer 5, of the heterojunction type. This layer 61 typically forms part of the emitter. This layer 61 typically has a thickness of the order of 20 nm.

- a layer 62 based on N+ doped InP, intended to form part of the emitter. This layer 62 typically has a thickness of the order of 30 nm.

- a layer 63 based on N+ doped InGaAs, intended to form part of the emitter. This layer 63 typically acts as an interface with the emitter contact of the HBT transistor. This layer 63 typically has a thickness of the order of 20 nm. The layers 61, 62, 63 typically form the emitter layer 6.

- a 64 layer based on InP, which serves as a stop layer for etching. This 64 layer typically has a thickness of the order of 20 nm.

After formation of the stack of layers based on 11 l-V materials, this stack is structured by different lithography and etching steps, and contacts are formed to produce the HBT transistor.

As illustrated in Figure 2, a planarization step can first be performed. This step typically comprises a deposition of a SiN-based layer 71, intended on the one hand to fill the spaces bordering the stack of layers based on 11 l-V materials, and intended on the other hand to form a mask on the stack of layers based on 11 l-V materials. After deposition, chemical mechanical polishing (CMP) typically makes it possible to planarize the layer 71. The layer 71 surmounting the stack typically has a thickness of the order of 150 nm after planarization.

A resin-based masking layer 81 is then formed on the layer 71, then structured by lithography to form one or more openings 101 having a dimension L2 along x. The layer 71 is then etched through the opening 101, typically by plasma-based dry etching or by reactive ion etching (RIE). The layer 64 of the stack is then etched through the opening 101, typically by selective wet etching with respect to the underlying layer 63. An upper face 630 of the layer 63 is thus exposed after the successive etchings through the opening 101.

As illustrated in FIG. 3, the masking layer 81 is then removed in a known manner by a so-called “stripping” step, typically by O2-based plasma. A deposition of a metal layer 11 is then carried out, so as to fill the opening 101 of the layer 71. This metal layer 11 may comprise several sub-layers, for example bonding layers based on Ti and TiN, with thicknesses of 10 nm respectively, and a main layer based on tungsten W, of sufficient thickness to fill the opening of the layer 71. This main layer based on tungsten W has for example a thickness of the order of 225 nm.

As illustrated in FIG. 4, a chemical-mechanical polishing is carried out so as to remove the excess metal deposited on the layer 71. The CMP polishing is stopped on the layer 71, in order to keep the portion of metal layer in the opening of the layer 71. The emitter contact 60 is thus formed. Here, it is in contact with the layer 63 based on N+ doped InGaAs.

As illustrated in Figure 5, a portion of layer 71 is then etched away, so as to expose an upper face 640 of layer 64.

As illustrated in FIG. 6, the layers 64, 63, 62, 61 of the stack are then etched around the emitter contact 60, so as to expose an upper face 500 of the layer 5. The layers 64, 63, 62 and partly the InP-based layer 61 are typically etched by dry etching, with a stop in the layer 61. A finishing etching by wet etching then makes it possible to remove the remaining part of the InP-based layer 61, selectively to the InGaAs P++-based layer 5. A 6M mesa structure of dimension L2 along x is thus obtained under the emitter contact 60. This 6M mesa structure has sides 601 which can be slightly inclined with respect to the vertical. This is typically due to the isotropic nature of the etchings, in particular wet etching. This also comes from the crystallography of InP and InGaAs insofar as certain crystal planes are etched faster than others.

As illustrated in FIG. 7, a SiN-based layer 72 is then formed by conformal deposition at 300°C on the exposed face 500, and on the flanks 601 and the emitter contact 60. This layer 72 typically has a thickness of the order of 30 nm. A SiO2-based layer 73 is then formed on the layer 72, for example by deposition at 400°C. This layer 73 typically has a thickness of the order of 400 nm. A planarization step by CMP polishing is then carried out on the layer 73.

As illustrated in FIG. 8, CMP polishing of layer 73 is typically stopped on SiN-based layer 72 atop emitter contact 60. A resin-based masking layer 82 is then formed on layer 73 and on the portion of layer 72 atop emitter contact 60, then lithographically structured to form apertures 102, for example by e-beam electron lithography. Apertures 102 are formed on either side of emitter contact 60. An upper face 730 of layer 73 is thus exposed through apertures 102.

As illustrated in FIG. 9, layers 73 and 72 are then etched through openings 102, typically by dry etching. The etching stops on layer 5 based on InGaAs P++. An upper face 500 of layer 5 is thus exposed after etching through openings 102.

As illustrated in FIG. 10, the masking layer 82 is removed by “stripping”. A deposit of a metal layer 12 is then carried out, so as to fill the openings 102 of the layer 73. This metal layer 12 can comprise several sub-layers, for example bonding layers based on Ti and TiN, with thicknesses of 10 nm respectively, and a main layer based on tungsten W, with a thickness sufficient to fill the openings of the layer 73. This main layer based on tungsten W has for example a thickness of the order of 375 nm.

As illustrated in Figure 11, a chemical mechanical polishing is first performed so as to remove the excess metal deposited on the layer 73. The CMP polishing is stopped on the layer 73, in order to keep the portions 50' of the metal layer 12 in the openings of the layer 73.

As illustrated in FIG. 12, these metal layer portions are then thinned to form the base contacts 50, typically so that the upper faces of the base contacts 50 are located under a plane passing through the lower face of the emitter contact 60. This makes it possible to minimize the parasitic capacitances between the emitter contact 60 and the base contacts 50. Such thinning typically makes it possible to reduce these parasitic capacitances by 55%, in comparison of unthinned 50' base contacts having a height substantially equal to the thickness of the layer 73, as illustrated in FIG. 11.

The W metal layer portions can be thinned by wet etching based on Potassium Triiodide KII2. The Ti/TiN metal layer portions, at the flanks of the base contacts 50, can be removed by dry etching. Base contacts 50 directly in contact with the layer 5 based on P++ doped InGaAs are thus formed.

According to a possibility illustrated in FIG. 13, the thinning is carried out differentially, in order to obtain peripheral portions 50p of the contact 50 thinner than the central portion 50c of the contact 50. Such differential thinning can occur when the deposition of the main layer based on tungsten W is carried out by plasma-assisted CVD of nitrogen species N+. The peripheral portions 50p of the contact 50 are then etched preferentially at the central portion 50c of the contact 50. The peripheral portions 50p typically have a decreasing thickness profile from the central portion 50c. In this case, the parasitic capacitances between the emitter contact 60 and the base contacts 50 are further reduced. Such differential thinning typically makes it possible to reduce these parasitic capacitances by 70%, in comparison with non-thinned 50' base contacts having a height substantially equal to the thickness of the layer 73, as illustrated in FIG. 11.

As illustrated in FIG. 14, a SiN-based layer 74 is then formed by conformal deposition at 400°C on the layer 73, and on the base contacts 50 and the emitter contact 60. This layer 74 typically has a thickness of the order of 60 nm. A masking layer 83 based on resin is then formed and structured, for example by e-beam electron lithography, above the base contacts 50 and the emitter contact 60, while retaining portions of layer 74 exposed around the base contacts 50.

As illustrated in Figure 15, layers 74, 73 and 72 are then etched around masking layer 83, typically by dry etching. The etching stop is made on layer 5 based on InGaAs P++. An upper face 500 of layer 5 is thus exposed after etching. The protruding structure of layer 5, comprising base contacts 50, mesa structure 6M, emitter contact 60 and masking layer 83, typically has a dimension L1 along x. Masking layer 83 is then removed by “stripping” (Figure 16).

As illustrated in Figure 17, layers 5, 44, 43, 42 and 41 of the stack are then etched around the base contacts 50. Layers 5, 44, 43, 42 and partly the InP-based layer 41 are typically etched by dry etching, with a stop in layer 41. The partial dry etching of the InP-based layers 43, 42 and 41 can be configured to stop at an etching depth of the order of 140 nm from the interface between layer 43 and layer 44, so as to maintain a residual thickness of layer 41 at the end of dry etching.

As illustrated in FIG. 18, a wet etching finish etch then removes the remaining portion of the InP-based layer 41, preferably selectively to the InGaAs N+-based layer 34, so as to expose an upper face 300 of the layer 34. A mesa structure 45M is thus obtained under the base contacts 50. This 45M mesa structure of dimension L1 along x typically has 451 sides which can be slightly inclined with respect to the vertical. This is typically due to the isotropic nature of the etchings, in particular wet etching.

As illustrated in FIG. 19, a SiN-based layer 74 is then formed by conformal deposition at 300°C on the exposed face 300, and on the flanks 451, the base contacts 50 and the emitter contact 60. This layer 74 typically has a thickness of the order of 60 nm. A SiO2-based layer 75 is then formed on the layer 74, for example by deposition at 400°C. This layer 75 typically has a thickness of the order of 750 nm. A planarization step by CMP polishing is then carried out on the layer 75, stopping on the protruding parts of the SiN-based layer 74.

As illustrated in FIG. 20, a resin-based masking layer 84 is then formed on layer 75 and on the protruding portions of layer 74, then structured by lithography to form openings 103. Openings 103 are formed on either side of base contacts 50. As illustrated in FIG. 21, layers 75 and 74 are then etched through openings 103, typically by dry etching. The etching stops on layer 34 based on InGaAs N+. An upper face 300 of layer 34 is thus exposed after etching through openings 103.

As illustrated in FIG. 22, the masking layer 84 is removed by “stripping”. A deposit of a metal layer 13 is then carried out, so as to fill the openings 103 of the layer 75. This metal layer 13 can comprise several sub-layers, for example bonding layers based on Ti and TiN, with thicknesses of 10 nm respectively, and a main layer based on tungsten W, with a thickness sufficient to fill the openings of the layer 75. This main layer based on tungsten W has for example a thickness of the order of 750 nm.

As illustrated in FIG. 23, chemical mechanical polishing is first performed to remove excess metal deposited on layer 75. The portions of metal layer 13 in the openings of layer 75 are then thinned to form collector contacts 30, typically such that the upper faces of collector contacts 30 are located below a plane passing through the lower faces of base contacts 50. This minimizes parasitic capacitances between collector contacts 30 and base contacts 50. This also minimizes parasitic capacitances between collector contacts 30 and emitter contact 60.

The W-based metal layer portions 13 can be thinned by wet etching based on Potassium Triiodide KII2, for example to an etching depth of approximately 270 nm. The Ti/TiN metal layer portions, at the flanks of the collector contacts 30, can be removed by dry etching. Collector contacts 30 directly in contact with the N+-doped InGaAs-based layer 34 are thus formed. According to one possibility, the collector contacts 30 can be thinned by differential thinning as before. The collector contacts 30 therefore have a peripheral portion relatively thinner than their central portion.

As illustrated in FIG. 24, a SiN-based layer 76 is then formed by conformal deposition at 400°C on the layer 75, and on the collector contacts 30. This layer 76 typically has a thickness of the order of 30 nm. A SiO2-based layer 77 is then formed on the layer 76, for example by deposition at 400°C. This layer 77 typically has a thickness of the order of 400 nm. A planarization step by CMP polishing is then carried out on the layer 77. An HBT transistor based on 11 l-V materials, on a Si substrate, and encapsulated by SiO2/SiN dielectric materials, is thus obtained. The following steps aim to form the contact vias on the various emitter, base and collector contacts of the HBT transistor.

As illustrated in FIG. 25, a resin-based masking layer 85 is formed over layer 77 and patterned, typically by e-beam electron beam lithography. An opening 104 is formed above emitter contact 60, first in layer 85, then in the dielectric layer stack up to emitter contact 60.

As illustrated in Figure 26, after stripping masking layer 85, a new resin-based masking layer 86 is formed over layer 77 and patterned, typically by e-beam electron beam lithography. An opening 105 is made above base contact 50, first in layer 86, then in the dielectric layer stack up to base contact 50. Opening 104 above emitter contact 60 is typically filled by layer 86 at this point.

As illustrated in Figure 27, after stripping the masking layer 86, a new resin-based masking layer 87 is formed on the layer 77 and patterned, typically by e-beam electron lithography. An opening 106 is made above the collector contact 30, first in the layer 87, then in the dielectric layer stack up to the collector contact 30. The openings 104, 105 respectively above the emitter contact 60 and the base contact 50 are typically filled by the layer 87 at this stage.

As illustrated in FIG. 28, after stripping the masking layer 87, interconnections 55, 65, 35, also called contact vias, are formed in the openings 105, 104, 106, so as to connect the base, emitter, and collector contacts respectively. A metal layer is first deposited, so as to fill the openings 105, 104, 106. This metal layer may comprise, as previously, several sub-layers, for example Ti and TiN-based bonding layers, with thicknesses of 10 nm respectively, and a main layer based on tungsten W, with a thickness sufficient to fill the openings 105, 104, 106. This main layer based on tungsten W has, for example, a thickness of the order of 700 nm. A mechanical-chemical polishing is then carried out so as to remove the excess metal deposited on the layer 77. The interconnections 55, 65, 35 are thus individualized.

The following steps are to isolate the HBT transistor from other components (not shown). As illustrated in FIG. 29, a SiN-based layer 78 may be formed by deposition at 400°C on layer 77, and on interconnections 55, 65, 35. This layer 78 typically has a thickness of the order of 150 nm. A masking layer 88 based on resin is formed on layer 78 and then structured by lithography. Openings in the form of trenches 107 are made around the HBT transistor, typically around collector contacts 30, first in layer 88, then in the stack of dielectric layers up to layer 34 based on InGaAs N+.

As illustrated in Figure 30, after stripping the masking layer 88, the etching of the trenches 107 is extended in the stack of layers based on III-V materials, up to layer 2 based on SiO2.

As illustrated in Figure 31, these trenches 107 are then filled with a dielectric material 79, typically by deposition of SiO2 TEOS at 300°C over a thickness of 2 μm. A mechanical-chemical polishing of the SiO2 is then carried out with a stop on the SiN-based layer 78.

The following steps aim to form the first metal level M1 comprising the metal tracks connecting the different interconnections 55, 65, 35. The interconnections 55, 65, 35 form an interconnection level 11.

As illustrated in FIG. 32, a resin-based masking layer 89 is formed over layer 78 and patterned, typically by e-beam electron lithography. Openings 108 are formed over interconnects 55, 65, 35, first in layer 89, then in layer 78 up to interconnects 55, 65, 35.

As illustrated in FIG. 33, after “stripping” the masking layer 89, a deposit of a metal layer 14 is carried out, so as to connect the interconnections 55, 65, 35. This metal layer 14 can comprise several sub-layers, for example bonding layers based on Ti and TiN, with thicknesses of 10 nm respectively, a main layer based on AlCu alloy, with a thickness of 440 nm for example, and surface layers based on Ti and TiN, with thicknesses of 10 nm respectively.

As illustrated in Figure 34, this metal layer 14 is then structured by lithography and etching so as to form a track 56 connected to via 55, a track 66 connected to via 65, and a track 36 connected to via 35.

An HBT transistor comprising 6M, 45M mesa structures formed in a stack of III-V materials on a Si substrate, integrated in SiO2, SiN dielectric materials and connected by W-based interconnections 55, 65, 35 is thus obtained. Such an HBT transistor and its first level of interconnections 11, M1 is advantageously integrable in a system comprising CMOS transistors and CMOS interconnections.

Figures 35, 36 illustrate a variation of the HBT transistor manufacturing process, in which the base contacts are formed before the emitter contact.

As illustrated in Figure 35, the 6M mesa structure is formed by lithography and etching from the stack of III-V material-based layers. Dielectric layers 72, 73 are then formed on this 6M mesa structure, then planarized. The dielectric layers 72, 73 are then opened at the edge of the 6M mesa structure, so as to expose the upper face 500 of the layer 5.

As illustrated in Figure 36, the openings are then filled with a metal layer. CMP polishing then removes excess metal layer portions to form the base contacts 50. The emitter contact and collector contacts can then be formed as before. In this case, the upper face of the base contacts 50 lies in a plane substantially corresponding to the top of the 6M mesa structure. It is therefore not necessary to thin the base contacts 50 when they are formed before the emitter contact. This saves a process step.

Figures 37, 38, 39, 40 illustrate possibilities of integrating the HBT transistor into a system comprising CMOS transistors and CMOS interconnects.

As illustrated in FIG. 37, an integrated circuit comprising transistors HBT1, HBT2, HBT3 based on III-V materials on a silicon-based substrate 1b, and integrated via interconnection levels 11, I2 and metal levels M1, M2 in a dielectric matrix D1 based on SiO2 and/or SiN, can advantageously be obtained. The last metal level M2 of this “HBT” integrated circuit can typically form a first hybrid bonding interface.

As illustrated in Figure 38, a “CMOS” integrated circuit comprising components based on CMOS or BiCMOS transistors, CMOS1, CMOS2, etc. on a silicon-based substrate 1b and integrated via interconnection levels 11’, I2’ and metal levels M1’, M2’ in a dielectric matrix D2 based on SiO2 and/or SiN, can be advantageously assembled to the “HBT” integrated circuit. The last metal level M2’ of the “CMOS” integrated circuit can typically form a second hybrid bonding interface.

The “HBT” and “CMOS” integrated circuits can be aligned and assembled by hybrid bonding by facing the first and second hybrid bonding interfaces. In the case of “HBT” integrated circuits with small lateral dimensions relative to the “CMOS” integrated circuit, multiple “HBT” integrated circuits can be co-assembled side-by-side on the “CMOS” integrated circuit. After assembly, the substrate 1b can typically be removed by mechanical trimming and wet etching.

As illustrated in Figure 39, 11” interconnect levels, I2” and 1” metal levels, M2” in a SiO2 and/or SiN-based dielectric matrix D3 can be advantageously formed above the HBT1, HBT2, HBT3 transistors based on III-V materials. The 11” interconnect level advantageously connects the HBT1, HBT2, HBT3 transistors, typically at the collector or sub-collector portion of the HBT1, HBT2, HBT3 transistors. Some of the 11” interconnect levels can be relatively wider and more massive to form a heat sink for the corresponding HBT3 transistor. This improves the heat dissipation and heating management of such an HBT3 transistor. The M1”, M2” metal levels can typically comprise thick metal tracks, forming passive RF components such as antennas or transmission lines.

Advantageously, the HBT level may be integrated between different interconnection levels, for example between interconnection levels 11, 11” as illustrated, or between interconnection levels 11”, I2” etc. This allows for greater versatility in integrating the HBT transistors within the CMOS stack. Several CMOS metal levels M1’, M2’, for example up to five levels, may be provided below the HBT level. Several post-processing metal levels M1”, M2”, for example up to five additional levels, may be provided above the HBT level.

As illustrated in FIG. 40, the collector contact 30 can be formed on the “rear face” of the HBT transistor during subsequent integration steps, after removal of the silicon-based substrate 1. The layer 32 is typically based on doped InGaAs here. The emitter contacts 60 and base 50, as well as the contact resumptions 55 and 65 are previously formed for example, up to the metal level M2 and allow the transfer by “Direct Hybrid Bonding” of a plate comprising different metal levels M2’ or higher,’. The metal levels M1”, M2” correspond here for example to thick metal levels implemented in CMOS or BiCMOS technologies. The formation of the collector contact 30 on the “rear face” allows better heat dissipation for the HBT transistor, and less thermal resistance between the bases 50 and the collector 30. The overall resistance of the collector 30 is reduced. The formation of the collector contact 30 on the “rear face” also offers more possibilities in terms of design of the collector contact 30. According to a possibility illustrated in FIG. 40, the collector contact 30 has a dimension L3 substantially equal to the dimension L2 of the emitter contact. The facing metal surfaces between the collector 30 and the bases 50 are reduced. This reduces the parasitic capacitances between the base 50 contacts and the collector contact 30. Thermal management and the management of parasitic capacitances are improved. The InP-based layer 33 typically has a dielectric constant of the order of 13. It is surrounded by layers 71, 72 based on a dielectric material having a dielectric constant lower than that of InP and InGaAs. For example, this material may be silicon nitride having a dielectric constant of the order of 7. The surrounding matrix, comprising the layers 75, 77 based on silicon oxide, typically has a dielectric constant of the order of 4.

The interconnection levels I2’ and metal M2’ previously formed on another plate which constitutes the host plate or “Bottom” and can be a BiCMOS circuit for example. This makes it possible to consider other improvements and functionalizations of the device during end-of-line stages. This integration on the front face and/or on the back face of the HBT transistor by “Direct Hybrid Bonding”, which requires excellent surface flatness between the different plates and chips, is made possible in particular by the planarization stages occurring during the manufacturing bricks of the HBT transistor.

In view of the above, it appears clearly that the HBT transistor and its integration system can be integrated compactly and versatile within a CMOS or BiCMOS integrated circuit.

The invention is not limited to the embodiments previously described.

Claims

1. Method for producing a heterojunction bipolar transistor (HBT) comprising at least the following steps: A supply of a stack comprising, in a z direction, a silicon-based substrate (1), a first layer (3) made of a first III-V material having a first conductivity type with a first doping level N+, a formation by epitaxy on the first layer of a layer (4) called a collector layer, based on a second III-V material having the first conductivity type with a second doping level N, and a formation by epitaxy on the collector layer (4) of a layer (5) called a base layer, based on a third III-V material having a second conductivity type with a first doping level P+, a formation by epitaxy on the base layer (5) of a layer (6) called an emitter layer, based on a fourth III-V material having the first conductivity type with a third doping level N, A first mesa-shaped structuring of the collector and base layers (4, 5), configured to form a first mesa structure (45M) having a dimension L1 in a y direction perpendicular to the z direction, A second mesa-shaped structuring of the emitter layer (6), configured to form a second mesa structure (6M) having a dimension L2 less than the dimension L1 in the y direction, A formation of a collector contact (30) on the first layer (3), preferably at the edge of the first mesa structure (45M), A formation of a base contact (50) on the base layer (5), at the edge of the second mesa structure (6M), A formation of an emitter contact (60) on the emitter layer (6), said collector, base and emitter contacts being formed from an electrically conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors, A formation of at least one encapsulation layer covering the first layer (3), the first and second mesa structures (45M, 6M), the collector, base and emitter contacts (30, 50, 60), said encapsulation layer being formed from a dielectric material suitable for isolation of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors. A planarization of at least one encapsulation layer. 2. Method according to the preceding claim in which the formations of the first and second mesa structures (45M, 6M) are carried out respectively by a first etching along z of the collector and base layers (4, 5), and by a second etching along z of the emitter layer (6). 3. Method according to the preceding claim, in which the first and second etchings each comprise a wet isotropic etching step, such that the first and second mesa structures (45M, 6M) each have inclined sides (451, 601), overhanging respectively the first layer (3) and the base layer (5). 4. A method according to any preceding claim wherein the following steps are performed in the following chronological order: forming the emitter contact (60), then forming the second mesa structure (6M), then forming the base contact (50), then forming the first mesa structure (45M), then forming the collector contact (30). 5. Method according to any one of the preceding claims in which the following steps are carried out in the following chronological order: formation of the second mesa structure (6M), then formation of the base contact (50), then formation of the emitter contact (60), then formation of the first mesa structure (45M), then formation of the collector contact (30). 6. A method according to any preceding claim wherein the formation of the collector contact (30) and/or the formation of the base contact (50) comprise a first nitrogen plasma-assisted deposition of tungsten, intended to form a peripheral portion of the collector contact and/or the base contact respectively, said formation further comprising a thinning of the peripheral portion of the contact in question by preferential etching of the peripheral portion of the contact in question with respect to a central portion of said contact. 7. Heterojunction bipolar transistor (HBT) comprising, stacked in a z direction on a silicon-based substrate (1, 1b): a first layer (3) made of a first 11 l-V material having a first conductivity type with a first doping level N+, a first mesa structure (45M) on the first layer (3), comprising: • a layer (4) called a collector, based on a second III- material having the first type of conductivity with a second level of N doping, and • a so-called base layer (5), based on a third III-V material having a second type of conductivity with a first doping level P+, a second mesa structure (6M) on the first mesa structure (45M), comprising an emitter layer (6) based on a fourth III-V material having the first type of conductivity with a third doping level N, said transistor (HBT) further comprising a collector contact (30) on the first layer (3), preferably at the edge of the first mesa structure Tl (45M), a base contact (50) on the base layer (5), at the edge of the second mesa structure (6M), an emitter contact (60) on the emitter layer (6), said collector, base and emitter contacts being based on an electrically conductive material suitable for metallurgy of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors, said transistor (HBT) further comprising an encapsulation layer based on a dielectric encapsulation material, said encapsulation layer covering the first layer (3), the first and second mesa structures (45M, 6M), and the collector, base and emitter contacts (30, 50, 60), said encapsulation layer being based on a dielectric material suitable for isolation of the metal levels of an integrated circuit based on complementary metal-oxide-semiconductor (CMOS) transistors, said transistor (HBT) being characterized in that the base contact (50) has a central portion (50c) and a peripheral portion (50p) around the central portion (50c) such that the peripheral portion (50p) has a thickness less than that of the central portion (50c) and which decreases away from the central portion (50c), so as to reduce a parasitic capacitance between the base contact (50) and the emitter contact (60). 8. Transistor according to the preceding claim in which the dielectric material is taken from SiO2, SiN, SiOC, HfO2, AI2O3 and the conductive material is taken from W, Ti, TiN, Cu Ni, NiSi, NiPt, Mo, Al. 9. Transistor according to any one of claims 7 to 8 in which the first and fourth 11 l-V materials are based on InP, and the second and third 11 l-V materials are based on InGaAs. 10. Transistor according to any one of claims 7 to 9 in which the collector contact (30) has a central portion and a peripheral portion around the central portion such that the peripheral portion has a thickness less than that of the central portion and which decreases as it moves away from the central portion, so as to reduce a parasitic capacitance between the collector contact (30) and the base contact (50) and/or the emitter contact (60). 11. System for integrating at least one heterojunction bipolar transistor (HBT) comprising, stacked in a z direction: A first substrate (1a) based on silicon, A layer (CMOS) comprising complementary metal-oxide-semiconductor CMOS transistors and first levels of metal interconnections (11', M1') connected to said CMOS transistors, A bonding layer comprising a hybrid bonding type interface (M2, M2'), comprising electrical connections (12') with the first levels of metal interconnections (11', M1') connected to the CMOS transistors, A layer (HBT) comprising at least one heterojunction bipolar transistor according to any one of claims 7 to 10, and second levels of metal interconnections (11, M1) intercalated between the bonding layer and the layer (HBT) comprising the at least one heterojunction bipolar transistor, said second levels of metal interconnections (11, M1) being electrically connected to the bonding layer and to the at least one heterojunction bipolar transistor. 12. Integration system according to the preceding claim further comprising, on the layer (HBT) comprising the at least one heterojunction bipolar transistor, at least one third level of interconnections (11”, M 1 ”) comprising a layer (M 1 ”) of so-called thick metal having a thickness at least twice the different thicknesses of metal (M 1 , M 1 ’) of the first and second levels of metal interconnections located under the layer (HBT) comprising the at least one heterojunction bipolar transistor. 13. Integration system according to the preceding claim, in which the layer (M1”) of thick metal is connected to the first layer (3) of a first III-V material of the heterojunction bipolar transistor by an electrical connection (37) for heat dissipation, said electrical connection (37) for heat dissipation acting as a collector contact for the heterojunction bipolar transistor. 14. Integration system according to any one of claims 11 to 13 in which the first layer (3) in a first III-V material of the layer comprising the at least one heterojunction bipolar transistor is continuous and completely covers, in projection in the z direction, the first silicon-based substrate (1a). 15. Integration system according to any one of claims 11 to 14 in which the first levels of metal interconnections (11’, M1’) connected to the CMOS transistors comprise between three and five layers (M1’, M2’) of metal. 16. Method for integrating at least one heterojunction bipolar transistor comprising the following steps: A supply of a first stack comprising in a direction z: • a first substrate (1a) based on silicon, • a layer (CMOS) comprising complementary CMOS metal-oxide-semiconductor transistors and first levels of metal interconnections (11’, M1’) connected to said CMOS transistors, • a first part (M2') of a bonding layer comprising a hybrid bonding type interface, comprising connections electrical (12') with the first levels of metallic interconnections (11', M1') connected to the CMOS transistors, A supply of a second stack comprising in a z direction: • a second silicon-based substrate (1b), • a layer (HBT) comprising at least one heterojunction bipolar transistor according to any one of claims 7 to 10, and second levels of metal interconnections (11, M1) connected to said heterojunction bipolar transistor, • a second part (M2) of a bonding layer comprising a hybrid bonding type interface, comprising electrical connections (I2) with said second levels of metal interconnections (11, M1) connected to the heterojunction bipolar transistor, a hybrid bonding of the second part (M2) of the bonding layer on the first part (M2') of the bonding layer, a removal of the second silicon-based substrate (1 b), a formation, on the layer (HBT) comprising the at least one heterojunction bipolar transistor, of at least one third level of interconnections (11", M1"), said at least one third level of interconnections (11", M1") preferably comprising a layer (M1") of so-called thick metal having a thickness at least twice as great as the different thicknesses of metal (M1, M1') of the first and second levels of metal interconnections located (11, M1, 11 ’, M1 ’) under the layer (HBT) comprising the at least one heterojunction bipolar transistor.