WO2024251732A1

WO2024251732A1 - FAST-SWITCHING INGAALP OR INGAALAS-BASED µLEDS FOR HIGH-SPEED DATA COMMUNICATION

Info

Publication number: WO2024251732A1
Application number: PCT/EP2024/065331
Authority: WO
Inventors: Philipp Kreuter; Martin Hetzl; Norwin Von Malm; Tansen Varghese
Original assignee: Ams Osram International GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2023-06-08
Filing date: 2024-06-04
Publication date: 2024-12-12
Anticipated expiration: 2025-12-08
Also published as: CN121312293A; DE112024002463T5; TW202515399A

Abstract

The invention concerns a µ-LED comprising a semiconductor layer stack having a first layer of a first doping type, a second layer of a second doping type, and an active region arranged between the first and the second layer. The semiconductor layer stack comprises a bottom surface and a top surface as well as mesa structured side surfaces connecting the top and bottom surface and a central region with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack. Further the semiconductor layer stack comprises a material including at least one of phosphide and arsenide and a current path from the first layer to the second layer through the active region is limited to the central region.

Description

FAST- SWITCH ING INGAALP OR INGAALAS- BASED LEDS FOR HIGH-SPEED DATA COMMUNICATION

The present application claims priority from German patent application DE 10 2023 115 113 . 4 filed on June 08 , 2023 , the disclosure of which is incorporated by way for reference in its entirety .

The present invention concerns a p-LED for use as a means for optical data communication, as well as a method for manufacturing the p-LED .

BACKGROUND

Today ' s Internet relies on large data centres . However, their high- power consumption poses problems to ensure their operation with purely sustainable energy sources . Most of the power is consumed not for computations , but for data transmission over short distances ( «10m) : CPU to GPU, server to server , rack to rack .

The use of p-LEDs for optical and data communication has several benefits . Apart from the small size , which provides an easier interconnect to fibre optics , the vertical or horizontal optoelectronic components provide an improved scalability and can be easily implemented in existing designs at large numbers . In this regard a p- LED is an optoelectronic component that comprises a diameter or more general a dimension that is smaller than 50 pm and in particular smaller than 20 pm . In some special applications , a p-LED can range in diameter between 1 pm and 10 pm . p-LEDs in comparison to conventional LEDs with larger sizes further require a very low current resulting in an overall low power consumption, thereby reducing the amount of heat generated during operation . This again not only saves power , which is particularly suitable for short and midrange interconnects , but also simplifies the requirements regarding the heat transfer layer enabling a dense application of such optoelectronic components . However, apart from the requirement of a high quantum efficiency to provide enough light , data communication also requires a high switchability or more general a large amplitude modulation depth at high frequencies . Current optical data communication ranges from several hundred Megahertz to a few Gigahertz , for example in the range between 10 GHz and 50 GHz .

As a result thereof , current p-LEDs have to be switched on and off or at least modulated in their respective emission amplitude within that frequency range . Given the fact , that a light pulse in itself requires a certain length to be detected at the receiver end, such high frequencies require a radiative recombination lifetime in the range of a few ten picoseconds and less . The radiative recombination lifetime is the time required for the minority charge carriers to recombine under radiation after turning off the current through the p-LEDs . Consequently, the radiative recombination life directly affects the fall time of a light pulse emitted by the p-LEDs .

Various measures have been proposed to reduce the rise and fall times during a pulse or amplitude modulated emission, as current p-LEDs are limited in this regard resulting in a switching time of only a few hundred megahertz and rise and fall times to 100 ps or more .

As an example , background doping in the quantum barriers of the respective optoelectronic components can be implemented in order to increase the charge carrier density . While this is suitable in some cases , it requires a precise control during the epitaxial growth of the quantum barriers . As an alternative , non-radiative defect centres within the active region can be provided to increase the non-radiative recombination competing with radiative recombination of the charge carrier . However, due to dopant or defect centre diffusion and other characteristics , those induced measures face reliability issues and are difficult to control during processing of the devices .

It is thus an obj ect of the present invention, to provide an optoelectronic device that can be used for optical data communication with a reduced energy consumption while maintaining or even increasing the data transmission rate to be achieved or decreasing the switching time required for this . SUMMARY OF THE INVENTION

This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

The inventors have recognized that for optoelectronic devices such as p-LEDs based on a gallium arsenide ( GaAs ) , or indium aluminum gallium arsenide ( InAlGaAs ) material systems , increasing the current density through the optoelectronic device increases the carrier concentration in the area of radiative recombination . This results in higher recombination rates and, thus , higher switching speeds to be achieved with the optoelectronic device . The current density at a given current and a given size of the optoelectronic device is thereby in particular increased by reducing the region through which the current flow is conducted through the active region of the optoelectronic device .

In an aspect of the proposed principle , an optoelectronic device such as a -LED comprises a semiconductor layer stack . The semiconductor layer stack includes a first layer having a first doping type and a second layer having a second doping type . The first doping type can for example include an n-type doping, while the second doping type may include a respective p-type doping . In this regard, the first and second layer may comprise a plurality of sub-layers including different doping concentrations and doping profiles , respectively . For example , doped sub-layers opposite an active region may comprise a higher doping concentration suitable for current distribution across the overall area of the respective doped layer .

An active region is arranged between the first and second layer . In some aspects , the active region may comprise a simple pn-j unction . In some other aspects , the active region may comprise a quantum well layer . As a further alternative , the active region may include a multiquantum well structure having a plurality of alternating barrier layers and quantum well layers , respectively . In accordance with the proposed principle , the material for the semiconductor layer stack comprises gallium arsenide ( GaAs ) , or aluminum gallium arsenide ( InAlGaAs ) . Said combination of materials is suitable to emit light in the red, and infrared portion of the spectra . In this regard, the aluminum (Al ) content of the aluminum gallium arsenide Al_xGa!__xAs layers within the layer stack may vary with parameter x and can be in the range between 0% and 70% , respectively . In some aspects , the Al content varies depending on the colour and can reach up to 80% in the outer layers with decreasing Al content in the direction of the active region . With longer wavelengths , i . e . in the infrared spectrum, the Al content can be 30 % and less . In some aspects , the active region may comprise no Al content or less than 10% in some further aspects , the active region may comprise InAlGaAs with an In content from 0% to 50% . In this regard an active region may comprise a multi-quantum well with its barrier layers having an Al content of larger than 10% and its quantum well layers having an AL content of less than 10% .

The semiconductor layer stack comprises a top surface and a bottom surface opposite the top surface as well as mesa structured side surfaces connecting the top and bottom surface . The mesa structured side surfaces , extend from the first layer to the second layer . The side surfaces can be inclined with a varying degree of inclination . In some aspects , the side surfaces extend along a certain crystal direction, in particular in a direction that generates only a few natural non-radiative recombination centres . In some aspects , the inclination of the side surfaces can change . In particular, the inclination of the side surfaces close to the active region may be smaller than an inclination further away and particularly on one of the first and second layer , respectively .

The semiconductor layer stack further comprises a central region with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack . In particular the semiconductor layer comprises a central region extending between the top surface and the bottom surface and being spaced to the side surfaces by at least one fourth of the distance between two opposing side surfaces . The term central region can in particular be understood as a region extending around the center of gravity of the semiconductor layer stack being spaced to the side surfaces by for example by at least one fourth of the distance between two opposing side surfaces , thus the central region comprises a lateral dimension which is less than three quarters , or less than one half of a lateral dimension of the semiconductor layer stack, wherein the lateral dimension extends between opposing side surfaces in a lateral direction . Less than one half of the lateral dimension can in particular mean that the central region comprises approximately less than one nineth of the area of the semiconductor layer stack .

In accordance with the proposed principle , a current path from the first layer to the second layer through the active region is limited to the central region . This can be achieved by several measures addressed in the following aspects . The different aspects allow for example an optimization of the active region size for high current density/switching speeds while keeping a respective size of the semiconductor layer stack for deheating the heat generated within the optoelectronic device during operation of the same . The improved heat management can thereby have positive effects on the reliability and lifetime of the optoelectronic device .

In some aspects , the semiconductor layer stack comprises a partially oxidized Al_xGa!__xAs layer arranged between the first layer and the active region and/or between the second layer and the active region . The parameter x is thereby in particular greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 . The oxidized portion of the partially oxidized Al_xGa!__xAs layer ranges from the side surfaces until the central region whereas the central region of the Al_xGa!__xAs layer remains substantially unoxidized . The partially oxidized Al_xGa!__xAs layer can for example comprise a thickness in the range of 5 nm to 20 nm and/or is optionally doped . By means of the oxidized portion of the partially oxidized Al_xGa!__xAs layer a current confinement of a current applied to the first and second layer is created, since the oxidized area has an insulating effect and the current therefore only flows through the non-oxidized central region into and through the adj acent active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

The oxidation of the Al_xGa!__xAs layer can for example be conducted in a wet oven after mesa structuring the semiconductor layer stack . The depth of the oxidation can in thereby in particular be tuned by for example the time of the step of oxidation within the wet oven . The partially oxidized Al_xGa!__xAs layer can be arranged in the blocking area/active region of the semiconductor layer stack on the first layer , on the second layer, or on both layers .

In some aspects , the active region comprises an intermixed, in particular quantum well intermixed, region outside the central region with a larger band gap than the active region within the central region . By means of the intermixed region of the active region, a current confinement of a current applied to the first and second layer is created, since the intermixed region with a larger bandgap as the central region has a more or less insulating or at least current guiding effect and the current therefore mostly flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

A quantum well intermixing can at the same time result in an increase of the amount of defects ( dangling bonds/ non-radiative recombination centers ) along the side surfaces of the active region to influence the possibilities for non-radiative recombination in the active region . In particular by this the diffusion length/mean-f ree path of the charge carriers is limited to a central region of the active region in which recombination of the charge carriers under the emission of light can take place resulting in a reduced charge carrier lifetime . By the term "charge carrier lifetime" it is in particular to be understood the time t , until which a charge carrier within the active region recombines under the emission of light or non-radiatively . A high charge carrier lifetime comes with a high switch off time of the optoelectronic devices and thus with a reduced possible switching time of the optoelectronic devices , as charge carriers within the active region with a high lifetime may recombine under the emission of light well after the point in time when the optoelectronic devices are already disconnected from their electrical supply . Such an "afterglow" does not allow to provide fast switching frequencies , e . g . in the GHz range . By means of a quantum well intermixing of the active region in regions outside the central region, the charge carrier lifetime can however be reduced resulting in a high switch off time of the optoelectronic device .

In some aspects , the active region and in particular the semiconductor layer stack comprises an ion implanted region outside the central region with having a worse conductivity than the active region within the central region and in particular the semiconductor layer stack within the central region . The ion implantation can in particular be conducted by means of an ion bombardment of the side surfaces of the semiconductor layer stack resulting in an ion implanted region outside the central region . The type of ions and the amount of ions implanted into the semiconductor layer stack outside the central region can thereby be chosen such that the ion implanted region outside the central region comprises a worse conductivity than within the central region or higher insulating properties than within the central region . In addition or as an alternative due to the ion implantation, the active region outside the central region can comprise a larger bandgap than within the active region .

By means of the ion implanted region outside the central region, a current confinement of a current applied to the first and second layer is created, since the ion implanted region with a larger bandgap and/or a worse conductivity as the central region has a more or less insulating or at least current guiding effect and the current therefore mostly flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

As described for the quantum well intermixing , the ion implantation can at the same time result in an increase of the amount of defects ( dangling bonds/ non-radiative recombination centers ) along the side surfaces of the active region to influence the possibilities for non- radiative recombination in the active region . In particular by this the diffusion length/mean-f ree path of the charge carriers is limited to a central region of the active region in which recombination of the charge carriers under the emission of light can take place resulting in a reduced charge carrier lifetime . Hence , by means of a ion implantation of the active region in regions outside the central region, the charge carrier lifetime can be reduced resulting in a high switch off time of the optoelectronic device .

In some aspects , the first and/or the second layer is limited to the central region . The first and/or second layer can in particular be selectively grown on the active region such that it is limited to the central region . By means of this a current confinement of a current applied to the first and second layer is created, since the first and/or second layer being already limited to the central region resulting in a current guiding effect and the current therefore mostly flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

Some further aspects concern the semiconductor layer stack . In some aspects , the semiconductor layer stack comprises a first and second, - in particular- undoped cladding layer . The cladding layers are located directly adj acent to the active region and may comprise , for example undoped aluminum gallium arsenide . The cladding layer is usually used to prevent an undesired diffusion of dopants from the doped first and second layers into the active region . The thickness of the cladding layer may range from a few nm to a few 10 nm .

In some aspects , the active region may comprise a quantum well layer having an additional doping level in the range between lel 6 1/cm³ to lel8 1 /cm³ . The additional doping level increases the charge carrier density within the quantum well layer , thereby reducing the carrier lifetime . Accompanying it with the other measures , the overall radiative lifetime can be further reduced .

In some further aspects , the active region comprises a multi-quantum well structure having a plurality of alternating barrier layers and quantum well layers . The barrier layers comprise a higher Al content than the adj acent quantum well layers . In this regard, at least two barrier layers can comprise a doping level in the range of lel 6 1/cm³ to lel8 1 /cm³ . Similar to the previous embodiment , the charge carrier density in the barrier layers is increased, thereby reducing the radiative lifetime .

In a further aspects , the active region may comprise a plurality of quantum dots , in particular , GaAs /AlGaAs quantum dots . Inserting quantum dots instead of quantum wells in the active region may also increase the overall switching speed due to their faster recombination . Similar to the previous embodiments , this aspect can be combined with the implementation of the non-radiative recombination centres .

In this regard, the optoelectronic device can be implemented as a vertical or horizontal optoelectronic device . In a horizontal optoelectronic device the device comprises their respective highly doped or otherwise conductive contact areas on the same side of the layer stack and preferably opposite the main emission surface of the device . A vertical optoelectronic device comprises respective highly doped or otherwise conductive contact areas on two opposing sides , wherein one of the contact areas may also include the main emission surface . The proposed principle illustrated in the various embodiments later on are not limited to vertical or horizontal optoelectronic devices but can be implemented in both . In some aspects , the optoelectronic device further comprises at least one regrowth layer covering the side surfaces and/or optionally a passivation layer arranged on exposed surfaces of the regrowth layer and/or exposed surfaces of the semiconductor layer stack . The at least one regrowth layer can for example be a structure of alternating layers having different doping types such as for example a pnp or an npn structure covering the side surfaces of the semiconductor layer stack . Such an embodiment can in particular also be suitable even without any of aforementioned aspects for current confinement within the semiconductor layer stack when reducing the lateral dimensions of the semiconductor layer stack to an ablute minimum, and thus reducing the emission area of the active region . At the same time this results in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device . The at least one regrowth layer and/or passivation layer thereby acts as current confinement structure to guide the current through the active region and preserves the side surfaces from other unwanted effects .

In some aspects , the optoelectronic device further comprises a first contact element arranged on the first layer and/or a second contact element arranged on the second layer . The first and/or second contact element in particular serve to provide a supply current to the optoelectronic device . The first and/or second contact element can for example be of a transparent conductive oxide (TCO ) to allow light being generated within the active region being emitted from the optoelectronic device and/or the first second contact element can when viewed onto the bottom surface , comprise a structure with a central region of the first and/or second layer remaining free of the first contact element and in particular forming a ring . It is however also conceivable that the first and/or second contact element completely cover the respective underlying semiconductor layer .

According to at least one aspect , the central region of the active region comprises a lateral dimension of less than the diffusion length of the material system of the active region . By this the charge carrier lifetime can further be reduced and desired switching times for the optoelectronic device can be achieved .

According to at least one aspect , the optoelectronic device is configured to have a switching on and/or off time in the range of 0 , 5 ns to 10ns , in particular a switching on and/or off time down to 0 , 1ns . With such a switching time , fast switching frequencies , e . g . in the GHz range , can be realized .

According to a further aspect of the present invention, the optoelectronic device according to at least one of aforementioned aspects can be used as a means for optical data communication, in particular short distance communication of less than 10m . The optoelectronic device according to at least one of aforementioned aspects can in particular be used for data transmission in large data centres and the like , to transmit data over short distances (<<10m) for example from CPU to GPU, server to server , and/or rack to rack .

Further aspects refer to a method of manufacturing an optoelectronic device . The method provides a semiconductor layer stack having a first layer and a second layer . The first layer comprises a first doping type and the second layer comprises a second doping type . An active region is arranged between the first and second layer . The semiconductor layer stack is thereby comprising a material including at least one of phosphide and arsenide and is for example based on an GaAs /AlGaAs material combination .

In a further step, a mesa etching process is conducted to form side surfaces connecting a top and a bottom surface of the semiconductor layer stack and exposing portions of the active region in a circumferential perimeter . In a top view, said perimeter can have the shape of a circle , a rectangle , or a polygon like a hexagon for example .

The semiconductor layer stack is then processed in such a way that a central region with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack is formed and such that a current path from the first layer to the second layer through the active region is limited to that central region . Hence the semiconductor layer stack is processed to realize a current confinement of a current applied to the first and second layer to a central region of at least the active region . This can be achieved by several measures addressed in the following aspects . The different aspects allow for example an optimization of the active region size for high current density/switching speeds while keeping a respective size of the semiconductor layer stack for deheating the heat generated within the optoelectronic device during operation of the same . The improved heat management can thereby have positive effects on the reliability and lifetime of the optoelectronic device .

In some aspects , the step of providing a semiconductor layer stack comprises depositing an Al_xGa!__xAs layer arranged between the first layer and the active region and/or between the second layer and the active region . The parameter x is thereby in particular greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 . The Al_xGa!__xAs layer can for example comprise a thickness in the range of 5 nm to 20 nm and/or is optionally doped in the same range as the first and second doped layers of the layer stack . Suitable doping concentrations are known to the skilled person .

In some aspects , the step of processing the semiconductor layer stack comprises partially oxidizing the Al_xGa!__xAs layer ( s ) such that the oxidized portion of the partially oxidized Al_xGa!__xAs layer ranges from the side surfaces until the central region and the central portion remains substantially unoxidized . Hence the semiconductor layer stack comprises a partially oxidized Al_xGa!__xAs layer arranged between the first layer and the active region and/or between the second layer and the active region . The oxidized portion of the partially oxidized Al_xGa!__xAs layer ranges from the side surfaces until the central region whereas the central region of the Al_xGa!__xAs layer remains substantially unoxidized . By means of the oxidized portion of the partially oxidized Al_xGa!__xAs layer a current confinement of a current applied to the first and second layer is created, since the oxidized area has an insulating effect and the current therefore only flows through the non-oxidized central region into and through the adj acent active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

In some aspects , the step of processing the semiconductor layer stack comprises implanting ions into at least the active region and in particular the semiconductor layer stack outside the central region forming an ion implanted region outside the central region having a worse conductivity and or higher bandgap than the active region within the central region and in particular the semiconductor layer stack within the central region . The ion implantation can be conducted by means of an ion bombardment of the side surfaces followed by for example a step of annealing such that at least the active region and in particular the semiconductor layer stack outside the central region forms an ion implanted region outside the central region having a worse conductivity and/or larger bandgap than the active region within the central region and in particular the semiconductor layer stack within the central region . By means of the ion implanted region outside the central region a current confinement of a current applied to the first and second layer is created, since the ion implanted region has an insulating effect and the current therefore only flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device .

In some aspects , the step of processing the semiconductor layer stack comprises intermixing, in particular quantum well intermixing , the active region outside the central region forming a region of the active region with a larger band gap than the active region within the central region . By means of the intermixed region outside the central region a current confinement of a current applied to the first and second layer is created, since the intermixed region has an insulating effect and the current therefore only flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device . The intermixing of the active region can thereby be conducted by any know process known in the art .

In some aspects , the step of providing or the step of processing the semiconductor layer stack comprises a structuring and/or selevtive growth of the first and/or the second layer such that the first and/or second layer is limited to the central region . In particular a selective growth of the first and/or the second layer on the active region comprises providing a hardmask of for example SiO₂ or Si₃N₄ on the active region adj acent to the central region and growing the first and/or the second layer on the active region in the central region . The limitation of the first and or second layer results in a current confinement of a current applied to the first and second layer , since the current only flows through the central region through the active region . Although this results in a smaller emission area of the active region it results on the other hand in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device . The structuring and/or growing of the first and/or second layer can thereby be conducted by any know process known in the art .

In some aspects , the method further comprises a step of regrowing at least one regrowth layer on the side surfaces and/or optionally a step of growing a passivation layer on exposed surfaces of the regrowth layer ( s ) and/or on exposed surfaces of the semiconductor layer stack . In some aspects , the method further comprises a step of providing a first contact element on the first layer and/or a bottom contact element on the second layer . The first and/or second contact element can thereby be formed according to aforementioned aspects described for the optoelectronic device .

In some aspects , the step of providing the semiconductor layer stack comprises providing a first and a second, in particularly undoped cladding layer directly adj acent to the active region . To this extent the semiconductor layer stack comprises in some aspects a first and a second, in particularly undoped cladding layer directly adj acent to the active region . Those layer prevent diffusion of dopants but can also be used as a charge carrier blocking structure .

The optoelectronic device such as a p-LED presented herein is suitable for a variety of applications , in which a high switching or current modulation frequency is required . In some aspects , the optoelectronic device according to the proposed principle is used in optical data communication, particularly in the short and medium range with modulation frequencies larger than 1 GHz and particularly larger than 10 GHz .

SHORT DESCRIPTION OF THE DRAWINGS

Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which

Figures 1A to ID show steps of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 2A to 2D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; Figures 3a to 3D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;

Figures 4A to 4D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ; and

Figures 5A to 5D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle .

DETAILED DESCRIPTION

The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form . It should be noted that in practice slight differences and deviations from the ideal form may occur without , however , contradicting the inventive idea .

In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures .

Figures 1A to ID illustrate steps of a method for manufacturing an optoelectronic device , in particular p-LED 1 in accordance with the proposed principle . These steps are conducted in a similar manner in all the respective embodiments illustrated herein . However , certain variations and deviations from the illustrated steps can be implemented without deviating from the overall scope . In addition, although only vertical optoelectronic devices are illustrated herein, one will recognize that the proposed principle is not restricted to such devices . Rather , the respective contact areas can be arranged on the same side with a via leading through the active region and connecting the desired doped layer .

Figure 1A illustrates the epitaxial deposition of a semiconductor layer stack 2 on the respective growth substrate 11 . The growth substrate 11 comprises an n-doped gallium arsenide layer, which acts as wafer substrate , on which the subsequent layers are epitaxially deposited . Furthermore , the n-doped gallium arsenide substrate may comprise a plurality of buffer layers to smooth and flattening its surface , such as to provide a substantially defect free surface .

In a subsequent step , an n-doped aluminum gallium arsenide layer 3 is epitaxially deposited on the surface of the growth substrate as a first semiconductor layer . The first layer 3 can comprise a doping distribution and/or a varying doping concentration based on the required needs . For example , the doping concentration closer to the growth substrate 11 may be larger than further away to improve the charge carrier inj ection into the aluminum gallium arsenide layer 3 . Furthermore , the aluminum content of the first layer 3 may vary and also comprise a respective distribution over the thickness of the first layer 3 . To this extent , first layer 3 can include one or more sublayers , in which the above-mentioned varying concentrations and distributions of dopants and Al content are implemented . On top of the first layer 3 , first Al_xGai__xAs layer 12 is arranged, where parameter x is greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 . First Al_xGa!__xAs layer 12 can in particular comprise an Al content such that first Al_xGa!__xAs layer 12 can easily be oxidized .

On top of the first Al_xGa!__xAs layer 12 an undoped aluminum gallium arsenide first cladding layer 14 is deposited . The aluminum content of that layer may be similar to the aluminum content of the first layer 3 but can also vary to improve the charge carrier transport diffusion into the active region 5 epitaxially deposited on top of first cladding layer 14 . The thickness of first cladding layer 14 is in the range between 10 nm and 50 nm. The purpose of first cladding layer 14 is to prevent diffusion of dopants from the first layer 3 and the first Al_xGa!__xAs layer 12 respectively into the active region 5 .

Active region 5 is deposited thereupon and comprises a pn-j unction or a multi-quantum well structure in this embodiment . The multi-quantum well structure for example includes a plurality of barrier layers and quantum well layers , respectively, whereas the aluminum content for the barrier layers is slightly larger than the aluminum content of the respective quantum well layers . Consequently, a varying band gap in the semiconductor material of active region 5 is provided, trapping the charge carriers between the "valleys" of the bandgap .

Active region 5 is covered by another cladding layer 15 of aluminum gallium arsenide similar to the first cladding layer 14 .

On top of the second cladding layer 15 , second Al_xGa!__xAs layer 13 is arranged, where parameter x is greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 . Second Al_xGa!__xAs layer 13 can in particular comprise an Al content such that second Al_xGa!__xAs layer 13 can easily be oxidized .

On top of the second Al_xGai__xAs layer 13 a p-doped layer 4 is deposited as a second semiconductor layer . Similar to the n-doped layer 3 , the doping concentration as well as the doping distribution of the p-doped aluminum gallium arsenide layer 4 may vary .

In this regard, both layers 3 and 4 may not only comprise aluminum gallium arsenide sublayers , but can also include one or more gallium arsenide sub-layers or aluminum gallium arsenide sub-layers with varying aluminum content . The purpose of these sublayers is to distribute the inj ected charge carriers across the overall area of the semiconductor layer stack 2 and will provide a continuous and equally distributed diffusion towards the active region .

The top surface of the second layer 4 is covered by a highly doped gallium arsenide contact layer 16 . The contact layer 16 provides not only a connection to a conductive metal or a transparent conductive oxide , but also acts as the main emission surface in operation of the device 1 later on .

The first and the second Al_xGai__xAs layer 12 and 13 are for example very thin layers containing aluminum gallium arsenide with a high aluminum content introduced between the first and second layer 3 and 4 and the respective cladding layer 14 and 15 or more generally between the first and second layer 3 and 4 and the active region 5 . The aluminum content of the Al_xGa!__xAs layers comprise a very high aluminum content with parameter x larger than 0 . 9 and particularly larger than 0 . 97 .

The next step of the proposed method is illustrated in Figure IB . A not shown mas k layer material is deposited on the p-doped gallium arsenide contact layer 16 and subsequently structured to form a central portion of the hard mask layer .

In a top view the central portion forms a circle , a rectangle , or any other polygon like a hexagon structure . Then, one or more mesa etching steps are performed to provide side surfaces 2 c exposing the facets of active region 5 as well as the first and second layer 3 and 4 , respectively . The results of the mesa etching process is illustrated in Figure IB and can be achieved by several subsequent mesa etching steps . In a twostep process , the side surfaces 2c of the semiconductor layer stack 2 and in particular of the active region 5 can in addition for example be cleaned and annealed after the first etching step to remove any plasma damages from the side surfaces 2 c .

For example , in a first mesa etching step, material of contact layer 16 , the p-doped aluminum gallium arsenide layer 4 , the cladding layers 14 and 15 , first and second Al_xGa!__xAs layer 12 and 13 as well as active region 5 is removed using a plasma etching process or any similar suitable way . The exposed surfaces are cleaned and annealed using NH₃ or other suitable gas . The cleaning reduces the damages and the non- radiative recombination centres after the mesa etching process to obtain more defined side surfaces 2 c, preferably with only a small number of non-radiative recombination centres and thus a defined surface state .

To increase the charge carrier density within the active region 5 , the semiconductor layer stack 2 is then processed as shown in Figure 1C . The semiconductor layer stack is therefore exposed to an oxygen containing atmosphere ( shown by the two arrows ) , initiating an oxidation of the aluminum within the first and second Al_xGa!__xAs layer 12 and 13 . Due to the oxygen containing atmosphere and the high Al content of layers 12 and 13 , a portion of the layers 12 and 13 starting from the side surfaces 2c is oxidized resulting in oxidized thin portions of the layers 12 and 13 until a central region 10 of the semiconductor layer stack 2 .

The oxidation results in a constrain of the conductivity of the first and second Al_xGa!__xAs layer 12 and 13 to some smaller central portion thereof similar to apertures for the charge carriers , as indicated in Figure ID . Hence , the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time for example in addition a defined amount of non-radiative recombination centres can be formed beneath and above the active region 5 as well as on the circumferential perimeter . By this , the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region . To receive the optoelectronic device as shown in Figure ID, the growth substrate 11 is removed, top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces are passivated by means of a passivation layer 8 . In the embodiment shown, the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .

The method according to the proposed principle follows the latter approach but can be combined with other measures to increase the charge density or the bandgap structure to provide a faster radiative recombination .

Figures 2A to 2D illustrate a respective embodiment thereof . The steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 2A and 2B thereby relate to the embodiment shown in Figures 1A and IB but without providing the first and the second Al_xGa!__xAs layer . To increase the charge carrier density within the active region 5 , the semiconductor layer stack 2 is then processed as shown in Figure 2C .

To increase the charge carrier density within the active region 5 , a structured mask 9 is provided on the semiconductor layer stack 2 to conduct a quantum well intermixing ( indicated by the vertical arrows ) of the active region 5 in a region between the side surfaces 2 c and the central region 10 . Therefrom intermixed regions 17 of the active region 5 result having a larger bandgap than the active region within the central region 10 not being quantum well intermixed .

The intermixing results in a higher bandgap of the active region 5 outside the central region 10 . Hence the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time a defined amount of non-radiative recombination centres is formed beneath and above the active region 5 as well as on the circumferential perimeter . By this , the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region and increase the amount of non-radiative recombination centres in the intermixed region 17 .

To receive the optoelectronic device as shown in Figure 2D, the growth substrate 11 is removed, top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces 2 c are passivated by means of a passivation layer 8 . In the embodiment shown, the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .

Figures 3A to 3D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 . The steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 3A and 3B thereby relate to the embodiment shown in Figures 2A and 2B with the difference of providing an active region with a simple pn-j unction and not a quantum well or multi quantum well layer . This is however understood to be exemplary and can also be in the same way as shown in Figures 2A and 2B . To increase the charge carrier density within the active region 5 , the semiconductor layer stack 2 is then processed as shown in Figure 3C .

To increase the charge carrier density within the active region 5 , a structured mask 9 is provided on the semiconductor layer stack 2 to conduct an ion bombardment of the side surfaces 2 c ( indicated by the arrows ) of the semiconductor layer stack 2 in a region between the side surfaces 2 c and the central region 10 . Therefrom ion implanted regions 18 of semiconductor layer stack 2 result having semi insulating properties and in particular a worse conductivity than the semiconductor layer stack 2 within the central region 10 . In addition, the ion bombardment can cause the active region outside the central region 10 having a larger bandgap than the active region 5 within the central region 10 . The ion bombardment results in a worse conductivity of the layers adj acent to the active region 5 as well as a higher bandgap of the active region 5 outside the central region 10 . Hence the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time a defined amount of non-radiative recombination centres is formed beneath and above the active region 5 as well as on the circumferential perimeter . By this , the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region and increase the amount of non-radiative recombination centres in the intermixed region 17 .

To receive the optoelectronic device as shown in Figure 3D, the growth substrate 11 is removed, and top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a , 2b of the semiconductor layer stack 2 . In the embodiment shown, the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .

Figures 4A to 4D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 . The steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 4A to 4C thereby relate to the embodiment shown in Figures 3A and 3B with the difference that the second layer 4 as well as the contact layer 16 is provided selectively on the active region 5 using a structured mas k 9 only in the central region 10 of the semiconductor layer stack 2 . This step can in this embodiment already be understood as the step, by means of which the charge carrier density within the active region 5 is increased . The semiconductor layer stack 2 is then mesa structured as shown in Figure 4C to receive side surfaces 2 c of the semiconductor layer stack 2 .

The selective growth results in current feed into the active region 5 only in the central region 10 . Hence the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure . By this , the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region 5 .

To receive the optoelectronic device as shown in Figure 4D, the growth substrate 11 is removed, top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces 2 c are passivated by means of a passivation layer 8 . In the embodiment shown, the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .

Figures 5A to 5D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 . The steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 5A and 5B thereby relate to the embodiment shown in Figures 3A and 3B with the difference that by means of the mesa structuring using a structured mas k 9 , an already smaller semiconductor layer stack 2 is pixelated with smaller lateral dimensions compared to aforementioned embodiments .

By this the charge carrier density within the active region 5 can be increased compared to a larger sized layer stack 2 with larger lateral dimensions and assuming the same current is applied to the active region 5 . To now increase the efficiency of the optoelectronic device regrowth layers 6 are provided along the side surfaces 2c of the semiconductor layer stack 2 . The regrowth layers 6 can for example be a structure of alternating layers having different doping types such as for example a pnp or a npn structure covering the side surfaces 2 c of the semiconductor layer stack 2 . Such an embodiment can in particular also be suitable in combination with any of aforementioned aspects for current confinement within the semiconductor layer stack 2 . This results in a higher carrier concentration in the area of radiative recombination resulting in higher recombination rates and, thus , higher switching speeds of the optoelectronic device 1 . The regrowth layers 6 thereby act as current confinement structure to guide the current through the active region 5 and preserve the side surfaces 2 c from unwanted effects .

To receive the optoelectronic device as shown in Figure 5D, the growth substrate 11 is removed, and top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a , 2b of the semiconductor layer stack 2 . In the embodiment shown, the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .

LIST OF REFERENCES optoelectronic device , p-LED layer stack a top surface b bottom surface c side surface layer layer active region regrowth layer a contact element b contact element passivation layer mas k 0 central region 1 growth substrate 2 Al_xGai__xAs layer 3 Al_xGa!__xAs layer 4 cladding layer 5 cladding layer 6 contact layer 7 intermixed region 8 implanted region

Claims

1. A p-LED (1) comprising: a semiconductor layer stack (2) having a first layer (3) of a first doping type, a second layer (4) of a second doping type, and an active region (5) arranged between the first and the second layer ( 3 , 4 ) ; wherein the semiconductor layer stack (2) comprises a bottom surface (2a) and a top surface (2b) as well as mesa structured side surfaces (2c) connecting the top and bottom surface (2a, 2b) ; wherein the semiconductor layer stack (2) comprises a central region (10) with a lateral dimension which is less than one half or less than three fourth of a lateral dimension of the semiconductor layer stack (2) ; wherein the semiconductor layer stack (2) comprises a material including at least one of phosphide and arsenide; and wherein a current path from the first layer (3) to the second layer (4) through the active region (5) is limited to the central region ( 10 ) .

2. The p-LED according to claim 1, wherein the semiconductor layer stack (2) comprises a partially oxidized Al_xGa!__xAs layer (12, 13) arranged between the first layer (3) and the active region (5) and/or the second layer (4) and the active region (5) , wherein parameter x is greater than 0.5 and in particular greater than 0.9 and in particular greater than 0.97, wherein the oxidized portion of the partially oxidized Al_xGa!_ xAs layer (s) (12, 13) ranges from the side surfaces (2c) until the central region (10) and the central region (10) of the Al_xGa!__xAs layer (s) (12, 13) remains substantially unoxidized, and wherein optionally the partially oxidized Al_xGa!__xAs layer (s) (12, 13) comprises a thickness in the range of 5 nm to 20 nm; and/or wherein optionally the partially oxidized Al_xGai__xAs layer (s) (12, 13) is doped.

3. The p-LED according to claim 1 or 2, wherein the active region (5) comprises an intermixed, in particular quantum well intermixed, region (17) outside the central region (10) with a larger bandgap than the active region (5) within the central region (10) .

4. The p-LED according to any one of claims 1 to 3, wherein the active region (5) and in particular the semiconductor layer stack (2) comprises an ion implanted region (18) outside the central region (10) having a worse conductivity and/or larger bandgap than the active region (5) within the central region (10) and in particular the semiconductor layer stack (2) within the central region (10) .

5. The p-LED according to any one of claims 1 to 4 , wherein the first and/or the second layer (3, 4) is limited to the central region (10) .

6. The p-LED according to any one of claims 1 to 5, wherein the semiconductor layer stack (2) comprises a first and a second, in particularly undoped, cladding layer (14, 15) directly adjacent to the active region (5) .

7. The p-LED according to any one of claims 1 to 6, wherein the active region (5) comprises at least one of:

At least one quantum well layer comprising a doping level in the range between lel6 1/cm³ and lel8 2/cm³;

At least two barrier layers encompassing at least one quantum well layer, said at least two barrier layers comprising a doping level in the range between lel6 1/cm³ and lel8 1/cm³;

A plurality of quantum dots .

8. The p-LED according to any one of claims 1 to 7, further comprising at least one regrowth layer (6) covering the side surfaces (2c) and/or optionally a passivation layer (8) arranged on exposed surfaces of the regrowth layer (s) (6) and/or exposed surfaces of the semiconductor layer stack (2) .

9. The p-LED according to any one of claims 1 to 8, further comprising a first contact element (7a) arranged on the first layer (3) and/or a second contact element (7b) arranged on the second layer (4) .

10. The p-LED according to claim 9, wherein, when viewed onto the bottom surface (2a) , a central region of the first layer (3) remains free of the first contact element (7a) , the first contact element (7a) in particular comprising the form of a ring.

11. The p-LED according to any one of the preceding claims, wherein the central region (10) of the active region (5) comprises a lateral dimension of less than the diffusion length of the material system of the active region (5) .

12. The p-LED according to any one of the preceding claims, wherein the p-LED (1) is configured to have a switching on and/or off time in the range of 0,1 ns to 10ns.

13. Use of a p-LED (1) according to any one of the preceding claims as a means for optical data communication, in particular short distance communication of less than 10m.

14. A method for manufacturing p-LED (1) , comprising the steps:

Providing a semiconductor layer stack (2) having a first layer (3) of a first doping type, a second layer (4) of a second doping type, and an active region (5) arranged between the first and the second layer (3, 4) with the semiconductor layer stack (2) comprising a material including at least one of phosphide and arsenide ; Structuring the semiconductor layer stack (2) such that the semiconductor layer stack (2) comprises side surfaces (2c) connecting a top and a bottom surface (2a, 2b) of the semiconductor layer stack (2) ;

Processing the semiconductor layer stack (2) in such a way that a central region (10) with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack (2) is formed and such that a current path from the first layer (3) to the second layer (4) through the active region (5) is limited to that central region (10) .

15. Method according to claim 14, wherein the step of providing a semiconductor layer stack (2) comprises:

- Depositing an Al_xGa!__xAs layer (12, 13) arranged between the first layer (3) and the active region (5) and/or between the second layer (13) and the active region (5) , wherein parameter x is greater than 0.5 and in particular greater than 0.9 and in particular greater than 0.97; and wherein

- optionally the Al_xGa!__xAs layer (s) (12, 13) comprises a thickness in the range of 5 nm to 20 nm; and/or wherein

- optionally the Al_xGa!__xAs layer (s) (12, 13) is doped.

16. Method according to claim 15, wherein the step of processing the semiconductor layer stack (2) comprises partially oxidizing the Al_xGa!__xAs layer (s) (12, 13) such that the oxidized portion of the partially oxidized Al_xGai__xAs layer (s) (12, 13) ranges from the side surfaces (2c) until the central region (10) and such that the portion of the Al_xGa!__xAs layer (s) (12, 13) within the central region (10) remains substantially unoxidized.

17. Method according to any one of claims 14 to 16, wherein the step of processing the semiconductor layer stack (2) comprises implanting ions into at least the active region (5) and in particular the semiconductor layer stack (2) outside the central region (10) forming an ion implanted region (18) outside the central region (5) having a worse conductivity and/or larger bandgap than the active region (5) within the central region (10) and in particular the semiconductor layer stack (2) within the central region ( 10 ) .

18. Method according to any one of claims 14 to 17, wherein the step of processing the semiconductor layer stack (2) comprises intermixing, in particular quantum well intermixing, the active region (5) outside the central region (10) forming an intermixed region (17) of the active region (5) with a larger band gap than the active region (5) within the central region (10) .

19. Method according to any one of claims 14 to 18, wherein the step of processing the semiconductor layer stack (2) comprises structuring the first and/or the second layer (3, 4) such that the first and/or second layer (3, 4) is limited to the central region (10) .

20. Method according to any one of claims 14 to 19, further comprising a step of regrowing at least one regrowth layer (6) on the side surfaces (2c) and/or optionally growing a passivation layer (8) on exposed surfaces of the regrowth layer (s) (6) and/or exposed surfaces of the semiconductor layer stack (2) .

21. Method according to any one of claims 14 to 20, further comprising a step of providing a first contact element (7a) on the first layer (3) and/or a second contact element (7b) on the second layer (4) .