WO2024251732A1 - Μleds à commutation rapide ou à base d'ingaalas pour communication de données à grande vitesse - Google Patents

Μleds à commutation rapide ou à base d'ingaalas pour communication de données à grande vitesse Download PDF

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Publication number
WO2024251732A1
WO2024251732A1 PCT/EP2024/065331 EP2024065331W WO2024251732A1 WO 2024251732 A1 WO2024251732 A1 WO 2024251732A1 EP 2024065331 W EP2024065331 W EP 2024065331W WO 2024251732 A1 WO2024251732 A1 WO 2024251732A1
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Prior art keywords
layer
active region
semiconductor layer
central region
layer stack
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English (en)
Inventor
Philipp Kreuter
Martin Hetzl
Norwin Von Malm
Tansen Varghese
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Ams Osram International GmbH
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Ams Osram International GmbH
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Priority to CN202480038034.1A priority Critical patent/CN121312293A/zh
Priority to DE112024002463.7T priority patent/DE112024002463T5/de
Publication of WO2024251732A1 publication Critical patent/WO2024251732A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H10H20/8162—Current-blocking structures

Definitions

  • the present invention concerns a p-LED for use as a means for optical data communication, as well as a method for manufacturing the p-LED .
  • p-LEDs for optical and data communication has several benefits .
  • the vertical or horizontal optoelectronic components provide an improved scalability and can be easily implemented in existing designs at large numbers .
  • a p- LED is an optoelectronic component that comprises a diameter or more general a dimension that is smaller than 50 pm and in particular smaller than 20 pm .
  • a p-LED can range in diameter between 1 pm and 10 pm .
  • p-LEDs in comparison to conventional LEDs with larger sizes further require a very low current resulting in an overall low power consumption, thereby reducing the amount of heat generated during operation .
  • background doping in the quantum barriers of the respective optoelectronic components can be implemented in order to increase the charge carrier density . While this is suitable in some cases , it requires a precise control during the epitaxial growth of the quantum barriers .
  • non-radiative defect centres within the active region can be provided to increase the non-radiative recombination competing with radiative recombination of the charge carrier .
  • dopant or defect centre diffusion and other characteristics those induced measures face reliability issues and are difficult to control during processing of the devices .
  • the inventors have recognized that for optoelectronic devices such as p-LEDs based on a gallium arsenide ( GaAs ) , or indium aluminum gallium arsenide (InAlGaAs ) material systems , increasing the current density through the optoelectronic device increases the carrier concentration in the area of radiative recombination . This results in higher recombination rates and, thus , higher switching speeds to be achieved with the optoelectronic device .
  • the current density at a given current and a given size of the optoelectronic device is thereby in particular increased by reducing the region through which the current flow is conducted through the active region of the optoelectronic device .
  • the semiconductor layer stack includes a first layer having a first doping type and a second layer having a second doping type .
  • the first doping type can for example include an n-type doping
  • the second doping type may include a respective p-type doping .
  • the first and second layer may comprise a plurality of sub-layers including different doping concentrations and doping profiles , respectively .
  • doped sub-layers opposite an active region may comprise a higher doping concentration suitable for current distribution across the overall area of the respective doped layer .
  • the active region is arranged between the first and second layer .
  • the active region may comprise a simple pn-j unction .
  • the active region may comprise a quantum well layer .
  • the active region may include a multiquantum well structure having a plurality of alternating barrier layers and quantum well layers , respectively .
  • the material for the semiconductor layer stack comprises gallium arsenide ( GaAs ) , or aluminum gallium arsenide ( InAlGaAs ) . Said combination of materials is suitable to emit light in the red, and infrared portion of the spectra .
  • the aluminum (Al ) content of the aluminum gallium arsenide Al x Ga!_ x As layers within the layer stack may vary with parameter x and can be in the range between 0% and 70% , respectively .
  • the Al content varies depending on the colour and can reach up to 80% in the outer layers with decreasing Al content in the direction of the active region . With longer wavelengths , i . e . in the infrared spectrum, the Al content can be 30 % and less .
  • the active region may comprise no Al content or less than 10% in some further aspects , the active region may comprise InAlGaAs with an In content from 0% to 50% .
  • an active region may comprise a multi-quantum well with its barrier layers having an Al content of larger than 10% and its quantum well layers having an AL content of less than 10% .
  • the semiconductor layer stack comprises a top surface and a bottom surface opposite the top surface as well as mesa structured side surfaces connecting the top and bottom surface .
  • the mesa structured side surfaces extend from the first layer to the second layer .
  • the side surfaces can be inclined with a varying degree of inclination .
  • the side surfaces extend along a certain crystal direction, in particular in a direction that generates only a few natural non-radiative recombination centres .
  • the inclination of the side surfaces can change .
  • the inclination of the side surfaces close to the active region may be smaller than an inclination further away and particularly on one of the first and second layer , respectively .
  • the semiconductor layer stack further comprises a central region with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack .
  • the semiconductor layer comprises a central region extending between the top surface and the bottom surface and being spaced to the side surfaces by at least one fourth of the distance between two opposing side surfaces .
  • the term central region can in particular be understood as a region extending around the center of gravity of the semiconductor layer stack being spaced to the side surfaces by for example by at least one fourth of the distance between two opposing side surfaces , thus the central region comprises a lateral dimension which is less than three quarters , or less than one half of a lateral dimension of the semiconductor layer stack, wherein the lateral dimension extends between opposing side surfaces in a lateral direction .
  • Less than one half of the lateral dimension can in particular mean that the central region comprises approximately less than one nineth of the area of the semiconductor layer stack .
  • a current path from the first layer to the second layer through the active region is limited to the central region .
  • This can be achieved by several measures addressed in the following aspects .
  • the different aspects allow for example an optimization of the active region size for high current density/switching speeds while keeping a respective size of the semiconductor layer stack for deheating the heat generated within the optoelectronic device during operation of the same .
  • the improved heat management can thereby have positive effects on the reliability and lifetime of the optoelectronic device .
  • the semiconductor layer stack comprises a partially oxidized Al x Ga!_ x As layer arranged between the first layer and the active region and/or between the second layer and the active region .
  • the parameter x is thereby in particular greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 .
  • the oxidized portion of the partially oxidized Al x Ga!_ x As layer ranges from the side surfaces until the central region whereas the central region of the Al x Ga!_ x As layer remains substantially unoxidized .
  • the partially oxidized Al x Ga!_ x As layer can for example comprise a thickness in the range of 5 nm to 20 nm and/or is optionally doped .
  • the oxidation of the Al x Ga!_ x As layer can for example be conducted in a wet oven after mesa structuring the semiconductor layer stack .
  • the depth of the oxidation can in thereby in particular be tuned by for example the time of the step of oxidation within the wet oven .
  • the partially oxidized Al x Ga!_ x As layer can be arranged in the blocking area/active region of the semiconductor layer stack on the first layer , on the second layer, or on both layers .
  • the active region comprises an intermixed, in particular quantum well intermixed, region outside the central region with a larger band gap than the active region within the central region .
  • a quantum well intermixing can at the same time result in an increase of the amount of defects ( dangling bonds/ non-radiative recombination centers ) along the side surfaces of the active region to influence the possibilities for non-radiative recombination in the active region .
  • the diffusion length/mean-f ree path of the charge carriers is limited to a central region of the active region in which recombination of the charge carriers under the emission of light can take place resulting in a reduced charge carrier lifetime .
  • charge carrier lifetime it is in particular to be understood the time t , until which a charge carrier within the active region recombines under the emission of light or non-radiatively .
  • a high charge carrier lifetime comes with a high switch off time of the optoelectronic devices and thus with a reduced possible switching time of the optoelectronic devices , as charge carriers within the active region with a high lifetime may recombine under the emission of light well after the point in time when the optoelectronic devices are already disconnected from their electrical supply .
  • Such an "afterglow” does not allow to provide fast switching frequencies , e . g . in the GHz range .
  • the charge carrier lifetime can however be reduced resulting in a high switch off time of the optoelectronic device .
  • the active region and in particular the semiconductor layer stack comprises an ion implanted region outside the central region with having a worse conductivity than the active region within the central region and in particular the semiconductor layer stack within the central region .
  • the ion implantation can in particular be conducted by means of an ion bombardment of the side surfaces of the semiconductor layer stack resulting in an ion implanted region outside the central region .
  • the type of ions and the amount of ions implanted into the semiconductor layer stack outside the central region can thereby be chosen such that the ion implanted region outside the central region comprises a worse conductivity than within the central region or higher insulating properties than within the central region .
  • the active region outside the central region can comprise a larger bandgap than within the active region .
  • the ion implantation can at the same time result in an increase of the amount of defects ( dangling bonds/ non-radiative recombination centers ) along the side surfaces of the active region to influence the possibilities for non- radiative recombination in the active region .
  • the diffusion length/mean-f ree path of the charge carriers is limited to a central region of the active region in which recombination of the charge carriers under the emission of light can take place resulting in a reduced charge carrier lifetime .
  • the charge carrier lifetime can be reduced resulting in a high switch off time of the optoelectronic device .
  • the first and/or the second layer is limited to the central region .
  • the first and/or second layer can in particular be selectively grown on the active region such that it is limited to the central region .
  • a current confinement of a current applied to the first and second layer is created, since the first and/or second layer being already limited to the central region resulting in a current guiding effect and the current therefore mostly flows through the central region through the active region .
  • the semiconductor layer stack comprises a first and second, - in particular- undoped cladding layer .
  • the cladding layers are located directly adj acent to the active region and may comprise , for example undoped aluminum gallium arsenide .
  • the cladding layer is usually used to prevent an undesired diffusion of dopants from the doped first and second layers into the active region .
  • the thickness of the cladding layer may range from a few nm to a few 10 nm .
  • the active region may comprise a quantum well layer having an additional doping level in the range between lel 6 1/cm 3 to lel8 1 /cm 3 .
  • the additional doping level increases the charge carrier density within the quantum well layer , thereby reducing the carrier lifetime .
  • the overall radiative lifetime can be further reduced .
  • the active region comprises a multi-quantum well structure having a plurality of alternating barrier layers and quantum well layers .
  • the barrier layers comprise a higher Al content than the adj acent quantum well layers .
  • at least two barrier layers can comprise a doping level in the range of lel 6 1/cm 3 to lel8 1 /cm 3 . Similar to the previous embodiment , the charge carrier density in the barrier layers is increased, thereby reducing the radiative lifetime .
  • the active region may comprise a plurality of quantum dots , in particular , GaAs /AlGaAs quantum dots . Inserting quantum dots instead of quantum wells in the active region may also increase the overall switching speed due to their faster recombination . Similar to the previous embodiments , this aspect can be combined with the implementation of the non-radiative recombination centres .
  • the optoelectronic device can be implemented as a vertical or horizontal optoelectronic device .
  • the device comprises their respective highly doped or otherwise conductive contact areas on the same side of the layer stack and preferably opposite the main emission surface of the device .
  • a vertical optoelectronic device comprises respective highly doped or otherwise conductive contact areas on two opposing sides , wherein one of the contact areas may also include the main emission surface .
  • the proposed principle illustrated in the various embodiments later on are not limited to vertical or horizontal optoelectronic devices but can be implemented in both .
  • the optoelectronic device further comprises at least one regrowth layer covering the side surfaces and/or optionally a passivation layer arranged on exposed surfaces of the regrowth layer and/or exposed surfaces of the semiconductor layer stack .
  • the at least one regrowth layer can for example be a structure of alternating layers having different doping types such as for example a pnp or an npn structure covering the side surfaces of the semiconductor layer stack .
  • Such an embodiment can in particular also be suitable even without any of aforementioned aspects for current confinement within the semiconductor layer stack when reducing the lateral dimensions of the semiconductor layer stack to an ablute minimum, and thus reducing the emission area of the active region .
  • the at least one regrowth layer and/or passivation layer thereby acts as current confinement structure to guide the current through the active region and preserves the side surfaces from other unwanted effects .
  • the optoelectronic device further comprises a first contact element arranged on the first layer and/or a second contact element arranged on the second layer .
  • the first and/or second contact element in particular serve to provide a supply current to the optoelectronic device .
  • the first and/or second contact element can for example be of a transparent conductive oxide (TCO ) to allow light being generated within the active region being emitted from the optoelectronic device and/or the first second contact element can when viewed onto the bottom surface , comprise a structure with a central region of the first and/or second layer remaining free of the first contact element and in particular forming a ring . It is however also conceivable that the first and/or second contact element completely cover the respective underlying semiconductor layer .
  • TCO transparent conductive oxide
  • the central region of the active region comprises a lateral dimension of less than the diffusion length of the material system of the active region .
  • the optoelectronic device is configured to have a switching on and/or off time in the range of 0 , 5 ns to 10ns , in particular a switching on and/or off time down to 0 , 1ns .
  • a switching time fast switching frequencies , e . g . in the GHz range , can be realized .
  • the optoelectronic device can be used as a means for optical data communication, in particular short distance communication of less than 10m .
  • the optoelectronic device can in particular be used for data transmission in large data centres and the like , to transmit data over short distances ( ⁇ 10m) for example from CPU to GPU, server to server , and/or rack to rack .
  • the method provides a semiconductor layer stack having a first layer and a second layer .
  • the first layer comprises a first doping type and the second layer comprises a second doping type .
  • An active region is arranged between the first and second layer .
  • the semiconductor layer stack is thereby comprising a material including at least one of phosphide and arsenide and is for example based on an GaAs /AlGaAs material combination .
  • a mesa etching process is conducted to form side surfaces connecting a top and a bottom surface of the semiconductor layer stack and exposing portions of the active region in a circumferential perimeter .
  • said perimeter can have the shape of a circle , a rectangle , or a polygon like a hexagon for example .
  • the semiconductor layer stack is then processed in such a way that a central region with a lateral dimension which is less than one half of a lateral dimension of the semiconductor layer stack is formed and such that a current path from the first layer to the second layer through the active region is limited to that central region .
  • the semiconductor layer stack is processed to realize a current confinement of a current applied to the first and second layer to a central region of at least the active region .
  • This can be achieved by several measures addressed in the following aspects .
  • the different aspects allow for example an optimization of the active region size for high current density/switching speeds while keeping a respective size of the semiconductor layer stack for deheating the heat generated within the optoelectronic device during operation of the same .
  • the improved heat management can thereby have positive effects on the reliability and lifetime of the optoelectronic device .
  • the step of providing a semiconductor layer stack comprises depositing an Al x Ga!_ x As layer arranged between the first layer and the active region and/or between the second layer and the active region .
  • the parameter x is thereby in particular greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 .
  • the Al x Ga!_ x As layer can for example comprise a thickness in the range of 5 nm to 20 nm and/or is optionally doped in the same range as the first and second doped layers of the layer stack . Suitable doping concentrations are known to the skilled person .
  • the step of processing the semiconductor layer stack comprises partially oxidizing the Al x Ga!_ x As layer ( s ) such that the oxidized portion of the partially oxidized Al x Ga!_ x As layer ranges from the side surfaces until the central region and the central portion remains substantially unoxidized .
  • the semiconductor layer stack comprises a partially oxidized Al x Ga!_ x As layer arranged between the first layer and the active region and/or between the second layer and the active region .
  • the oxidized portion of the partially oxidized Al x Ga!_ x As layer ranges from the side surfaces until the central region whereas the central region of the Al x Ga!_ x As layer remains substantially unoxidized .
  • the oxidation of the Al x Ga!_ x As layer can for example be conducted in a wet oven after mesa structuring the semiconductor layer stack .
  • the depth of the oxidation can in thereby in particular be tuned by for example the time of the step of oxidation within the wet oven .
  • the partially oxidized Al x Ga!_ x As layer can be arranged in the blocking area/active region of the semiconductor layer stack on the first layer , on the second layer, or on both layers .
  • the step of processing the semiconductor layer stack comprises implanting ions into at least the active region and in particular the semiconductor layer stack outside the central region forming an ion implanted region outside the central region having a worse conductivity and or higher bandgap than the active region within the central region and in particular the semiconductor layer stack within the central region .
  • the ion implantation can be conducted by means of an ion bombardment of the side surfaces followed by for example a step of annealing such that at least the active region and in particular the semiconductor layer stack outside the central region forms an ion implanted region outside the central region having a worse conductivity and/or larger bandgap than the active region within the central region and in particular the semiconductor layer stack within the central region .
  • the step of processing the semiconductor layer stack comprises intermixing, in particular quantum well intermixing , the active region outside the central region forming a region of the active region with a larger band gap than the active region within the central region .
  • intermixed region outside the central region a current confinement of a current applied to the first and second layer is created, since the intermixed region has an insulating effect and the current therefore only flows through the central region through the active region .
  • the intermixing of the active region can thereby be conducted by any know process known in the art .
  • the step of providing or the step of processing the semiconductor layer stack comprises a structuring and/or selevtive growth of the first and/or the second layer such that the first and/or second layer is limited to the central region .
  • a selective growth of the first and/or the second layer on the active region comprises providing a hardmask of for example SiO 2 or Si 3 N 4 on the active region adj acent to the central region and growing the first and/or the second layer on the active region in the central region .
  • the limitation of the first and or second layer results in a current confinement of a current applied to the first and second layer , since the current only flows through the central region through the active region .
  • the structuring and/or growing of the first and/or second layer can thereby be conducted by any know process known in the art .
  • the method further comprises a step of regrowing at least one regrowth layer on the side surfaces and/or optionally a step of growing a passivation layer on exposed surfaces of the regrowth layer ( s ) and/or on exposed surfaces of the semiconductor layer stack .
  • the method further comprises a step of providing a first contact element on the first layer and/or a bottom contact element on the second layer . The first and/or second contact element can thereby be formed according to aforementioned aspects described for the optoelectronic device .
  • the step of providing the semiconductor layer stack comprises providing a first and a second, in particularly undoped cladding layer directly adj acent to the active region .
  • the semiconductor layer stack comprises in some aspects a first and a second, in particularly undoped cladding layer directly adj acent to the active region .
  • Those layer prevent diffusion of dopants but can also be used as a charge carrier blocking structure .
  • the optoelectronic device such as a p-LED presented herein is suitable for a variety of applications , in which a high switching or current modulation frequency is required .
  • the optoelectronic device according to the proposed principle is used in optical data communication, particularly in the short and medium range with modulation frequencies larger than 1 GHz and particularly larger than 10 GHz .
  • Figures 1A to ID show steps of a method for manufacturing an optoelectronic device in accordance with some aspects of the proposed principle ;
  • Figures 2A to 2D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;
  • Figures 3a to 3D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;
  • Figures 4A to 4D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle ;
  • Figures 5A to 5D show steps of a method for manufacturing a further embodiment of an optoelectronic device in accordance with some aspects of the proposed principle .
  • Figures 1A to ID illustrate steps of a method for manufacturing an optoelectronic device , in particular p-LED 1 in accordance with the proposed principle . These steps are conducted in a similar manner in all the respective embodiments illustrated herein . However , certain variations and deviations from the illustrated steps can be implemented without deviating from the overall scope . In addition, although only vertical optoelectronic devices are illustrated herein, one will recognize that the proposed principle is not restricted to such devices . Rather , the respective contact areas can be arranged on the same side with a via leading through the active region and connecting the desired doped layer .
  • Figure 1A illustrates the epitaxial deposition of a semiconductor layer stack 2 on the respective growth substrate 11 .
  • the growth substrate 11 comprises an n-doped gallium arsenide layer, which acts as wafer substrate , on which the subsequent layers are epitaxially deposited .
  • the n-doped gallium arsenide substrate may comprise a plurality of buffer layers to smooth and flattening its surface , such as to provide a substantially defect free surface .
  • an n-doped aluminum gallium arsenide layer 3 is epitaxially deposited on the surface of the growth substrate as a first semiconductor layer .
  • the first layer 3 can comprise a doping distribution and/or a varying doping concentration based on the required needs .
  • the doping concentration closer to the growth substrate 11 may be larger than further away to improve the charge carrier inj ection into the aluminum gallium arsenide layer 3 .
  • the aluminum content of the first layer 3 may vary and also comprise a respective distribution over the thickness of the first layer 3 .
  • first layer 3 can include one or more sublayers , in which the above-mentioned varying concentrations and distributions of dopants and Al content are implemented .
  • first Al x Gai_ x As layer 12 is arranged, where parameter x is greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 .
  • First Al x Ga!_ x As layer 12 can in particular comprise an Al content such that first Al x Ga!_ x As layer 12 can easily be oxidized .
  • first cladding layer 14 On top of the first Al x Ga!_ x As layer 12 an undoped aluminum gallium arsenide first cladding layer 14 is deposited .
  • the aluminum content of that layer may be similar to the aluminum content of the first layer 3 but can also vary to improve the charge carrier transport diffusion into the active region 5 epitaxially deposited on top of first cladding layer 14 .
  • the thickness of first cladding layer 14 is in the range between 10 nm and 50 nm.
  • the purpose of first cladding layer 14 is to prevent diffusion of dopants from the first layer 3 and the first Al x Ga!_ x As layer 12 respectively into the active region 5 .
  • Active region 5 is deposited thereupon and comprises a pn-j unction or a multi-quantum well structure in this embodiment .
  • the multi-quantum well structure for example includes a plurality of barrier layers and quantum well layers , respectively, whereas the aluminum content for the barrier layers is slightly larger than the aluminum content of the respective quantum well layers . Consequently, a varying band gap in the semiconductor material of active region 5 is provided, trapping the charge carriers between the "valleys" of the bandgap .
  • Active region 5 is covered by another cladding layer 15 of aluminum gallium arsenide similar to the first cladding layer 14 .
  • second Al x Ga!_ x As layer 13 is arranged, where parameter x is greater than 0 . 5 and in particular greater than 0 . 9 and in particular greater than 0 . 97 .
  • Second Al x Ga!_ x As layer 13 can in particular comprise an Al content such that second Al x Ga!_ x As layer 13 can easily be oxidized .
  • a p-doped layer 4 is deposited as a second semiconductor layer . Similar to the n-doped layer 3 , the doping concentration as well as the doping distribution of the p-doped aluminum gallium arsenide layer 4 may vary .
  • both layers 3 and 4 may not only comprise aluminum gallium arsenide sublayers , but can also include one or more gallium arsenide sub-layers or aluminum gallium arsenide sub-layers with varying aluminum content .
  • the purpose of these sublayers is to distribute the inj ected charge carriers across the overall area of the semiconductor layer stack 2 and will provide a continuous and equally distributed diffusion towards the active region .
  • the top surface of the second layer 4 is covered by a highly doped gallium arsenide contact layer 16 .
  • the contact layer 16 provides not only a connection to a conductive metal or a transparent conductive oxide , but also acts as the main emission surface in operation of the device 1 later on .
  • the first and the second Al x Gai_ x As layer 12 and 13 are for example very thin layers containing aluminum gallium arsenide with a high aluminum content introduced between the first and second layer 3 and 4 and the respective cladding layer 14 and 15 or more generally between the first and second layer 3 and 4 and the active region 5 .
  • the aluminum content of the Al x Ga!_ x As layers comprise a very high aluminum content with parameter x larger than 0 . 9 and particularly larger than 0 . 97 .
  • FIG. IB The next step of the proposed method is illustrated in Figure IB .
  • a not shown mas k layer material is deposited on the p-doped gallium arsenide contact layer 16 and subsequently structured to form a central portion of the hard mask layer .
  • the central portion forms a circle , a rectangle , or any other polygon like a hexagon structure .
  • one or more mesa etching steps are performed to provide side surfaces 2 c exposing the facets of active region 5 as well as the first and second layer 3 and 4 , respectively .
  • the results of the mesa etching process is illustrated in Figure IB and can be achieved by several subsequent mesa etching steps .
  • the side surfaces 2c of the semiconductor layer stack 2 and in particular of the active region 5 can in addition for example be cleaned and annealed after the first etching step to remove any plasma damages from the side surfaces 2 c .
  • material of contact layer 16 , the p-doped aluminum gallium arsenide layer 4 , the cladding layers 14 and 15 , first and second Al x Ga!_ x As layer 12 and 13 as well as active region 5 is removed using a plasma etching process or any similar suitable way .
  • the exposed surfaces are cleaned and annealed using NH 3 or other suitable gas . The cleaning reduces the damages and the non- radiative recombination centres after the mesa etching process to obtain more defined side surfaces 2 c, preferably with only a small number of non-radiative recombination centres and thus a defined surface state .
  • the semiconductor layer stack 2 is then processed as shown in Figure 1C .
  • the semiconductor layer stack is therefore exposed to an oxygen containing atmosphere ( shown by the two arrows ) , initiating an oxidation of the aluminum within the first and second Al x Ga!_ x As layer 12 and 13 . Due to the oxygen containing atmosphere and the high Al content of layers 12 and 13 , a portion of the layers 12 and 13 starting from the side surfaces 2c is oxidized resulting in oxidized thin portions of the layers 12 and 13 until a central region 10 of the semiconductor layer stack 2 .
  • the oxidation results in a constrain of the conductivity of the first and second Al x Ga!_ x As layer 12 and 13 to some smaller central portion thereof similar to apertures for the charge carriers , as indicated in Figure ID .
  • the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time for example in addition a defined amount of non-radiative recombination centres can be formed beneath and above the active region 5 as well as on the circumferential perimeter .
  • the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region .
  • top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces are passivated by means of a passivation layer 8 .
  • the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .
  • the method according to the proposed principle follows the latter approach but can be combined with other measures to increase the charge density or the bandgap structure to provide a faster radiative recombination .
  • Figures 2A to 2D illustrate a respective embodiment thereof .
  • the steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 2A and 2B thereby relate to the embodiment shown in Figures 1A and IB but without providing the first and the second Al x Ga!_ x As layer .
  • the semiconductor layer stack 2 is then processed as shown in Figure 2C .
  • a structured mask 9 is provided on the semiconductor layer stack 2 to conduct a quantum well intermixing ( indicated by the vertical arrows ) of the active region 5 in a region between the side surfaces 2 c and the central region 10 .
  • intermixed regions 17 of the active region 5 result having a larger bandgap than the active region within the central region 10 not being quantum well intermixed .
  • the intermixing results in a higher bandgap of the active region 5 outside the central region 10 .
  • the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time a defined amount of non-radiative recombination centres is formed beneath and above the active region 5 as well as on the circumferential perimeter .
  • the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region and increase the amount of non-radiative recombination centres in the intermixed region 17 .
  • top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces 2 c are passivated by means of a passivation layer 8 .
  • the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .
  • Figures 3A to 3D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 .
  • the steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 3A and 3B thereby relate to the embodiment shown in Figures 2A and 2B with the difference of providing an active region with a simple pn-j unction and not a quantum well or multi quantum well layer .
  • This is however understood to be exemplary and can also be in the same way as shown in Figures 2A and 2B .
  • the semiconductor layer stack 2 is then processed as shown in Figure 3C .
  • a structured mask 9 is provided on the semiconductor layer stack 2 to conduct an ion bombardment of the side surfaces 2 c ( indicated by the arrows ) of the semiconductor layer stack 2 in a region between the side surfaces 2 c and the central region 10 .
  • ion implanted regions 18 of semiconductor layer stack 2 result having semi insulating properties and in particular a worse conductivity than the semiconductor layer stack 2 within the central region 10 .
  • the ion bombardment can cause the active region outside the central region 10 having a larger bandgap than the active region 5 within the central region 10 .
  • the ion bombardment results in a worse conductivity of the layers adj acent to the active region 5 as well as a higher bandgap of the active region 5 outside the central region 10 .
  • the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure , while at the same time a defined amount of non-radiative recombination centres is formed beneath and above the active region 5 as well as on the circumferential perimeter .
  • the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region and increase the amount of non-radiative recombination centres in the intermixed region 17 .
  • top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a , 2b of the semiconductor layer stack 2 .
  • the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .
  • Figures 4A to 4D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 .
  • the steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 4A to 4C thereby relate to the embodiment shown in Figures 3A and 3B with the difference that the second layer 4 as well as the contact layer 16 is provided selectively on the active region 5 using a structured mas k 9 only in the central region 10 of the semiconductor layer stack 2 .
  • This step can in this embodiment already be understood as the step, by means of which the charge carrier density within the active region 5 is increased .
  • the semiconductor layer stack 2 is then mesa structured as shown in Figure 4C to receive side surfaces 2 c of the semiconductor layer stack 2 .
  • the selective growth results in current feed into the active region 5 only in the central region 10 .
  • the charge density within the active region 5 inside the central region is significantly increased by the resulting aperture like structure .
  • the rise and fall time of the optoelectronic device can be decreased by changing the charge carrier density within the active region 5 .
  • top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a, 2b of the semiconductor layer stack 2 and the side surfaces 2 c are passivated by means of a passivation layer 8 .
  • the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .
  • Figures 5A to 5D illustrate a further embodiment a current confinement to the central region of an optoelectronic device 1 .
  • the steps of providing a semiconductor layer stack 2 as well as mesa structuring the semiconductor layer stack 2 shown in Figures 5A and 5B thereby relate to the embodiment shown in Figures 3A and 3B with the difference that by means of the mesa structuring using a structured mas k 9 , an already smaller semiconductor layer stack 2 is pixelated with smaller lateral dimensions compared to aforementioned embodiments .
  • the charge carrier density within the active region 5 can be increased compared to a larger sized layer stack 2 with larger lateral dimensions and assuming the same current is applied to the active region 5 .
  • the regrowth layers 6 are provided along the side surfaces 2c of the semiconductor layer stack 2 .
  • the regrowth layers 6 can for example be a structure of alternating layers having different doping types such as for example a pnp or a npn structure covering the side surfaces 2 c of the semiconductor layer stack 2 .
  • Such an embodiment can in particular also be suitable in combination with any of aforementioned aspects for current confinement within the semiconductor layer stack 2 .
  • the regrowth layers 6 thereby act as current confinement structure to guide the current through the active region 5 and preserve the side surfaces 2 c from unwanted effects .
  • top and bottom contact elements 7a, 7b are provided on the top and bottom surface 2a , 2b of the semiconductor layer stack 2 .
  • the bottom contact element 7a is exemplarily arranged on the bottom surface 2a comprises the shape of a ring leaving the central region 10 of the semiconductor layer stack 2 uncovered .
  • p-LED layer stack a top surface b bottom surface c side surface layer layer active region regrowth layer a contact element b contact element passivation layer mas k 0 central region 1 growth substrate 2 Al x Gai_ x As layer 3 Al x Ga!_ x As layer 4 cladding layer 5 cladding layer 6 contact layer 7 intermixed region 8 implanted region

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  • Led Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un µ-LED comprenant un empilement de couches semi-conductrices possédant une première couche de transport de charge d'un premier type de dopage, une seconde couche de transport de charge d'un second type de dopage, et une région active agencée entre les première et seconde couches de transport de charge. L'empilement de couches semi-conductrices comprend une surface inférieure et une surface supérieure ainsi que des surfaces latérales structurées mesa reliant les surfaces supérieure et inférieure et une région centrale ayant une dimension latérale qui est inférieure à la moitié d'une dimension latérale de l'empilement de couches semi-conductrices. En outre, l'empilement de couches semi-conductrices comprend un matériau comprenant au moins l'un parmi le phosphure et l'arséniure et un trajet de courant de la première couche à la seconde couche à travers la région active est limité à la région centrale.
PCT/EP2024/065331 2023-06-08 2024-06-04 Μleds à commutation rapide ou à base d'ingaalas pour communication de données à grande vitesse Ceased WO2024251732A1 (fr)

Priority Applications (2)

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CN202480038034.1A CN121312293A (zh) 2023-06-08 2024-06-04 用于高速数据通信的基于INGAALP或INGAALAS的快速开关μ-LED
DE112024002463.7T DE112024002463T5 (de) 2023-06-08 2024-06-04 SCHNELL SCHALTENDE µLEDS AUF INGAALP- ODER INGAALAS-BASIS FÜR HOCHGESCHWINDIGKEITS-DATENÜBERTRAGUNG

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DE102023115113.4 2023-06-08
DE102023115113 2023-06-08

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DE (1) DE112024002463T5 (fr)
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Citations (4)

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US20050040415A1 (en) * 2001-10-09 2005-02-24 Infinera Corporation Oxygen-doped al-containing current blocking layers in active semiconductor devices in photonic integrated circuits (PICs)
US20070153853A1 (en) * 2005-12-15 2007-07-05 Palo Alto Research Center Incorporated Buried lateral index guided lasers and lasers with lateral current blocking layers
US20130200492A1 (en) * 2010-02-09 2013-08-08 The Centre For Integrated Photonics Limited Opto-electronic device
US20200052158A1 (en) * 2015-12-22 2020-02-13 Apple Inc. Led sidewall processing to mitigate non-radiative recombination

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US20050040415A1 (en) * 2001-10-09 2005-02-24 Infinera Corporation Oxygen-doped al-containing current blocking layers in active semiconductor devices in photonic integrated circuits (PICs)
US20070153853A1 (en) * 2005-12-15 2007-07-05 Palo Alto Research Center Incorporated Buried lateral index guided lasers and lasers with lateral current blocking layers
US20130200492A1 (en) * 2010-02-09 2013-08-08 The Centre For Integrated Photonics Limited Opto-electronic device
US20200052158A1 (en) * 2015-12-22 2020-02-13 Apple Inc. Led sidewall processing to mitigate non-radiative recombination

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Title
LU TINGWEI ET AL: "High-speed visible light communication based on micro-LED: A technology with wide applications in next generation communication", OPTO-ELECTRONIC SCIENCE, vol. 1, no. 12, 29 December 2022 (2022-12-29), pages 220020 - 220020, XP093195927, ISSN: 2097-0382, Retrieved from the Internet <URL:https://www.oejournal.org/data/article/oes/preview/pdf/oes-2022-0020-WuTingzhu.pdf> [retrieved on 20240816], DOI: 10.29026/oes.2022.220020 *

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