WO2024252536A1 - Circuit de détection de signal - Google Patents

Circuit de détection de signal Download PDF

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Publication number
WO2024252536A1
WO2024252536A1 PCT/JP2023/021074 JP2023021074W WO2024252536A1 WO 2024252536 A1 WO2024252536 A1 WO 2024252536A1 JP 2023021074 W JP2023021074 W JP 2023021074W WO 2024252536 A1 WO2024252536 A1 WO 2024252536A1
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WO
WIPO (PCT)
Prior art keywords
signal
unit
frequency
calculation unit
detection circuit
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PCT/JP2023/021074
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English (en)
Japanese (ja)
Inventor
孝俊 赤松
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2024564630A priority Critical patent/JP7618116B1/ja
Priority to PCT/JP2023/021074 priority patent/WO2024252536A1/fr
Publication of WO2024252536A1 publication Critical patent/WO2024252536A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • This disclosure relates to a signal detection circuit.
  • Patent Document 1 requires information on both the I and Q signals to calculate the signal power, which requires a lot of processing such as multiplication and root calculations, and has the problem that the circuit size of the digital circuit tends to become large.
  • the present disclosure aims to solve the above problem by providing a signal detection circuit that can prevent the circuit size from becoming larger than before.
  • the signal detection circuit disclosed herein is characterized by comprising a frequency shift unit that shifts the frequency of an input signal from an analog-digital converter that converts an analog signal into a digital signal, and outputs the input signal so that the center frequency of the band of the input signal becomes the Nyquist frequency; a moving sum calculation unit that calculates the sum over a fixed period of time of the absolute values of the signal output from the frequency shift unit; and a signal detection unit that detects a specific signal contained in the input signal using the calculation result by the moving sum calculation unit.
  • signal detection is possible through processing using only either the I signal or the Q signal, making it possible to prevent the circuit size from becoming larger than in the past.
  • FIG. 1 is a block diagram showing a configuration of a signal detection circuit according to a first embodiment.
  • 4 is a diagram showing a frequency spectrum of a signal output from an A/D converter of the signal detection circuit according to the first embodiment.
  • 4 is a diagram showing a frequency spectrum of a signal output from a mixer of the signal detection circuit according to the first embodiment;
  • 4 is a diagram showing frequency spectra of an I signal and a Q signal output from a downsampling unit of the signal detection circuit according to the first embodiment;
  • 4 is a diagram showing a frequency spectrum of an I signal output from a downsampling unit of the signal detection circuit according to the first embodiment;
  • 4 is a diagram showing a time waveform of a signal output from an absolute value calculation unit of the signal detection circuit according to the first embodiment.
  • FIG. 4 is a diagram showing a time waveform of a signal output from a sum calculation unit of the signal detection circuit according to the first embodiment;
  • FIG. 4 is a diagram showing a time waveform of a signal output from a threshold value determination unit of the signal detection circuit according to the first embodiment;
  • Fig. 1 is a block diagram showing a configuration of a signal detection circuit 10 according to a first embodiment.
  • the signal detection circuit 10 according to the first embodiment includes an A/D converter 1, a Nyquist shift numerically controlled oscillator 2, a mixer 3, a frequency filter 4, a downsampling unit 5, an absolute value calculation unit 6, a delay holding unit 7, a sum calculation unit 8, and a threshold determination unit 9.
  • the A/D converter 1 which acts as an analog-to-digital converter, converts the input analog signal 101 into a digital signal 102 by sampling it at a specific sampling frequency that is set in advance.
  • the A/D converter 1 outputs the signal 102 to the mixer 3.
  • the Nyquist shift numerically controlled oscillator 2 which serves as a signal generator, generates a signal 201, which is a local signal for shifting the center frequency of the band of the signal 102 output from the A/D converter 1 to the Nyquist frequency of the signal sampled by the A/D converter 1.
  • the Nyquist shift numerically controlled oscillator 2 outputs the generated signal 201 to the mixer 3.
  • the mixer 3 shifts the frequency of the signal 102 by multiplying the signal 102, which is the input signal from the A/D converter 1, by the signal 201 output from the Nyquist shift numerical control oscillator 2.
  • the mixer 3 outputs the frequency-shifted signal 301 to the frequency filter 4.
  • the frequency filter 4 extracts only the signal band of the analog signal 101, which is a specific signal band, from the signal 301 output from the mixer 3.
  • the frequency filter 4 outputs the extracted signal 401.
  • the downsampling unit 5 performs sample decimation on the signal 401 output from the frequency filter 4 in accordance with the sampling frequency. In other words, the downsampling unit 5 performs downsampling on the signal of a specific band extracted by the frequency filter 4.
  • the downsampling unit 5 outputs the decimated signal 501 to the absolute value calculation unit 6.
  • the downsampling value according to the first embodiment is a value determined by the subsequent operating frequency, and any value can be adopted according to the principles of the configuration according to the present disclosure.
  • the frequency shift unit in the first embodiment is composed of the Nyquist shift numerically controlled oscillator 2, the mixer 3, the frequency filter 4, and the downsampling unit 5.
  • the absolute value calculation unit 6 calculates the absolute value of the I signal (I component) of the signal 501 output from the downsampling unit 5.
  • the absolute value calculation unit 6 may be configured to calculate the absolute value of either the I signal or the Q signal (Q component) of the signal 501 output from the downsampling unit 5.
  • the absolute value calculation unit 6 outputs the calculation result to the delay holding unit 7 as the signal 601.
  • the delay holding unit 7 holds samples (a fixed number of samples) of the signal 601 output from the absolute value calculation unit 6 for a fixed time.
  • the delay holding unit 7 outputs the signal of the samples held for the fixed time as the signal 701 to the sum calculation unit 8. Note that the time for which the delay holding unit according to the first embodiment holds the samples can be any time.
  • the sum calculation unit 8 calculates the sum of the signals 701 output from the delay holding unit 7.
  • the sum calculation unit 8 outputs the calculated signal 801 to the threshold determination unit 9.
  • the absolute value calculation unit 6, the delay holding unit 7, and the sum calculation unit 8 constitute the moving sum calculation unit in the first embodiment.
  • the threshold determination unit 9 which serves as a signal detection unit, compares the signal 801 output from the sum calculation unit 8 with a preset threshold, and determines whether or not the signal to be detected is included in the analog signal 101 based on the magnitude relationship between the signal 801 and the threshold. In other words, the signal 801 output from the sum calculation unit 8 is used to detect a specific signal included in the analog signal 101.
  • the threshold determination unit 9 outputs a signal 901 that is the result of the determination.
  • the signal detection circuit 10 will be described in detail with reference to Fig. 2 to Fig. 8.
  • the signal to be detected is a chirp signal with a frequency band of ⁇ f.
  • the downsampling value by the downsampling unit 5 is 1/2.
  • An input analog signal 101 is sampled by the A/D converter 1 at a preset sampling frequency fS , and converted into a digital signal 102.
  • FIG. 2 is a diagram showing the frequency spectrum of the signal 102 output from the A/D converter 1 of the signal detection circuit 10 according to the first embodiment.
  • the signal 102 output from the A/D converter 1 and a signal 201, which is an I signal output from the Nyquist shift numerically controlled oscillator 2 are multiplied by the mixer 3 and output as a signal 301.
  • the Nyquist shift numerically controlled oscillator 2 according to the first embodiment shifts the center frequency of the band of the signal 102 to f S /4.
  • Fig. 3 is a diagram showing the frequency spectrum of the signal 301 output from the mixer 3 of the signal detection circuit 10 according to the first embodiment. After the desired signal is extracted from the signal 301 output from the mixer 3 by the frequency filter 4, the signal is downsampled by the downsampling unit 5 and output as the signal 501.
  • FIG. 4 is a diagram showing the frequency spectrum of the signal 501 output from the downsampling unit 5 of the signal detection circuit 10 according to the first embodiment.
  • the downsampling unit 5 according to the first embodiment performs a process of thinning the signal 401 output from the frequency filter 4 by 1/2 (a process of thinning out one point for every two points). As a result, the Nyquist band becomes 1/2.
  • FIG. 5 is a diagram showing the frequency spectrum of the I component of the signal 501 output from the downsampling unit 5 of the signal detection circuit 10 according to the first embodiment.
  • the downsampling unit 5 extracts only the I component (or Q component) as the output signal 501.
  • the signal 501 output from the downsampling unit 5 is input to the absolute value calculation unit 6.
  • the absolute value calculation unit 6 calculates the absolute value of the signal 501 and outputs the calculation result, signal 601.
  • FIG. 6 is a diagram showing the time waveform of signal 601 output from absolute value calculation unit 6 of signal detection circuit 10 according to embodiment 1.
  • Signal 601 output from absolute value calculation unit 6 is held for a certain period of time A by delay holding unit 7 before being output.
  • Sum calculation unit 8 calculates the sum of the values of signal 701 output from delay holding unit 7, and outputs the calculation result as signal 801.
  • FIG. 7 is a diagram showing the time waveform of signal 801 output from sum calculation unit 8 of signal detection circuit 10 according to embodiment 1.
  • Threshold determination unit 9 performs threshold determination using the value of signal 801 output from sum calculation unit 8.
  • Threshold determination unit 9 outputs, as an output signal (signal 901 which is the result of threshold determination), 1 if the value of signal 801 exceeds the threshold, and 0 if it is below the threshold.
  • signal 901 which is the result of threshold determination
  • even for just the I signal always exceeds the threshold (having a certain magnitude), making it detectable as a signal.
  • FIG. 8 is a diagram showing the time waveform of a signal 901 output from the threshold determination unit 9 of the signal detection circuit 10 according to the first embodiment.
  • FIG. 8 shows a case where the value of the signal 801 exceeds the threshold, in other words, a case where it is always determined that a signal is present.
  • the signal to be detected is a very slow signal ( ⁇ fS ) when it is near the baseband.
  • ⁇ fS very slow signal
  • the signal detection circuit 10 is capable of detecting a signal by processing using only either the I signal or the Q signal, without using the band near the baseband, whereas the conventional technology requires both I and Q signal components. This also makes it possible to reduce the number of multiplication circuits compared to the conventional technology, thereby preventing the circuit size from increasing. Furthermore, by preventing the circuit size from increasing, the circuit delay can be reduced.
  • the new signal detection circuit disclosed herein can be used, for example, to detect a specific signal contained in an analog signal.
  • A/D converter analog-to-digital converter
  • Numerical control oscillator for Nyquist shift frequency shift section, signal generation section
  • Mixer frequency shift section
  • Frequency filter frequency shift section
  • Downsampling section frequency shift section
  • Absolute value calculation section moving sum calculation section
  • Delay holding section moving sum calculation section
  • Sum calculation section moving sum calculation section
  • Threshold determination section signal detection section

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

La présente invention porte sur un circuit de détection de signal (10) qui est équipé : d'unités de décalage de fréquence (2, 3, 4, 5) qui soumettent un signal d'entrée provenant d'un convertisseur analogique-numérique (1) qui convertit un signal analogique en un signal numérique à un décalage de fréquence d'une manière telle que la fréquence centrale de la bande devienne la fréquence de Nyquist, et délivre celle-ci ; des unités de calcul de somme de mouvement (6, 7, 8) qui calculent la somme des valeurs absolues des signaux émis par les unités de décalage de fréquence pendant une certaine période de temps ; et une unité de détection de signal (9) qui détecte un signal spécifique inclus dans le signal d'entrée à l'aide des résultats de calcul provenant de l'unité de calcul de somme de mouvement.
PCT/JP2023/021074 2023-06-07 2023-06-07 Circuit de détection de signal Pending WO2024252536A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2024564630A JP7618116B1 (ja) 2023-06-07 2023-06-07 信号検出回路
PCT/JP2023/021074 WO2024252536A1 (fr) 2023-06-07 2023-06-07 Circuit de détection de signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/021074 WO2024252536A1 (fr) 2023-06-07 2023-06-07 Circuit de détection de signal

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WO2024252536A1 true WO2024252536A1 (fr) 2024-12-12

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193843U (fr) * 1987-12-14 1989-06-20
JP2008022355A (ja) * 2006-07-13 2008-01-31 Pioneer Electronic Corp 信号検出装置及び信号検出方法
JP2009517969A (ja) * 2005-12-01 2009-04-30 トムソン ライセンシング 受信機において周波数オフセットを判別する方法および装置
WO2012014876A1 (fr) * 2010-07-27 2012-02-02 日本電気株式会社 Dispositif de détection de signal, son procédé de commande, programme, et dispositif de communication sans fil

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193843U (fr) * 1987-12-14 1989-06-20
JP2009517969A (ja) * 2005-12-01 2009-04-30 トムソン ライセンシング 受信機において周波数オフセットを判別する方法および装置
JP2008022355A (ja) * 2006-07-13 2008-01-31 Pioneer Electronic Corp 信号検出装置及び信号検出方法
WO2012014876A1 (fr) * 2010-07-27 2012-02-02 日本電気株式会社 Dispositif de détection de signal, son procédé de commande, programme, et dispositif de communication sans fil

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JP7618116B1 (ja) 2025-01-20

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