WO2024252792A1 - Composant électronique céramique multicouche et son procédé de production - Google Patents

Composant électronique céramique multicouche et son procédé de production Download PDF

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Publication number
WO2024252792A1
WO2024252792A1 PCT/JP2024/014991 JP2024014991W WO2024252792A1 WO 2024252792 A1 WO2024252792 A1 WO 2024252792A1 JP 2024014991 W JP2024014991 W JP 2024014991W WO 2024252792 A1 WO2024252792 A1 WO 2024252792A1
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internal electrode
layer
multilayer ceramic
electronic component
surface roughness
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Japanese (ja)
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村井稚明
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • the present invention relates to a multilayer ceramic electronic component and a manufacturing method thereof.
  • Layered ceramic electronic components such as multilayer ceramic capacitors are used in electrical equipment (see, for example, Patent Documents 1 and 2).
  • the present invention has been developed in consideration of the above problems, and aims to provide a multilayer ceramic electronic component that can improve the adhesion of the insulator, and a method for manufacturing the same.
  • the multilayer ceramic electronic component according to the present invention comprises a plurality of dielectric layers, a plurality of internal electrode layers that face each other in a first direction via the plurality of dielectric layers, have one end drawn out in a second direction perpendicular to the first direction, and have an end provided inside the ends of the plurality of dielectric layers in a third direction perpendicular to the first direction and the second direction, and an insulator layer provided beyond the end in the third direction of at least one of the plurality of internal electrode layers, wherein a first surface roughness at the interface between the insulator layer and the dielectric layer adjacent in the first direction is greater than a second surface roughness at the interface between the insulator layer and the dielectric layer adjacent in the first direction of the internal electrode layer adjacent in the third direction.
  • the first surface roughness may be three times or more the second surface roughness.
  • the first surface roughness expressed as an arithmetic mean roughness Ra, may be 0.2 ⁇ m or more and 5.0 ⁇ m or less.
  • the first surface roughness expressed as a maximum height difference Rz, may be 0.8 ⁇ m or more and 10.0 ⁇ m or less.
  • the dimension of the insulator layer in the third direction may be 6.9 times or more and 27.2 times or less the thickness of the internal electrode layer adjacent to the insulator layer.
  • the insulating layer may be a resin.
  • the insulating layer may be acrylic, epoxy, polyimide or silicone.
  • the laminated ceramic electronic component may have an external electrode that is provided to cover and electrically connect to one end of the plurality of internal electrode layers.
  • the method for manufacturing a multilayer ceramic electronic component according to the present invention includes the steps of forming an internal electrode pattern on a ceramic green sheet, stacking the ceramic green sheets on which the internal electrode pattern is formed to obtain a laminate, forming a dielectric layer from the ceramic green sheets by firing the laminate and forming an internal electrode layer from the internal electrode pattern to obtain an element body, etching the ends of the internal electrode layer in the element body to increase the surface roughness of the dielectric layer at the interface between the ends and the dielectric layer, and forming an insulating layer on the ends.
  • nitric acid with added hydrogen peroxide may be used in the step of etching the ends of the internal electrode layers.
  • the surface roughness of the interface between the end and the dielectric layer may be three times or more the surface roughness of the interface between the internal electrode layer having the end and the dielectric layer.
  • the manufacturing method for the multilayer ceramic electronic component may include a step of forming external electrodes on the body.
  • a vacuum deposition method may be used.
  • the present invention provides a multilayer ceramic electronic component that can improve the adhesion of the insulator, and a method for manufacturing the same.
  • FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor.
  • 2 is a cross-sectional view taken along line AA in FIG. 1.
  • 2 is a cross-sectional view taken along line BB in FIG. 1.
  • FIG. 4 is an enlarged view of a YZ cross section of a side margin.
  • FIG. 5 is a further enlarged view of the YZ cross section of FIG. 4.
  • FIG. 5 is a further enlarged view of the YZ cross section of FIG. 4.
  • 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor.
  • FIG. 2 is a diagram illustrating a laminate;
  • 1 is a diagram illustrating an etching process.
  • FIG. (a) and (b) are traces of SEM photographs.
  • FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1.
  • FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1.
  • the multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the element body 10. Of the four faces of the element body 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces.
  • the external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the element body 10. However, the external electrodes 20a, 20b are spaced apart from each other.
  • the Z-axis direction (first direction) is the stacking direction, and is the direction in which the internal electrode layers face each other.
  • the X-axis direction (second direction) is the length direction of the element body 10, the direction in which the two end faces of the element body 10 face each other, and the direction in which the external electrodes 20a and 20b face each other.
  • the Y-axis direction (third direction) is the width direction of the internal electrode layers, and is the direction in which the two side faces other than the two end faces of the four side faces of the element body 10 face each other.
  • the X-axis direction, Y-axis direction, and Z-axis direction are mutually perpendicular.
  • the element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately laminated. One end of each internal electrode layer 12 is alternately drawn out to the end face of the element body 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are laminated via the internal electrode layers 12.
  • the internal electrode layer 12 is arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered with the cover layer 13.
  • the cover layer 13 is mainly composed of a ceramic material.
  • the cover layer 13 may have the same composition as the dielectric layer 11 or may have a different composition.
  • the size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, and 0.2 mm high, or 0.6 mm long, 0.3 mm wide, and 0.3 mm high, or 1.0 mm long, 0.5 mm wide, and 0.5 mm high, or 3.2 mm long, 1.6 mm wide, and 1.6 mm high, or 4.5 mm long, 3.2 mm wide, and 2.5 mm high, but is not limited to these sizes.
  • the internal electrode layers 12 are mainly composed of base metals such as nickel (Ni), copper (Cu), and tin (Sn).
  • Noble metals such as platinum (Pt), palladium (Pd), silver (Ag), and gold (Au), or alloys containing these metals, may also be used as the internal electrode layers 12.
  • the average thickness per layer of the internal electrode layers 12 in the Z-axis direction is, for example, 1.5 ⁇ m or less, 1.0 ⁇ m or less, or 0.7 ⁇ m or less.
  • the thickness of each internal electrode layer 12 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 different points, and deriving the average value of each measurement point.
  • the dielectric layer 11 has a main phase of a ceramic material having a perovskite structure represented by the general formula ABO 3.
  • the perovskite structure includes ABO 3- ⁇ , which is not a stoichiometric composition.
  • the ceramic material can be selected from at least one of barium titanate (BaTiO 3 ), calcium zirconate (CaZrO 3 ), calcium titanate (CaTiO 3 ), strontium titanate (SrTiO 3 ), magnesium titanate (MgTiO 3 ), and Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ z ⁇ 1) that forms a perovskite structure.
  • Ba 1-x-y Ca x Sr y Ti 1-z Zr z O 3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate, etc.
  • the dielectric layer 11 contains 90 at % or more of the main component ceramic.
  • the thickness of the dielectric layer 11 is, for example, 5.0 ⁇ m or less, 3.0 ⁇ m or less, or 1.0 ⁇ m or less.
  • the thickness of the dielectric layer 11 can be measured by observing the cross section of the multilayer ceramic capacitor 100 with a SEM (scanning electron microscope), measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value of all the measurement points.
  • the dielectric layer 11 may contain additives.
  • additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
  • Zr zirconium
  • Hf hafnium
  • Mg manganese
  • Mo molybden
  • the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region that generates electrical capacitance in the multilayer ceramic capacitor 100. Therefore, this region that generates electrical capacitance is referred to as the capacitance section 14.
  • the capacitance section 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.
  • the region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b being interposed therebetween is called the end margin 15.
  • the region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a being interposed therebetween is also an end margin 15.
  • the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode being interposed therebetween.
  • the end margin 15 is a region that does not generate electrical capacitance.
  • the side margin 16 is a region provided to cover the ends (ends in the Y-axis direction) of two side surfaces of the dielectric layer 11 and the internal electrode layer 12.
  • the side margin 16 is a region provided outside the capacitance section 14 in the Y-axis direction.
  • the side margin 16 is also a region that does not generate electrical capacitance.
  • FIG. 4 is an enlarged view of the YZ cross section of the side margin 16.
  • the end of the internal electrode layer 12 is located inside the end of the dielectric layer 11. That is, in the Y-axis direction, the outer end of the internal electrode layer 12 is located inside the outer end of the dielectric layer 11.
  • the insulator layer 17 is located beyond the end of the internal electrode layer 12 in the Y-axis direction. Therefore, the side margin 16 has a structure in which the dielectric layer 11 and the insulator layer 17 are alternately stacked in the stacking direction of the dielectric layer 11 and the internal electrode layer 12 in the capacitance section 14.
  • Each dielectric layer 11 of the capacitance section 14 and each dielectric layer 11 of the side margin 16 are continuous layers.
  • FIG. 5 is a further enlarged view of the YZ cross section of FIG. 4, showing the details of the shapes of the dielectric layer 11, the internal electrode layer 12, and the insulator layer 17. Hatching has been omitted in FIG. 5.
  • the upper and lower surfaces of the insulator layer 17, which correspond to the interface with the adjacent dielectric layer 11 in the Z-axis direction, have irregularities.
  • the upper and lower surfaces of the internal electrode layer 12, which is adjacent to the insulator layer 17 in the Y-axis direction, which correspond to the interface with the adjacent dielectric layer 11 in the Z-axis direction, may or may not have irregularities on the surface.
  • the first surface roughness on the upper and lower surfaces of the insulator layer 17 is greater than the second surface roughness on the upper and lower surfaces of the internal electrode layer 12 adjacent to the insulator layer 17 in the Y-axis direction.
  • the first surface roughness and the second surface roughness are surface roughnesses measured by the same measurement method. Hatching has been omitted in FIG. 6.
  • the ends of the internal electrode layer 12 in the Y-axis direction are covered by the insulator layer 17, which can suppress the occurrence of short circuit defects. Furthermore, since the first surface roughness is greater than the second surface roughness, the contact area between the insulator layer 17 and the dielectric layer 11 is increased, improving adhesion.
  • the first surface roughness is large.
  • the first surface roughness is preferably at least three times the second surface roughness, more preferably at least five times, and even more preferably at least ten times.
  • the Ra arithmetic roughness (total area of unevenness/length of measurement point) specified in the JIS standard may be used, or the Rz maximum height difference (height between the peak top and bottom of the unevenness) specified in the JIS standard may be used.
  • the measurement range of the first surface roughness is a range of 1 ⁇ m in the Y-axis direction on the upper and lower surfaces of the insulator layer 17.
  • the measurement range of the second surface roughness is a range of 1 ⁇ m in the Y-axis direction on the upper and lower surfaces of the internal electrode layer 12. If there is a difference in the first surface roughness between the upper and lower surfaces of the insulator layer 17, the larger of the two is used as the first surface roughness. If there is a difference in the second surface roughness between the upper and lower surfaces of the internal electrode layer 12, the larger of the two is used as the second surface roughness.
  • the first surface roughness is expressed as the arithmetic mean roughness Ra
  • the arithmetic mean roughness Ra is preferably 0.2 ⁇ m or more, more preferably 0.3 ⁇ m or more, and even more preferably 0.4 ⁇ m or more.
  • the maximum height difference Rz is preferably 0.8 ⁇ m or more, more preferably 1.0 ⁇ m or more, and even more preferably 1.2 ⁇ m or more.
  • the first surface roughness is expressed as the arithmetic mean roughness Ra
  • the arithmetic mean roughness Ra is preferably 5 ⁇ m or less, more preferably 2 ⁇ m or less, and even more preferably 1 ⁇ m or less.
  • the maximum height difference Rz is preferably 10.0 ⁇ m or less, more preferably 5.0 ⁇ m or less, and even more preferably 3.0 ⁇ m or less.
  • the dimension of the insulator layer 17 in the Y-axis direction is preferably 6.9 times or more, more preferably 10 times or more, and even more preferably 20 times or more, the thickness of the internal electrode layer 12 adjacent to the insulator layer 17 in the Y-axis direction.
  • the dimension of the insulator layer 17 in the Y-axis direction can be obtained by measuring from the end of the insulator layer 17 on the internal electrode layer 12 side (the outermost position if the end is inclined) to the outer end of the insulator layer 17 (to the point closest to the internal electrode layer 12 if the end is inclined).
  • the dimension of the insulator layer 17 in the Y-axis direction is preferably 27.2 times or less the thickness of the internal electrode layer 12 adjacent to the insulator layer 17 in the Y-axis direction, more preferably 15 times or less, and even more preferably 10 times or less.
  • the insulator layer 17 is not particularly limited as long as it is an insulator.
  • resins such as acrylic, epoxy, polyimide, and silicone can be used as the insulator layer 17.
  • glass, ceramics, etc. can be used as the insulator layer 17.
  • a process of firing the ceramic powder is required, but when a resin is used as the insulator layer 17, the firing process is not necessary. Therefore, when a resin is used as the insulator layer 17, the process can be simplified. Furthermore, if the firing process can be eliminated, the effect of volume change during firing can be avoided, and the occurrence of voids can be suppressed. This allows the ends of the internal electrode layer 12 in the Y-axis direction to be sufficiently covered, suppressing the intrusion of moisture. Furthermore, by using resin, which is a ductile material, as the insulator layer 17, cracks during handling of the multilayer ceramic capacitor 100 can be suppressed.
  • Figure 7 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.
  • a dielectric material for forming the dielectric layer 11 is prepared.
  • the A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles.
  • barium titanate is a tetragonal compound having a perovskite structure and exhibits a high relative dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate.
  • additive compounds include oxides of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, rare earth elements (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, and ytterbium), oxides containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.
  • a compound containing an additive compound is wet mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material.
  • the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.
  • a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed.
  • the obtained slurry is used to coat a ceramic green sheet 51 on a substrate by, for example, a die coater method or a doctor blade method, and then dried.
  • the substrate is, for example, a polyethylene terephthalate (PET) film.
  • PET polyethylene terephthalate
  • a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the ceramic green sheet 51 by screen printing, gravure printing, or the like, to arrange an internal electrode pattern 52 for an internal electrode layer.
  • the conductive paste contains nickel and ceramic particles as a co-material.
  • the main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11.
  • a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder are added to the dielectric pattern material obtained in the raw powder preparation process, and the mixture is kneaded in a roll mill to obtain a dielectric pattern paste for the reverse pattern layer.
  • the lamination units are stacked so that the internal electrode layers 12 and the dielectric layers 11 are alternated.
  • the number of layers of the internal electrode pattern 52 is set to 100 to 500.
  • a predetermined number of cover sheets 53 (for example, 2 to 10 layers) are laminated on the top and bottom of the laminate in which the lamination units are stacked, and are thermocompression bonded.
  • Fig. 8 is a diagram showing an example of the laminate.
  • the upper left diagram is a bird's-eye view from above
  • the upper right diagram is a cross-sectional view from the side
  • the lower left diagram is a cross-sectional view from below.
  • the ceramic green sheet 51 and the internal electrode pattern 52 are visible through the transparent film. A hatched pattern is applied to the internal electrode pattern 52.
  • the ceramic laminate thus obtained is subjected to a binder removal process in a N2 atmosphere, after which a metal paste that will become the underlayer of the external electrodes 20a, 20b is applied by dipping, and the laminate is fired for 5 minutes to 10 hours in a reducing atmosphere with an oxygen partial pressure of 10-5 to 10-8 atm and a temperature range of 950°C to 1200°C.
  • the dielectric layer 11 is obtained from the ceramic green sheet 51
  • the internal electrode layer 12 is obtained from the internal electrode pattern 52
  • the cover layer 13 is obtained from the cover sheet 53.
  • the sintered body In order to return oxygen to the barium titanate, which is the partially reduced main phase of the dielectric layer 11 sintered in a reducing atmosphere, the sintered body may be heat-treated in a mixed gas of N2 and water vapor at about 1000°C or in the air at 500°C to 700°C, to a degree that does not oxidize the internal electrode layer 12. This process is called a reoxidation process.
  • FIG. 9 the sintered body is cut along the dashed lines in Fig. 8.
  • the upper left figure is a top view
  • the upper right figure is a cross-sectional view from the side
  • the lower left figure is a cross-sectional view from below.
  • a mesh pattern is applied to the internal electrode layer 12.
  • both ends of the sintered body in the Y-axis direction are etched using acid.
  • both ends of each internal electrode layer 12 in the Y-axis direction are removed by etching.
  • unevenness can be formed on the surface of the dielectric layer 11 at the places removed by the etching.
  • the etching solution is not particularly limited, but for example, nitric acid of 2 mol/L can be used.
  • the etching rate may be improved by adding hydrogen peroxide to the etching solution. By improving the etching rate, the unevenness on the surface of the dielectric layer 11 can be increased. Note that hatching is omitted in FIG. 10.
  • the material of the insulator layer 17 is filled into the portion removed by etching to form the insulator layer 17.
  • the insulator layer 17 is made of resin
  • the insulator layer 17 is formed by filling the portion removed by etching with resin.
  • FIG. 11 Cutting is performed along the dashed lines, thereby obtaining each element body 10.
  • the upper left diagram is a top view
  • the upper right diagram is a cross-sectional view from the side
  • the lower left diagram is a cross-sectional view from below.
  • a mesh pattern is applied to the internal electrode layer 12.
  • the external electrodes 20a, 20b are formed on both end surfaces in the X-axis direction of the element body 10 by a vacuum film forming method such as sputtering. Then, a plating layer is formed on the external electrodes 20a, 20b by a plating process. The above steps complete the multilayer ceramic capacitor 100.
  • the external electrodes 20a, 20b are formed by a vacuum film-forming method, the external electrodes 20a, 20b do not contain ceramic components. .
  • both ends of the internal electrode layer 12 in the Y-axis direction are removed by etching, and unevenness can be formed on the surface of the dielectric layer 11 in the removed area.
  • the surface roughness of the upper and lower surfaces of the insulator layer 17 becomes greater than the surface roughness of the upper and lower surfaces of the internal electrode layer 12 adjacent to the insulator layer 17 in the Y-axis direction. This increases the contact area between the insulator layer 17 and the dielectric layer 11, improving adhesion.
  • stretching occurs in the part in contact with the dicer when cutting before firing, by cutting after firing as in this embodiment, it is possible to suppress the stretching of the ends of the internal electrode layer 12 during cutting. This makes it possible to suppress the occurrence of short circuit defects.
  • the etching conditions such as the components of the etching solution and the etching time
  • the surface roughness of the interface between the end and the dielectric layer 11 can be made three times or more the surface roughness of the interface between the internal electrode layer 12 having the end and the dielectric layer 11.
  • a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited to this.
  • other multilayer ceramic electronic components such as varistors and thermistors may also be used.
  • a multilayer ceramic capacitor was produced according to the manufacturing method of the above embodiment.
  • Barium titanate powder was wet mixed with an organic solvent, a binder was added, and the resulting slurry was applied to a ceramic green sheet by the doctor blade method and dried.
  • a Ni-containing conductive paste film was screen-printed in a predetermined pattern on the ceramic green sheet to form an internal electrode pattern.
  • the ceramic green sheets were then stacked, pressed, and fired to obtain a sintered body, which was then cut as described in Figure 9. Both ends of the cut sintered body in the Y-axis direction were then etched with 2 mol/L nitric acid. The parts removed by etching were then filled with resin to form an insulator layer.
  • Figure 12(a) is a diagram of a trace of the YZ cross section of the insulator layer portion.
  • Figure 12(b) is a diagram of a trace of the YZ cross section of the internal electrode layer portion adjacent to the insulator layer.
  • the arithmetic mean roughness Ra of the upper surface of the insulator layer was 0.308 ⁇ m, and the arithmetic mean roughness Ra of the lower surface was 0.284 ⁇ m.
  • the arithmetic mean roughness Ra of the upper surface of the internal electrode layer was 0.093 ⁇ m, and the arithmetic mean roughness Ra of the lower surface was 0.094 ⁇ m.
  • the maximum height difference Rz of the upper surface of the insulator layer was 1.406 ⁇ m, and the maximum height difference Rz of the lower surface was 0.973 ⁇ m.
  • the maximum height difference Rz of the upper surface of the internal electrode layer was 0.540 ⁇ m, and the maximum height difference Rz of the lower surface was 0.486 ⁇ m. In this way, it was confirmed that by etching the ends of the internal electrode layers, the first surface roughness becomes greater than the second surface roughness.

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Abstract

L'invention concerne un composant électronique en céramique multicouche qui comprend : une pluralité de couches diélectriques (11); une pluralité de couches d'électrode internes (12) qui sont opposées les unes aux autres dans une première direction à travers la pluralité de couches diélectriques (11), et présentent chacune une extrémité s'étendant dans une deuxième direction orthogonale à la première direction, et ayant des parties d'extrémité disposées plus vers l'intérieur que des parties d'extrémité de la pluralité de couches diélectriques (11) dans une troisième direction orthogonale à la première direction et à la seconde direction; et une couche isolante (17) disposée au niveau de la pointe d'une partie d'extrémité dans la troisième direction d'au moins l'une de la pluralité de couches d'électrode interne (12). Une première rugosité de surface au niveau de l'interface entre des couches diélectriques (11) adjacentes dans la première direction de la couche isolante (17) est supérieure à une seconde rugosité de surface au niveau de l'interface entre des couches diélectriques (11) adjacentes dans la première direction de la couche d'électrode interne (12) à laquelle la couche isolante (17) est adjacente dans la troisième direction.　
PCT/JP2024/014991 2023-06-09 2024-04-15 Composant électronique céramique multicouche et son procédé de production Pending WO2024252792A1 (fr)

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WO2004075216A1 (fr) * 2003-02-21 2004-09-02 Murata Manufacturing Co., Ltd. Compose electronique ceramique de type lamine et procede de production associe
JP2019102577A (ja) * 2017-11-30 2019-06-24 凸版印刷株式会社 キャパシタ内蔵ガラス基板、キャパシタ内蔵回路基板及びキャパシタ内蔵ガラス基板の製造方法
JP2020072267A (ja) * 2018-10-31 2020-05-07 Tdk株式会社 薄膜キャパシタ及びその製造方法並びに電子部品内蔵基板

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