WO2024252795A1 - Silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate - Google Patents

Silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate Download PDF

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WO2024252795A1
WO2024252795A1 PCT/JP2024/015148 JP2024015148W WO2024252795A1 WO 2024252795 A1 WO2024252795 A1 WO 2024252795A1 JP 2024015148 W JP2024015148 W JP 2024015148W WO 2024252795 A1 WO2024252795 A1 WO 2024252795A1
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silicon carbide
region
single crystal
substrate
impurity concentration
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French (fr)
Japanese (ja)
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光亮 内田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to JP2025525972A priority Critical patent/JPWO2024252795A1/ja
Priority to DE112024002456.4T priority patent/DE112024002456T5/en
Priority to CN202480025712.0A priority patent/CN121014273A/en
Publication of WO2024252795A1 publication Critical patent/WO2024252795A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies

Definitions

  • This disclosure relates to a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide substrate.
  • a silicon carbide epitaxial substrate in which a recombination-promoting layer (silicon carbide epitaxial layer) having a higher impurity concentration than the silicon carbide single crystal substrate is provided between the silicon carbide single crystal substrate and the silicon carbide epitaxial layer.
  • the provision of the silicon carbide epitaxial layer suppresses the occurrence of stacking faults due to basal plane dislocations contained in the silicon carbide single crystal substrate.
  • the silicon carbide substrate of the present disclosure comprises a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region.
  • FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment.
  • FIG. 2 is a diagram showing a silicon carbide substrate according to a first example of the embodiment.
  • FIG. 3 is a diagram showing a silicon carbide substrate according to a second example of the embodiment.
  • FIG. 4 is a diagram showing a silicon carbide substrate according to a third example of the embodiment.
  • FIG. 5 is a diagram showing a silicon carbide substrate according to a fourth example of the embodiment.
  • FIG. 6 is a diagram showing a silicon carbide substrate according to a fifth example of the embodiment.
  • FIG. 7 is a diagram showing a silicon carbide substrate according to a sixth example of the embodiment.
  • the present disclosure aims to provide a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that can improve recombination efficiency and reduce the required thickness of a silicon carbide epitaxial layer.
  • the present disclosure can provide a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that can improve recombination efficiency and reduce the required thickness of a silicon carbide epitaxial layer.
  • a silicon carbide substrate includes a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region.
  • the silicon carbide epitaxial layer may have a third region provided between the silicon carbide single crystal substrate and the second region, and the impurity concentration of the third region may be the same as the impurity concentration of the first region.
  • the third region has a lower concentration than the second region, which reduces the lattice mismatch with the silicon carbide single crystal substrate, thereby suppressing the generation of defects.
  • a buffer layer having the first conductivity type may be provided between the silicon carbide single crystal substrate and the silicon carbide epitaxial layer, and the impurity concentration of the buffer layer may be lower than the impurity concentration of the silicon carbide single crystal substrate.
  • BPDs basal plane dislocations
  • TEDs threading edge dislocations
  • a silicon carbide substrate includes a silicon carbide single crystal substrate having a first conductivity type, a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the buffer layer, the buffer layer having a fourth region and a fifth region, the fourth region being located on the fifth region, the impurity concentration of the fourth region being lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region being higher than the impurity concentration of the silicon carbide single crystal substrate.
  • the impurity concentration of the outermost surface of the buffer layer is low, stacking faults are unlikely to be formed on the outermost surface of the buffer layer.
  • the buffer layer may have a sixth region provided between the silicon carbide single crystal substrate and the fifth region, and the impurity concentration of the sixth region may be the same as the impurity concentration of the fourth region.
  • the sixth region has a lower concentration than the fifth region, which reduces the lattice mismatch with the silicon carbide single crystal substrate, thereby suppressing the generation of defects.
  • a silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region.
  • the impurity concentration of the outermost surface of the silicon carbide epitaxial layer is low, stacking faults are unlikely to form on the outermost surface of the silicon carbide epitaxial layer. This prevents stacking faults from being inherited from the silicon carbide epitaxial layer to the drift layer.
  • the presence of a region with a high impurity concentration in the silicon carbide epitaxial layer promotes carrier recombination. This improves recombination efficiency and reduces the required thickness of the silicon carbide epitaxial layer.
  • a silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the buffer layer, the buffer layer having a fourth region and a fifth region, the fourth region being located on the fifth region, the impurity concentration of the fourth region being lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region being higher than the impurity concentration of the silicon carbide single crystal substrate.
  • a method for manufacturing a silicon carbide substrate includes the steps of: forming a silicon carbide epitaxial layer having a first conductivity type and having a higher impurity concentration than the silicon carbide single crystal substrate on a silicon carbide single crystal substrate having the first conductivity type; forming a second region having the first conductivity type at a position spaced from an upper surface of the silicon carbide epitaxial layer by ion implantation into the silicon carbide epitaxial layer; and, after the step of forming the second region, forming a drift layer having the first conductivity type on the silicon carbide epitaxial layer, wherein a first region is formed on the second region of the silicon carbide epitaxial layer in conjunction with the formation of the second region, and the impurity concentration of the first region is higher than the impurity concentration of the silicon carbide single crystal substrate and the impurity concentration of the second region is higher than the impurity concentration of the first region.
  • a method for manufacturing a silicon carbide substrate includes the steps of forming a buffer layer having a first conductivity type and a lower impurity concentration than the silicon carbide single crystal substrate on a silicon carbide single crystal substrate having a first conductivity type, forming a fifth region having the first conductivity type at a position separated from the upper surface of the buffer layer by ion implantation into the buffer layer, and forming a drift layer having the first conductivity type on the buffer layer after the step of forming the fifth region, and a fourth region is formed on the fifth region of the buffer layer with the formation of the fifth region, and the impurity concentration of the fourth region is lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region is higher than the impurity concentration of the silicon carbide single crystal substrate.
  • FIG 1 is a cross-sectional view showing a silicon carbide semiconductor device 100 according to an embodiment.
  • the silicon carbide semiconductor device 100 mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.
  • the silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50.
  • the silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1.
  • the silicon carbide epitaxial layer 40 constitutes the first main surface 1
  • the silicon carbide single crystal substrate 50 constitutes the second main surface 2.
  • the silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are composed of, for example, hexagonal silicon carbide of polytype 4H.
  • the silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type.
  • a semiconductor element is formed on the silicon carbide substrate 10.
  • a field effect transistor is formed as an example of a semiconductor element on the silicon carbide substrate 10.
  • the silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, a contact region 18, and a recombination promotion layer 19.
  • the drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.
  • the body region 12 is provided on the drift region 11.
  • the body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity.
  • the source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12.
  • the source region 13 contains n-type impurities such as nitrogen or phosphorus, and has an n-type.
  • the source region 13 constitutes the first main surface 1.
  • the contact region 18 contains p-type impurities such as aluminum and has a p-type.
  • the contact region 18 constitutes the first main surface 1.
  • the contact region 18 penetrates the source region 13 and contacts the body region 12.
  • the recombination promotion layer 19 is provided on the silicon carbide single crystal substrate 50.
  • the recombination promotion layer 19 is provided between the silicon carbide single crystal substrate 50 and the drift region 11. The details of the recombination promotion layer 19 will be described later.
  • a plurality of gate trenches 5 are provided in the first main surface 1.
  • the gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and the plurality of gate trenches 5 are arranged in a second direction.
  • the gate trenches 5 have a bottom surface 4 made of the drift region 11.
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 2.
  • the gate trenches 5 have side surfaces 3 that penetrate the source region 13 and the body region 12 and are continuous with the bottom surface 4.
  • the side surfaces 3 are inclined with respect to a plane including the bottom surface 4.
  • the gate insulating film 81 contacts the side surface 3 and the bottom surface 4.
  • the gate insulating film 81 is, for example, an oxide film.
  • the gate insulating film 81 is made of, for example, a material containing silicon dioxide.
  • the gate insulating film 81 contacts the drift region 11 at the bottom surface 4.
  • the gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3.
  • the gate insulating film 81 may contact the source region 13 at the first main surface 1.
  • the gate electrode 82 is provided on the gate insulating film 81.
  • the gate electrode 82 is made of, for example, polysilicon containing conductive impurities.
  • the gate electrode 82 is disposed inside the gate trench 5.
  • the interlayer insulating film 83 contacts the gate electrode 82 and the gate insulating film 81.
  • the interlayer insulating film 83 is made of a material containing, for example, silicon dioxide.
  • Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.
  • the source electrode 60 contacts the first main surface 1.
  • the source electrode 60 has a contact electrode 61 and a source wiring 62.
  • the contact electrode 61 is provided in the contact hole 90.
  • the contact electrode 61 contacts the source region 13 and the contact region 18 on the first main surface 1.
  • the contact electrode 61 is made of a material including titanium (Ti), aluminum (Al), and silicon (Si).
  • the contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18.
  • the contact electrode 61 is connected to the silicon carbide substrate 10 through the contact hole 90.
  • the source wiring 62 is made of a material containing aluminum or copper (Cu).
  • the source wiring 62 may be made of a material containing aluminum and copper.
  • the source electrode 60 is electrically insulated from the gate electrode 82 by the interlayer insulating film 83.
  • the source electrode 60 may include a barrier metal film, such as a titanium nitride (TiN) film, between the source wiring 62 and the interlayer insulating film 83.
  • the drain electrode 70 contacts the second main surface 2.
  • the drain electrode 70 contacts the silicon carbide single crystal substrate 50 at the second main surface 2.
  • the drain electrode 70 is electrically connected to the drift region 11.
  • the drain electrode 70 is made of the same material as the contact electrode 61.
  • the drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.
  • silicon carbide substrate 10 included in silicon carbide semiconductor device 100 according to the embodiment will be described.
  • FIG. 2 is a diagram showing a silicon carbide substrate 10A according to a first example of an embodiment.
  • the left figure shows a cross-sectional view of the silicon carbide substrate 10A
  • the right figure shows an impurity concentration profile of the silicon carbide substrate 10A.
  • the silicon carbide substrate 10A mainly includes a silicon carbide single crystal substrate 50, a recombination promotion layer 19, and a drift region 11.
  • Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has an n-type.
  • the effective concentration of the n-type impurity in silicon carbide single crystal substrate 50 is, for example, not less than 1 ⁇ 10 18 cm ⁇ 3 and not more than 7 ⁇ 10 18 cm ⁇ 3 .
  • the recombination promotion layer 19 is provided on a silicon carbide single crystal substrate 50.
  • the recombination promotion layer 19 has a first region 19a, a second region 19b, and a third region 19c.
  • the first region 19a is provided on the second region 19b.
  • the first region 19a is in contact with the drift region 11.
  • the first region 19a contains an n-type impurity such as nitrogen or phosphorus, and has an n-type.
  • the effective concentration of the n-type impurity in the first region 19a is higher than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50.
  • the effective concentration of the n-type impurity in the first region 19a is, for example, not less than 5 ⁇ 10 18 cm ⁇ 3 and not more than 2 ⁇ 10 19 cm ⁇ 3 .
  • the second region 19b is provided on the third region 19c.
  • the second region 19b is provided at a position separated from the upper surface of the recombination promotion layer 19.
  • the second region 19b is provided between the first region 19a and the third region 19c.
  • the second region 19b contains n-type impurities such as nitrogen or phosphorus and has an n-type.
  • the effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a.
  • the effective concentration of the n-type impurity in the second region 19b is, for example, 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the third region 19c is provided on the silicon carbide single crystal substrate 50.
  • the third region 19c is in contact with the silicon carbide single crystal substrate 50.
  • the third region 19c contains an n-type impurity such as nitrogen or phosphorus and has an n-type.
  • the effective concentration of the n-type impurity in the third region 19c is, for example, the same as the effective concentration of the n-type impurity in the first region 19a. In this case, the third region 19c has a lower concentration than the second region 19b. Therefore, the lattice mismatch with the silicon carbide single crystal substrate 50 is reduced, and thus defect generation can be suppressed.
  • the effective concentration of the n-type impurity in the third region 19c is, for example, 5 ⁇ 10 18 cm ⁇ 3 or more and 2 ⁇ 10 19 cm ⁇ 3 or less.
  • the drift region 11 is provided on the recombination promotion layer 19.
  • the drift region 11 is in contact with the first region 19a.
  • the drift region 11 contains n-type impurities such as nitrogen or phosphorus and has an n-type.
  • the effective concentration of the n-type impurity in the drift region 11 is, for example, not less than 1 ⁇ 10 14 cm ⁇ 3 and not more than 5 ⁇ 10 16 cm ⁇ 3 .
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a.
  • the impurity concentration in the outermost region (first region 19a) of the recombination promotion layer 19 is low, stacking faults are unlikely to be formed in the outermost surface of the recombination promotion layer 19. Therefore, stacking faults are prevented from being inherited from the recombination promotion layer 19 to the drift region 11.
  • second region 19b since a region (second region 19b) with a high impurity concentration exists in the recombination promotion layer 19, the recombination of carriers is promoted. Therefore, the recombination efficiency is improved and the required thickness of the recombination promotion layer 19 can be reduced. Reducing the required thickness of the recombination promotion layer 19 shortens the time required for epitaxial growth when forming the recombination promotion layer 19, thereby reducing manufacturing costs.
  • a silicon carbide single crystal substrate 50 is prepared.
  • the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.
  • the recombination promotion layer 19 is formed on the silicon carbide single crystal substrate 50. Specifically, the recombination promotion layer 19 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus. Next, ions are implanted into the recombination promotion layer 19. A second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by the ion implantation. As the second region 19b is formed, a first region 19a is formed on the second region 19b of the recombination promotion layer 19, and a third region 19c is formed below the second region 19b of the recombination promotion layer 19. In the ion implantation to form the second region 19b, for example, an n-type impurity such as nitrogen or phosphorus is implanted.
  • a silicon carbide epitaxial layer 40 is formed on the recombination promotion layer 19.
  • the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of an n-type impurity such as nitrogen.
  • ions are implanted into the silicon carbide epitaxial layer 40.
  • the body region 12, the source region 13, and the contact region 18 are formed by ion implantation.
  • the remaining portion of the silicon carbide epitaxial layer 40 functions as the drift region 11.
  • a p-type impurity such as aluminum is ion implanted.
  • an n-type impurity such as phosphorus is ion implanted.
  • a silicon carbide substrate 10A can be manufactured in which a recombination promotion layer 19 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.
  • the second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by ion implantation into the recombination promotion layer 19.
  • the first region 19a is formed on the second region 19b of the recombination promotion layer 19.
  • the effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a.
  • the impurity concentration in the outermost region (first region 19a) of the recombination promotion layer 19 is low, stacking faults are unlikely to be formed on the outermost surface of the recombination promotion layer 19. Therefore, the transfer of stacking faults from the recombination promotion layer 19 to the drift region 11 is suppressed.
  • the recombination of carriers is promoted. This improves recombination efficiency and reduces the required thickness of the recombination promotion layer 19. Reducing the required thickness of the recombination promotion layer 19 shortens the time required for epitaxial growth when forming the recombination promotion layer 19, thereby reducing manufacturing costs.
  • FIG. 3 is a diagram showing a silicon carbide substrate 10B according to a second example of an embodiment.
  • the left figure shows a cross-sectional view of the silicon carbide substrate 10B
  • the right figure shows an impurity concentration profile of the silicon carbide substrate 10B.
  • Silicon carbide substrate 10B differs from silicon carbide substrate 10A in that recombination promotion layer 19 does not have third region 19c, but has first region 19a and second region 19b.
  • the rest of the configuration of silicon carbide substrate 10B is the same as, for example, silicon carbide substrate 10A. The following description will focus on the configuration that differs from silicon carbide substrate 10A.
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the first region 19a contacts the drift region 11.
  • the second region 19b is provided on the silicon carbide single crystal substrate 50.
  • the second region 19b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19.
  • the second region 19b contacts the silicon carbide single crystal substrate 50.
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a.
  • the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.
  • Silicon carbide substrate 10B can be manufactured, for example, by a method similar to that for silicon carbide substrate 10A.
  • the method for manufacturing silicon carbide substrate 10B provides the same effects as the method for manufacturing silicon carbide substrate 10A.
  • FIG. 4 is a diagram showing a silicon carbide substrate 10C according to a third example of an embodiment.
  • the left figure shows a cross-sectional view of the silicon carbide substrate 10C
  • the right figure shows an impurity concentration profile of the silicon carbide substrate 10C.
  • the silicon carbide substrate 10C mainly includes a silicon carbide single crystal substrate 50, a buffer layer 20, and a drift region 11.
  • the buffer layer 20 is provided on a silicon carbide single crystal substrate 50.
  • the buffer layer 20 has a fourth region 20a, a fifth region 20b, and a sixth region 20c.
  • the fourth region 20a is provided on the fifth region 20b.
  • the fourth region 20a contacts the drift region 11.
  • the fourth region 20a contains an n-type impurity such as nitrogen or phosphorus, and has an n-type.
  • the effective concentration of the n-type impurity in the fourth region 20a is lower than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50.
  • the effective concentration of the n-type impurity in the fourth region 20a is, for example, 2 ⁇ 10 17 cm ⁇ 3 or more and 3 ⁇ 10 18 cm ⁇ 3 or less.
  • the effective concentration of the n-type impurity in the fourth region 20a is approximately constant, and the effective concentration of the n-type impurity at the interface between the fourth region 20a and the drift region 11 may be abruptly switched from the concentration in the fourth region 20a to the concentration in the drift region 11. In this case, the resistance of the silicon carbide semiconductor device 100 is unlikely to be high. In contrast, when the effective concentration of n-type impurities in fourth region 20a continuously decreases toward drift region 11, the resistance of silicon carbide semiconductor device 100 is likely to increase.
  • the fifth region 20b is provided on the sixth region 20c.
  • the fifth region 20b is provided at a position separated from the upper surface of the buffer layer 20.
  • the fifth region 20b is provided between the fourth region 20a and the sixth region 20c.
  • the fifth region 20b contains an n-type impurity such as nitrogen or phosphorus, and has an n-type.
  • the effective concentration of the n-type impurity in the fifth region 20b is higher than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50.
  • the effective concentration of the n-type impurity in the fifth region 20b is, for example, 1 ⁇ 10 19 cm ⁇ 3 or more.
  • the sixth region 20c is provided on the silicon carbide single crystal substrate 50.
  • the sixth region 20c is in contact with the silicon carbide single crystal substrate 50.
  • the sixth region 20c contains n-type impurities such as nitrogen or phosphorus, and has an n-type.
  • the effective concentration of the n-type impurities in the sixth region 20c is, for example, the same as the effective concentration of the n-type impurities in the fourth region 20a. In this case, the sixth region 20c has a lower concentration than the fifth region 20b. Therefore, the lattice mismatch with the silicon carbide single crystal substrate 50 is reduced, and thus defect generation can be suppressed.
  • the effective concentration of the n-type impurities in the sixth region 20c is, for example, 2 ⁇ 10 17 cm ⁇ 3 or more and 3 ⁇ 10 18 cm ⁇ 3 or less.
  • the drift region 11 is provided on the buffer layer 20.
  • the drift region 11 is in contact with the fourth region 20a.
  • the drift region 11 contains an n-type impurity such as nitrogen or phosphorus and has an n-type.
  • the effective concentration of the n-type impurity in the drift region 11 is, for example, not less than 1 ⁇ 10 14 cm ⁇ 3 and not more than 5 ⁇ 10 16 cm ⁇ 3 .
  • the buffer layer 20 has a fourth region 20a and a fifth region 20b.
  • the fourth region 20a is provided on the fifth region 20b.
  • the effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a.
  • the impurity concentration in the outermost region (fourth region 20a) of the buffer layer 20 is low, stacking faults are unlikely to be formed in the outermost surface of the buffer layer 20. Therefore, stacking faults are prevented from being inherited from the buffer layer 20 to the drift region 11.
  • the buffer layer 20 since a region (fifth region 20b) with a high impurity concentration exists in the buffer layer 20, carrier recombination is promoted. Therefore, the recombination efficiency is improved and the required thickness of the buffer layer 20 can be reduced. Reducing the required thickness of the buffer layer 20 shortens the time required for epitaxial growth when forming the buffer layer 20, thereby reducing manufacturing costs.
  • a silicon carbide single crystal substrate 50 is prepared.
  • the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.
  • the buffer layer 20 is formed on the silicon carbide single crystal substrate 50.
  • the buffer layer 20 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus.
  • ions are implanted into the buffer layer 20.
  • a fifth region 20b is formed at a position separated from the upper surface of the buffer layer 20 by the ion implantation. With the formation of the fifth region 20b, a fourth region 20a is formed on the fifth region 20b of the buffer layer 20, and a sixth region 20c is formed below the fifth region 20b of the buffer layer 20.
  • an n-type impurity such as nitrogen or phosphorus is implanted.
  • a silicon carbide epitaxial layer 40 is formed on the buffer layer 20.
  • the method for forming the silicon carbide epitaxial layer 40 may be the same as the method for forming the silicon carbide epitaxial layer 40 in the method for manufacturing the silicon carbide substrate 10A.
  • a silicon carbide substrate 10C can be manufactured in which a buffer layer 20 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.
  • the fifth region 20b is formed at a position separated from the upper surface of the buffer layer 20 by ion implantation into the buffer layer 20.
  • the fourth region 20a is formed on the fifth region 20b of the buffer layer 20.
  • the effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a. In this case, since the impurity concentration in the outermost region (fourth region 20a) of the buffer layer 20 is low, stacking faults are unlikely to be formed in the outermost surface of the buffer layer 20.
  • FIG. 5 is a diagram showing a silicon carbide substrate 10D according to a fourth embodiment.
  • the left figure shows a cross-sectional view of the silicon carbide substrate 10D
  • the right figure shows an impurity concentration profile of the silicon carbide substrate 10D.
  • Silicon carbide substrate 10D differs from silicon carbide substrate 10C in that buffer layer 20 does not have sixth region 20c, but has fourth region 20a and fifth region 20b.
  • Other configurations of silicon carbide substrate 10D are the same as, for example, silicon carbide substrate 10C. The following description will focus on the configurations that differ from silicon carbide substrate 10C.
  • the buffer layer 20 has a fourth region 20a and a fifth region 20b.
  • the fourth region 20a is provided on the fifth region 20b.
  • the fourth region 20a contacts the drift region 11.
  • the fifth region 20b is provided on the silicon carbide single crystal substrate 50.
  • the fifth region 20b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19.
  • the fifth region 20b contacts the silicon carbide single crystal substrate 50.
  • the buffer layer 20 has a fourth region 20a and a fifth region 20b.
  • the fourth region 20a is provided on the fifth region 20b.
  • the effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a. In this case, the same effects as those of the silicon carbide substrate 10C and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10C can be obtained.
  • Silicon carbide substrate 10D can be manufactured, for example, by a method similar to that for silicon carbide substrate 10C.
  • the method for manufacturing silicon carbide substrate 10D provides the same effects as the method for manufacturing silicon carbide substrate 10C.
  • FIG. 6 is a diagram showing a silicon carbide substrate 10E according to a fifth embodiment.
  • the left figure shows a cross-sectional view of the silicon carbide substrate 10E
  • the right figure shows an impurity concentration profile of the silicon carbide substrate 10E.
  • Silicon carbide substrate 10E differs from silicon carbide substrate 10A in that it has a buffer layer 21 between silicon carbide single crystal substrate 50 and recombination promotion layer 19.
  • the rest of the configuration of silicon carbide substrate 10E is the same as, for example, silicon carbide substrate 10A. Below, the configuration that differs from silicon carbide substrate 10A will be mainly described.
  • the silicon carbide substrate 10E mainly includes a silicon carbide single crystal substrate 50, a buffer layer 21, a recombination promotion layer 19, and a drift region 11.
  • the buffer layer 21 is provided on the silicon carbide single crystal substrate 50.
  • the buffer layer 21 is provided between the silicon carbide single crystal substrate 50 and the recombination promotion layer 19.
  • the buffer layer 21 contains an n-type impurity such as nitrogen or phosphorus, and has an n-type.
  • the effective concentration of the n-type impurity in the buffer layer 21 is lower than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50.
  • the effective concentration of the n-type impurity in the buffer layer 21 is, for example, not less than 2 ⁇ 10 17 cm ⁇ 3 and not more than 3 ⁇ 10 18 cm ⁇ 3 .
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a.
  • the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.
  • the buffer layer 21 is provided between the silicon carbide single crystal substrate 50 and the recombination promotion layer 19.
  • the basal plane dislocations present in the silicon carbide single crystal substrate 50 are easily converted to threading edge dislocations at the interface between the silicon carbide single crystal substrate 50 and the buffer layer 21. Therefore, the basal plane dislocations can be prevented from reaching the drift region 11.
  • the expansion of stacking faults in the drift region 11 is prevented when a current is applied in the forward direction to the pn junction, and as a result, the increase in the on-voltage can be prevented.
  • a silicon carbide single crystal substrate 50 is prepared.
  • the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.
  • a buffer layer 21 is formed on the silicon carbide single crystal substrate 50.
  • the buffer layer 21 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus.
  • the recombination promotion layer 19 is formed on the buffer layer 21.
  • the method for forming the recombination promotion layer 19 may be the same as the method for forming the recombination promotion layer 19 in the manufacturing method of the silicon carbide substrate 10A.
  • a silicon carbide epitaxial layer 40 is formed on the recombination promotion layer 19.
  • the method for forming the silicon carbide epitaxial layer 40 may be the same as the method for forming the silicon carbide epitaxial layer 40 in the method for manufacturing the silicon carbide substrate 10A.
  • a silicon carbide substrate 10E can be manufactured in which a buffer layer 21 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.
  • the second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by ion implantation into the recombination promotion layer 19.
  • the first region 19a is formed on the second region 19b of the recombination promotion layer 19.
  • the effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a. In this case, the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.
  • buffer layer 21 is grown by epitaxial growth on silicon carbide single crystal substrate 50
  • basal plane dislocations present in silicon carbide single crystal substrate 50 are likely to be converted to threading edge dislocations at the interface between silicon carbide single crystal substrate 50 and buffer layer 21. Therefore, basal plane dislocations can be prevented from reaching drift region 11.
  • the expansion of stacking faults in drift region 11 when forward current is applied to the pn junction is prevented, and as a result, an increase in on-voltage can be prevented.
  • FIG. 7 is a diagram showing a silicon carbide substrate 10F according to a sixth embodiment.
  • the left diagram shows a cross-sectional view of the silicon carbide substrate 10F
  • the right diagram shows an impurity concentration profile of the silicon carbide substrate 10F.
  • Silicon carbide substrate 10F differs from silicon carbide substrate 10E in that recombination promotion layer 19 does not have third region 19c, but has first region 19a and second region 19b.
  • the rest of the configuration of silicon carbide substrate 10F is the same as, for example, silicon carbide substrate 10E. The following description will focus on the configuration that differs from silicon carbide substrate 10E.
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the first region 19a contacts the drift region 11.
  • the second region 19b is provided on the silicon carbide single crystal substrate 50.
  • the second region 19b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19.
  • the second region 19b contacts the silicon carbide single crystal substrate 50.
  • the recombination promotion layer 19 has a first region 19a and a second region 19b.
  • the first region 19a is provided on the second region 19b.
  • the effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a.
  • the same effects as those of the silicon carbide substrate 10E and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10E can be obtained.
  • Silicon carbide substrate 10F can be manufactured, for example, by a method similar to that for silicon carbide substrate 10E.
  • the manufacturing method for silicon carbide substrate 10F provides the same effects as the manufacturing method for silicon carbide substrate 10E.
  • the effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the above impurity regions can be measured using a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method, for example.
  • SCM scanning capacitance microscope
  • SIMS secondary ion mass spectrometry
  • Silicon carbide substrate 10A Silicon carbide substrate 10B Silicon carbide substrate 10C Silicon carbide substrate 10D Silicon carbide substrate 10E Silicon carbide substrate 10F Silicon carbide substrate 11 Drift region 12 Body region 13 Source region 18 Contact region 19 Recombination promotion layer 19a First region 19b Second region 19c Third region 20 Buffer layer 20a Fourth region 20b Fifth region 20c Sixth region 21 Buffer layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 90 Contact hole 100 Silicon carbide semiconductor device

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Abstract

A silicon carbide substrate according to the present invention includes: a silicon carbide single-crystal substrate having a first conductivity type; a silicon carbide epitaxial layer provided on the silicon carbide single-crystal substrate and having the first conductivity type; and a drift layer provided on the silicon carbide epitaxial layer and having the first conductivity type. The silicon carbide epitaxial layer has a first region and a second region. The first region is located above the second region. The impurity concentration of the first region is higher than the impurity concentration of the silicon carbide single-crystal substrate. The impurity concentration of the second region is higher than the impurity concentration of the first region.

Description

炭化珪素基板、炭化珪素半導体装置および炭化珪素基板の製造方法Silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate

　本開示は、炭化珪素基板、炭化珪素半導体装置および炭化珪素基板の製造方法に関する。 This disclosure relates to a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide substrate.

　本出願は、２０２３年６月８日出願の日本出願第２０２３－０９４７９３号に基づく優先権を主張し、前記日本出願に記載された全ての記載内容を援用するものである。 This application claims priority to Japanese Application No. 2023-094793, filed on June 8, 2023, and incorporates all of the contents of said Japanese application by reference.

　炭化珪素単結晶基板と炭化珪素エピタキシャル層との間に、炭化珪素単結晶基板よりも不純物濃度が高い再結合促進層（炭化珪素エピタキシャル層）を設けた炭化珪素エピタキシャル基板が開示されている。炭化珪素エピタキシャル層が設けられることで、炭化珪素単結晶基板に含まれる基底面転移からの積層欠陥の発生が抑制される。 A silicon carbide epitaxial substrate is disclosed in which a recombination-promoting layer (silicon carbide epitaxial layer) having a higher impurity concentration than the silicon carbide single crystal substrate is provided between the silicon carbide single crystal substrate and the silicon carbide epitaxial layer. The provision of the silicon carbide epitaxial layer suppresses the occurrence of stacking faults due to basal plane dislocations contained in the silicon carbide single crystal substrate.

国際公開第２０１７／０９４７６４号International Publication No. 2017/094764

　本開示の炭化珪素基板は、第１導電型を有する炭化珪素単結晶基板と、前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有する炭化珪素エピタキシャル層と、前記炭化珪素エピタキシャル層の上に設けられ、前記第１導電型を有するドリフト層と、を有し、前記炭化珪素エピタキシャル層は、第１領域と、第２領域とを有し、前記第１領域は、前記第２領域の上に位置し、前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い。 The silicon carbide substrate of the present disclosure comprises a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region.

図１は、実施形態に係る炭化珪素半導体装置を示す断面図である。FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. 図２は、実施形態の第１例に係る炭化珪素基板を示す図である。FIG. 2 is a diagram showing a silicon carbide substrate according to a first example of the embodiment. 図３は、実施形態の第２例に係る炭化珪素基板を示す図である。FIG. 3 is a diagram showing a silicon carbide substrate according to a second example of the embodiment. 図４は、実施形態の第３例に係る炭化珪素基板を示す図である。FIG. 4 is a diagram showing a silicon carbide substrate according to a third example of the embodiment. 図５は、実施形態の第４例に係る炭化珪素基板を示す図である。FIG. 5 is a diagram showing a silicon carbide substrate according to a fourth example of the embodiment. 図６は、実施形態の第５例に係る炭化珪素基板を示す図である。FIG. 6 is a diagram showing a silicon carbide substrate according to a fifth example of the embodiment. 図７は、実施形態の第６例に係る炭化珪素基板を示す図である。FIG. 7 is a diagram showing a silicon carbide substrate according to a sixth example of the embodiment.

　［本開示が解決しようとする課題］
　炭化珪素エピタキシャル層を薄くする場合、炭化珪素エピタキシャル層の不純物濃度を高くすることが有効である。しかしながら、炭化珪素エピタキシャル層の不純物濃度を高くすると、結晶歪みにより炭化珪素エピタキシャル層に積層欠陥が形成されやすい。積層欠陥が形成されると、炭化珪素エピタキシャル層の上に形成されるドリフト層にも積層欠陥が拡張する。 [Problem to be solved by the present disclosure]
In order to make the silicon carbide epitaxial layer thinner, it is effective to increase the impurity concentration of the silicon carbide epitaxial layer. However, when the impurity concentration of the silicon carbide epitaxial layer is increased, stacking faults are likely to be formed in the silicon carbide epitaxial layer due to crystal distortion. When stacking faults are formed, the stacking faults also extend to the drift layer formed on the silicon carbide epitaxial layer.

　本開示は、再結合効率を向上し、必要な炭化珪素エピタキシャル層の厚みを低減できる炭化珪素基板、炭化珪素半導体装置および炭化珪素半導体装置の製造方法を提供することを目的とする。 The present disclosure aims to provide a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that can improve recombination efficiency and reduce the required thickness of a silicon carbide epitaxial layer.

　［本開示の効果］
　本開示によれば、再結合効率を向上し、必要な炭化珪素エピタキシャル層の厚みを低減できる炭化珪素基板、炭化珪素半導体装置および炭化珪素半導体装置の製造方法を提供できる。 [Effects of the present disclosure]
Advantageous Effects of Invention The present disclosure can provide a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that can improve recombination efficiency and reduce the required thickness of a silicon carbide epitaxial layer.

　実施するための形態について、以下に説明する。 The form for implementation is explained below.

　［本開示の実施形態の説明］
　最初に本開示の実施態様を列記して説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。 [Description of the embodiments of the present disclosure]
First, the embodiments of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

　〔１〕　本開示の一態様に係る炭化珪素基板は、第１導電型を有する炭化珪素単結晶基板と、前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有する炭化珪素エピタキシャル層と、前記炭化珪素エピタキシャル層の上に設けられ、前記第１導電型を有するドリフト層と、を有し、前記炭化珪素エピタキシャル層は、第１領域と、第２領域とを有し、前記第１領域は、前記第２領域の上に位置し、前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い。この場合、炭化珪素エピタキシャル層の最表面の不純物濃度が低いので、炭化珪素エピタキシャル層の最表面において積層欠陥が形成されにくい。そのため、炭化珪素エピタキシャル層からドリフト層に積層欠陥が引き継がれることが抑制される。また、炭化珪素エピタキシャル層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要な炭化珪素エピタキシャル層の厚みを低減できる。 　[1]　A silicon carbide substrate according to one embodiment of the present disclosure includes a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region. In this case, since the impurity concentration of the outermost surface of the silicon carbide epitaxial layer is low, stacking faults are unlikely to be formed on the outermost surface of the silicon carbide epitaxial layer. Therefore, stacking faults are prevented from being inherited from the silicon carbide epitaxial layer to the drift layer. In addition, since there are regions with high impurity concentrations in the silicon carbide epitaxial layer, carrier recombination is promoted. This improves recombination efficiency and reduces the required thickness of the silicon carbide epitaxial layer.

　〔２〕　〔１〕において、前記炭化珪素エピタキシャル層は、前記炭化珪素単結晶基板と前記第２領域との間に設けられる第３領域を有し、前記第３領域の不純物濃度は、前記第１領域の不純物濃度と同じであってもよい。この場合、第２領域よりもより低濃度の第３領域により炭化珪素単結晶基板との格子不整合が小さくなるため欠陥生成を抑制できる。 [2] In [1], the silicon carbide epitaxial layer may have a third region provided between the silicon carbide single crystal substrate and the second region, and the impurity concentration of the third region may be the same as the impurity concentration of the first region. In this case, the third region has a lower concentration than the second region, which reduces the lattice mismatch with the silicon carbide single crystal substrate, thereby suppressing the generation of defects.

　〔３〕　〔１〕または〔２〕において、前記炭化珪素単結晶基板と前記炭化珪素エピタキシャル層との間に設けられ、前記第１導電型を有するバッファ層を有し、前記バッファ層の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低くてもよい。この場合、炭化珪素単結晶基板の上にエピタキシャル成長によりバッファ層を成長させる際に、炭化珪素単結晶基板内に存在する基底面転移（ＢＰＤ：Basal Plane Dislocation）が炭化珪素単結晶基板とバッファ層との界面で貫通刃状転移（ＴＥＤ：Threading Edge Dislocation）に転換されやすい。そのため、基底面転移がドリフト層に到達することを抑制できる。その結果、ｐｎ接合に順方向通電を行った際にドリフト層に積層欠陥が拡大することが抑制され、結果としてオン電圧の上昇を抑制できる。 [3] In [1] or [2], a buffer layer having the first conductivity type may be provided between the silicon carbide single crystal substrate and the silicon carbide epitaxial layer, and the impurity concentration of the buffer layer may be lower than the impurity concentration of the silicon carbide single crystal substrate. In this case, when the buffer layer is grown by epitaxial growth on the silicon carbide single crystal substrate, basal plane dislocations (BPDs) present in the silicon carbide single crystal substrate are likely to be converted to threading edge dislocations (TEDs) at the interface between the silicon carbide single crystal substrate and the buffer layer. Therefore, the basal plane dislocations can be prevented from reaching the drift layer. As a result, the expansion of stacking faults in the drift layer when a forward current is applied to the pn junction is prevented, and as a result, an increase in the on-voltage can be prevented.

　〔４〕　本開示の他の一態様に係る炭化珪素基板は、第１導電型を有する炭化珪素単結晶基板と、前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有するバッファ層と、前記バッファ層の上に設けられ、前記第１導電型を有するドリフト層と、を有し、前記バッファ層は、第４領域と、第５領域とを有し、前記第４領域は、前記第５領域の上に位置し、前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い。この場合、バッファ層の最表面の不純物濃度が低いので、バッファ層の最表面において積層欠陥が形成されにくい。そのため、バッファ層からドリフト層に積層欠陥が引き継がれることが抑制される。また、バッファ層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要なバッファ層の厚みを低減できる。 [4] A silicon carbide substrate according to another embodiment of the present disclosure includes a silicon carbide single crystal substrate having a first conductivity type, a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the buffer layer, the buffer layer having a fourth region and a fifth region, the fourth region being located on the fifth region, the impurity concentration of the fourth region being lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region being higher than the impurity concentration of the silicon carbide single crystal substrate. In this case, since the impurity concentration of the outermost surface of the buffer layer is low, stacking faults are unlikely to be formed on the outermost surface of the buffer layer. Therefore, stacking faults are prevented from being inherited from the buffer layer to the drift layer. In addition, since a region with a high impurity concentration exists in the buffer layer, carrier recombination is promoted. Therefore, the recombination efficiency is improved and the required thickness of the buffer layer can be reduced.

　〔５〕　〔４〕において、前記バッファ層は、前記炭化珪素単結晶基板と前記第５領域との間に設けられる第６領域を有し、前記第６領域の不純物濃度は、前記第４領域の不純物濃度と同じであってもよい。この場合、第５領域よりもより低濃度の第６領域により炭化珪素単結晶基板との格子不整合が小さくなるため欠陥生成を抑制できる。 [5] In [4], the buffer layer may have a sixth region provided between the silicon carbide single crystal substrate and the fifth region, and the impurity concentration of the sixth region may be the same as the impurity concentration of the fourth region. In this case, the sixth region has a lower concentration than the fifth region, which reduces the lattice mismatch with the silicon carbide single crystal substrate, thereby suppressing the generation of defects.

　〔６〕　本開示の他の一態様に係る炭化珪素半導体装置は、第１主面と、前記第１主面と反対の第２主面とを有する炭化珪素基板を備え、前記炭化珪素基板は、第１導電型を有する炭化珪素単結晶基板と、前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有する炭化珪素エピタキシャル層と、前記炭化珪素エピタキシャル層の上に設けられ、前記第１導電型を有するドリフト層と、を有し、前記炭化珪素エピタキシャル層は、第１領域と、第２領域とを有し、前記第１領域は、前記第２領域の上に位置し、前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い。この場合、炭化珪素エピタキシャル層の最表面の不純物濃度が低いので、炭化珪素エピタキシャル層の最表面において積層欠陥が形成されにくい。そのため、炭化珪素エピタキシャル層からドリフト層に積層欠陥が引き継がれることが抑制される。また、炭化珪素エピタキシャル層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要な炭化珪素エピタキシャル層の厚みを低減できる。 [6] A silicon carbide semiconductor device according to another aspect of the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer, the silicon carbide epitaxial layer having a first region and a second region, the first region being located on the second region, the impurity concentration of the first region being higher than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the second region being higher than the impurity concentration of the first region. In this case, since the impurity concentration of the outermost surface of the silicon carbide epitaxial layer is low, stacking faults are unlikely to form on the outermost surface of the silicon carbide epitaxial layer. This prevents stacking faults from being inherited from the silicon carbide epitaxial layer to the drift layer. In addition, the presence of a region with a high impurity concentration in the silicon carbide epitaxial layer promotes carrier recombination. This improves recombination efficiency and reduces the required thickness of the silicon carbide epitaxial layer.

　〔７〕　本開示の他の一態様に係る炭化珪素半導体装置は、第１主面と、前記第１主面と反対の第２主面とを有する炭化珪素基板を備え、前記炭化珪素基板は、第１導電型を有する炭化珪素単結晶基板と、前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有するバッファ層と、前記バッファ層の上に設けられ、前記第１導電型を有するドリフト層と、を有し、前記バッファ層は、第４領域と、第５領域とを有し、前記第４領域は、前記第５領域の上に位置し、前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い。この場合、バッファ層の最表面の不純物濃度が低いので、バッファ層の最表面において積層欠陥が形成されにくい。そのため、バッファ層からドリフト層に積層欠陥が引き継がれることが抑制される。また、バッファ層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要なバッファ層の厚みを低減できる。 [7] A silicon carbide semiconductor device according to another aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a silicon carbide single crystal substrate having a first conductivity type, a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate, and a drift layer having the first conductivity type provided on the buffer layer, the buffer layer having a fourth region and a fifth region, the fourth region being located on the fifth region, the impurity concentration of the fourth region being lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region being higher than the impurity concentration of the silicon carbide single crystal substrate. In this case, since the impurity concentration of the outermost surface of the buffer layer is low, stacking faults are unlikely to be formed on the outermost surface of the buffer layer. Therefore, stacking faults are suppressed from being inherited from the buffer layer to the drift layer. In addition, since a region with a high impurity concentration exists in the buffer layer, carrier recombination is promoted. This improves recombination efficiency and reduces the required thickness of the buffer layer.

　〔８〕本開示の他の一態様に係る炭化珪素基板の製造方法は、第１導電型を有する炭化珪素単結晶基板の上に、前記第１導電型を有し、前記炭化珪素単結晶基板よりも不純物濃度が高い炭化珪素エピタキシャル層を形成する工程と、前記炭化珪素エピタキシャル層へのイオン注入により、前記炭化珪素エピタキシャル層の上面から離隔した位置に前記第１導電型を有する第２領域を形成する工程と、前記第２領域を形成する工程の後、前記炭化珪素エピタキシャル層の上に、前記第１導電型を有するドリフト層を形成する工程と、を有し、前記第２領域の形成に伴って、前記炭化珪素エピタキシャル層の前記第２領域の上に第１領域が形成され、前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い。この場合、炭化珪素エピタキシャル層の最表面の不純物濃度が低いので、炭化珪素エピタキシャル層の最表面において積層欠陥が形成されにくい。そのため、炭化珪素エピタキシャル層からドリフト層に積層欠陥が引き継がれることが抑制される。また、炭化珪素エピタキシャル層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要な炭化珪素エピタキシャル層の厚みを低減できる。 [8] A method for manufacturing a silicon carbide substrate according to another aspect of the present disclosure includes the steps of: forming a silicon carbide epitaxial layer having a first conductivity type and having a higher impurity concentration than the silicon carbide single crystal substrate on a silicon carbide single crystal substrate having the first conductivity type; forming a second region having the first conductivity type at a position spaced from an upper surface of the silicon carbide epitaxial layer by ion implantation into the silicon carbide epitaxial layer; and, after the step of forming the second region, forming a drift layer having the first conductivity type on the silicon carbide epitaxial layer, wherein a first region is formed on the second region of the silicon carbide epitaxial layer in conjunction with the formation of the second region, and the impurity concentration of the first region is higher than the impurity concentration of the silicon carbide single crystal substrate and the impurity concentration of the second region is higher than the impurity concentration of the first region. In this case, since the impurity concentration at the outermost surface of the silicon carbide epitaxial layer is low, stacking faults are unlikely to form at the outermost surface of the silicon carbide epitaxial layer. This prevents stacking faults from being inherited from the silicon carbide epitaxial layer to the drift layer. In addition, since there is a region with a high impurity concentration in the silicon carbide epitaxial layer, carrier recombination is promoted. This improves recombination efficiency and reduces the required thickness of the silicon carbide epitaxial layer.

　〔９〕本開示の他の一態様に係る炭化珪素基板の製造方法は、第１導電型を有する炭化珪素単結晶基板の上に、前記第１導電型を有し、前記炭化珪素単結晶基板よりも不純物濃度が低いバッファ層を形成する工程と、前記バッファ層へのイオン注入により、前記バッファ層の上面から離隔した位置に前記第１導電型を有する第５領域を形成する工程と、前記第５領域を形成する工程の後、前記バッファ層の上に、前記第１導電型を有するドリフト層を形成する工程と、を有し、前記第５領域の形成に伴って、前記バッファ層の前記第５領域の上に第４領域が形成され、前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い。この場合、バッファ層の最表面の不純物濃度が低いので、バッファ層の最表面において積層欠陥が形成されにくい。そのため、バッファ層からドリフト層に積層欠陥が引き継がれることが抑制される。また、バッファ層内に不純物濃度が高い領域が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要なバッファ層の厚みを低減できる。 [9] A method for manufacturing a silicon carbide substrate according to another aspect of the present disclosure includes the steps of forming a buffer layer having a first conductivity type and a lower impurity concentration than the silicon carbide single crystal substrate on a silicon carbide single crystal substrate having a first conductivity type, forming a fifth region having the first conductivity type at a position separated from the upper surface of the buffer layer by ion implantation into the buffer layer, and forming a drift layer having the first conductivity type on the buffer layer after the step of forming the fifth region, and a fourth region is formed on the fifth region of the buffer layer with the formation of the fifth region, and the impurity concentration of the fourth region is lower than the impurity concentration of the silicon carbide single crystal substrate, and the impurity concentration of the fifth region is higher than the impurity concentration of the silicon carbide single crystal substrate. In this case, since the impurity concentration of the outermost surface of the buffer layer is low, stacking faults are unlikely to be formed on the outermost surface of the buffer layer. Therefore, stacking faults are suppressed from being inherited from the buffer layer to the drift layer. In addition, since a region having a high impurity concentration exists in the buffer layer, recombination of carriers is promoted. This improves recombination efficiency and reduces the required thickness of the buffer layer.

　［本開示の実施形態の詳細］
　以下、本開示の実施形態について詳細に説明するが、本開示はこれらに限定されるものではない。 [Details of the embodiment of the present disclosure]
Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

　（炭化珪素半導体装置）
　実施形態に係る炭化珪素半導体装置１００について説明する。図１は、実施形態に係る炭化珪素半導体装置１００を示す断面図である。 (Silicon carbide semiconductor device)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A silicon carbide semiconductor device 100 according to an embodiment will now be described. FIG 1 is a cross-sectional view showing a silicon carbide semiconductor device 100 according to an embodiment.

　炭化珪素半導体装置１００は、炭化珪素基板１０と、ゲート絶縁膜８１と、ゲート電極８２と、層間絶縁膜８３と、ソース電極６０と、ドレイン電極７０とを主に有する。 The silicon carbide semiconductor device 100 mainly includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, and a drain electrode 70.

　炭化珪素基板１０は、炭化珪素単結晶基板５０と、炭化珪素単結晶基板５０上にある炭化珪素エピタキシャル層４０とを含む。炭化珪素基板１０は、第１主面１と、第１主面１と反対の第２主面２とを有する。炭化珪素エピタキシャル層４０は第１主面１を構成し、炭化珪素単結晶基板５０は第２主面２を構成する。炭化珪素単結晶基板５０および炭化珪素エピタキシャル層４０は、例えばポリタイプ４Ｈの六方晶炭化珪素から構成されている。炭化珪素単結晶基板５０は、例えば窒素（Ｎ）などのｎ型不純物を含みｎ型を有する。炭化珪素基板１０に半導体素子が形成されている。 The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type. A semiconductor element is formed on the silicon carbide substrate 10.

　実施形態では、炭化珪素基板１０に半導体素子の一例として電界効果トランジスタが形成されている。炭化珪素エピタキシャル層４０は、ドリフト領域１１と、ボディ領域１２と、ソース領域１３と、コンタクト領域１８と、再結合促進層１９とを主に有する。 In the embodiment, a field effect transistor is formed as an example of a semiconductor element on the silicon carbide substrate 10. The silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, a contact region 18, and a recombination promotion layer 19.

　ドリフト領域１１は、例えば窒素またはリン（Ｐ）などのｎ型不純物を含み、ｎ型を有する。 The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.

　ボディ領域１２は、ドリフト領域１１上に設けられている。ボディ領域１２は、例えばアルミニウム（Ａｌ）などのｐ型不純物を含み、ｐ型を有する。 The body region 12 is provided on the drift region 11. The body region 12 contains p-type impurities such as aluminum (Al) and has a p-type conductivity.

　ソース領域１３は、ボディ領域１２によってドリフト領域１１から隔てられるようにボディ領域１２上に設けられている。ソース領域１３は、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。ソース領域１３は、第１主面１を構成する。 The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 contains n-type impurities such as nitrogen or phosphorus, and has an n-type. The source region 13 constitutes the first main surface 1.

　コンタクト領域１８は、例えばアルミニウムなどのｐ型不純物を含み、ｐ型を有する。コンタクト領域１８は、第１主面１を構成する。コンタクト領域１８は、ソース領域１３を貫通し、ボディ領域１２と接する。 The contact region 18 contains p-type impurities such as aluminum and has a p-type. The contact region 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and contacts the body region 12.

　再結合促進層１９は、炭化珪素単結晶基板５０の上に設けられている。再結合促進層１９は、炭化珪素単結晶基板５０とドリフト領域１１との間に設けられている。再結合促進層１９の詳細については後述する。 The recombination promotion layer 19 is provided on the silicon carbide single crystal substrate 50. The recombination promotion layer 19 is provided between the silicon carbide single crystal substrate 50 and the drift region 11. The details of the recombination promotion layer 19 will be described later.

　第１主面１には、複数のゲートトレンチ５が設けられている。ゲートトレンチ５は、例えば第１主面１に平行な第１方向に延びており、複数のゲートトレンチ５が第２方向に並んでいる。ゲートトレンチ５は、ドリフト領域１１からなる底面４を有する。底面４は、例えば第２主面２と平行な平面である。ゲートトレンチ５は、ソース領域１３およびボディ領域１２を貫通して底面４に連なる側面３を有する。側面３は、底面４を含む平面に対して傾斜する。 A plurality of gate trenches 5 are provided in the first main surface 1. The gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and the plurality of gate trenches 5 are arranged in a second direction. The gate trenches 5 have a bottom surface 4 made of the drift region 11. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The gate trenches 5 have side surfaces 3 that penetrate the source region 13 and the body region 12 and are continuous with the bottom surface 4. The side surfaces 3 are inclined with respect to a plane including the bottom surface 4.

　ゲート絶縁膜８１は、側面３および底面４に接する。ゲート絶縁膜８１は、例えば酸化膜である。ゲート絶縁膜８１は、例えば二酸化珪素を含む材料により構成されている。ゲート絶縁膜８１は、底面４においてドリフト領域１１と接する。ゲート絶縁膜８１は、側面３においてソース領域１３、ボディ領域１２およびドリフト領域１１の各々と接する。ゲート絶縁膜８１は、第１主面１においてソース領域１３と接してもよい。 The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts each of the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

　ゲート電極８２は、ゲート絶縁膜８１上に設けられている。ゲート電極８２は、例えば導電性不純物を含むポリシリコンから構成されている。ゲート電極８２は、ゲートトレンチ５の内部に配置されている。 The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5.

　層間絶縁膜８３は、ゲート電極８２およびゲート絶縁膜８１と接する。層間絶縁膜８３は、例えば二酸化珪素を含む材料から構成されている。層間絶縁膜８３およびゲート絶縁膜８１には、第２方向に一定の間隔でコンタクトホール９０が形成されている。コンタクトホール９０は、第２方向で隣り合うコンタクトホール９０の間にゲートトレンチ５が位置するように設けられている。コンタクトホール９０は、第１方向に延びる。コンタクトホール９０を通じて、ソース領域１３およびコンタクト領域１８が層間絶縁膜８３およびゲート絶縁膜８１から露出する。 The interlayer insulating film 83 contacts the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

　ソース電極６０は、第１主面１と接する。ソース電極６０は、コンタクト電極６１と、ソース配線６２とを有する。 The source electrode 60 contacts the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62.

　コンタクト電極６１は、コンタクトホール９０内に設けられている。コンタクト電極６１は、第１主面１において、ソース領域１３およびコンタクト領域１８と接する。コンタクト電極６１は、チタン（Ｔｉ）、アルミニウム（Ａｌ）および珪素（Ｓｉ）を含む材料から構成されている。コンタクト電極６１は、ソース領域１３およびコンタクト領域１８とオーミック接合する。コンタクト電極６１は、コンタクトホール９０を通じて炭化珪素基板１０に接続されている。 The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 contacts the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material including titanium (Ti), aluminum (Al), and silicon (Si). The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The contact electrode 61 is connected to the silicon carbide substrate 10 through the contact hole 90.

　ソース配線６２は、アルミニウムまたは銅（Ｃｕ）を含む材料から構成されている。ソース配線６２は、アルミニウムおよび銅を含む材料から構成されていてもよい。ソース電極６０は、層間絶縁膜８３によりゲート電極８２から電気的に絶縁されている。ソース電極６０が、ソース配線６２と層間絶縁膜８３との間に窒化チタン（ＴｉＮ）膜などのバリアメタル膜を含んでもよい。 The source wiring 62 is made of a material containing aluminum or copper (Cu). The source wiring 62 may be made of a material containing aluminum and copper. The source electrode 60 is electrically insulated from the gate electrode 82 by the interlayer insulating film 83. The source electrode 60 may include a barrier metal film, such as a titanium nitride (TiN) film, between the source wiring 62 and the interlayer insulating film 83.

　ドレイン電極７０は、第２主面２と接する。ドレイン電極７０は、第２主面２において炭化珪素単結晶基板５０と接する。ドレイン電極７０は、ドリフト領域１１と電気的に接続されている。ドレイン電極７０は、コンタクト電極６１と同じ材料により構成されている。ドレイン電極７０は、炭化珪素単結晶基板５０とオーミック接合する。 The drain electrode 70 contacts the second main surface 2. The drain electrode 70 contacts the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of the same material as the contact electrode 61. The drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.

　（炭化珪素基板）
　次に、実施形態に係る炭化珪素半導体装置１００が有する炭化珪素基板１０について説明する。 (Silicon carbide substrate)
Next, silicon carbide substrate 10 included in silicon carbide semiconductor device 100 according to the embodiment will be described.

　図２を参照し、実施形態の第１例に係る炭化珪素基板１０Ａについて説明する。図２は、実施形態の第１例に係る炭化珪素基板１０Ａを示す図である。図２において、左図に炭化珪素基板１０Ａの断面図を示し、右図に炭化珪素基板１０Ａの不純物濃度プロファイルを示す。 With reference to FIG. 2, a silicon carbide substrate 10A according to a first example of an embodiment will be described. FIG. 2 is a diagram showing a silicon carbide substrate 10A according to a first example of an embodiment. In FIG. 2, the left figure shows a cross-sectional view of the silicon carbide substrate 10A, and the right figure shows an impurity concentration profile of the silicon carbide substrate 10A.

　炭化珪素基板１０Ａは、炭化珪素単結晶基板５０と、再結合促進層１９と、ドリフト領域１１とを主に有する。 The silicon carbide substrate 10A mainly includes a silicon carbide single crystal substrate 50, a recombination promotion layer 19, and a drift region 11.

　炭化珪素単結晶基板５０は、例えば窒素などのｎ型不純物を含み、ｎ型を有する。炭化珪素単結晶基板５０のｎ型不純物の実効濃度は、例えば１×１０１８ｃｍ－３以上７×１０１８ｃｍ－３以下である。 Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has an n-type. The effective concentration of the n-type impurity in silicon carbide single crystal substrate 50 is, for example, not less than 1×10 18 cm −3 and not more than 7×10 18 cm −3 .

　再結合促進層１９は、炭化珪素単結晶基板５０の上に設けられている。再結合促進層１９は、第１領域１９ａと、第２領域１９ｂと、第３領域１９ｃとを有する。 The recombination promotion layer 19 is provided on a silicon carbide single crystal substrate 50. The recombination promotion layer 19 has a first region 19a, a second region 19b, and a third region 19c.

　第１領域１９ａは、第２領域１９ｂの上に設けられている。第１領域１９ａは、ドリフト領域１１と接する。第１領域１９ａは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第１領域１９ａのｎ型不純物の実効濃度は、炭化珪素単結晶基板５０のｎ型不純物の実効濃度よりも高い。第１領域１９ａのｎ型不純物の実効濃度は、例えば５×１０１８ｃｍ－３以上２×１０１９ｃｍ－３以下である。 The first region 19a is provided on the second region 19b. The first region 19a is in contact with the drift region 11. The first region 19a contains an n-type impurity such as nitrogen or phosphorus, and has an n-type. The effective concentration of the n-type impurity in the first region 19a is higher than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the first region 19a is, for example, not less than 5×10 18 cm −3 and not more than 2×10 19 cm −3 .

　第２領域１９ｂは、第３領域１９ｃの上に設けられている。第２領域１９ｂは、再結合促進層１９の上面から離隔した位置に設けられている。第２領域１９ｂは、第１領域１９ａと第３領域１９ｃとの間に設けられている。第２領域１９ｂは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。第２領域１９ｂのｎ型不純物の実効濃度は、例えば１×１０１９ｃｍ－３以上である。 The second region 19b is provided on the third region 19c. The second region 19b is provided at a position separated from the upper surface of the recombination promotion layer 19. The second region 19b is provided between the first region 19a and the third region 19c. The second region 19b contains n-type impurities such as nitrogen or phosphorus and has an n-type. The effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a. The effective concentration of the n-type impurity in the second region 19b is, for example, 1×10 19 cm −3 or more.

　第３領域１９ｃは、炭化珪素単結晶基板５０の上に設けられている。第３領域１９ｃは、炭化珪素単結晶基板５０と接する。第３領域１９ｃは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第３領域１９ｃのｎ型不純物の実効濃度は、例えば第１領域１９ａのｎ型不純物の実効濃度と同じである。この場合、第３領域１９ｃは第２領域１９ｂと比較して低濃度である。そのため、炭化珪素単結晶基板５０との格子不整合が小さくなるため欠陥生成を抑制できる。第３領域１９ｃのｎ型不純物の実効濃度は、例えば５×１０１８ｃｍ－３以上２×１０１９ｃｍ－３以下である。 The third region 19c is provided on the silicon carbide single crystal substrate 50. The third region 19c is in contact with the silicon carbide single crystal substrate 50. The third region 19c contains an n-type impurity such as nitrogen or phosphorus and has an n-type. The effective concentration of the n-type impurity in the third region 19c is, for example, the same as the effective concentration of the n-type impurity in the first region 19a. In this case, the third region 19c has a lower concentration than the second region 19b. Therefore, the lattice mismatch with the silicon carbide single crystal substrate 50 is reduced, and thus defect generation can be suppressed. The effective concentration of the n-type impurity in the third region 19c is, for example, 5×10 18 cm −3 or more and 2×10 19 cm −3 or less.

　ドリフト領域１１は、再結合促進層１９の上に設けられている。ドリフト領域１１は、第１領域１９ａと接する。ドリフト領域１１は、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。ドリフト領域１１のｎ型不純物の実効濃度は、例えば１×１０１４ｃｍ－３以上５×１０１６ｃｍ－３以下である。 The drift region 11 is provided on the recombination promotion layer 19. The drift region 11 is in contact with the first region 19a. The drift region 11 contains n-type impurities such as nitrogen or phosphorus and has an n-type. The effective concentration of the n-type impurity in the drift region 11 is, for example, not less than 1×10 14 cm −3 and not more than 5×10 16 cm −3 .

　以上に説明した炭化珪素基板１０Ａ、および炭化珪素基板１０Ａを有する炭化珪素半導体装置１００によれば、再結合促進層１９が、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、再結合促進層１９の最表面の領域（第１領域１９ａ）の不純物濃度が低いので、再結合促進層１９の最表面において積層欠陥が形成されにくい。そのため、再結合促進層１９からドリフト領域１１に積層欠陥が引き継がれることが抑制される。また、再結合促進層１９内に不純物濃度が高い領域（第２領域１９ｂ）が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要な再結合促進層１９の厚みを低減できる。必要な再結合促進層１９の厚みが低減されると、再結合促進層１９を形成する際のエピタキシャル成長に要する時間が短縮され、製造コストが低減される。 According to the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A described above, the recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a. In this case, since the impurity concentration in the outermost region (first region 19a) of the recombination promotion layer 19 is low, stacking faults are unlikely to be formed in the outermost surface of the recombination promotion layer 19. Therefore, stacking faults are prevented from being inherited from the recombination promotion layer 19 to the drift region 11. In addition, since a region (second region 19b) with a high impurity concentration exists in the recombination promotion layer 19, the recombination of carriers is promoted. Therefore, the recombination efficiency is improved and the required thickness of the recombination promotion layer 19 can be reduced. Reducing the required thickness of the recombination promotion layer 19 shortens the time required for epitaxial growth when forming the recombination promotion layer 19, thereby reducing manufacturing costs.

　次に、炭化珪素基板１０Ａの製造方法について説明する。 Next, a method for manufacturing silicon carbide substrate 10A will be described.

　まず、炭化珪素単結晶基板５０を準備する。例えば、炭化珪素単結晶基板５０は、窒素などのｎ型不純物を含み、ｎ型を有する。 First, a silicon carbide single crystal substrate 50 is prepared. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.

　次に、炭化珪素単結晶基板５０の上に再結合促進層１９を形成する。具体的には、炭化珪素単結晶基板５０の上に、窒素またはリンなどのｎ型不純物を添加したエピタキシャル成長により、再結合促進層１９を形成する。次に、再結合促進層１９へのイオン注入を行う。イオン注入により、再結合促進層１９の上面から離隔した位置に第２領域１９ｂが形成される。第２領域１９ｂの形成に伴って、再結合促進層１９の第２領域１９ｂの上に第１領域１９ａが形成され、再結合促進層１９の第２領域１９ｂの下に第３領域１９ｃが形成される。第２領域１９ｂを形成するためのイオン注入においては、例えば窒素またはリンなどのｎ型不純物を注入する。 Next, the recombination promotion layer 19 is formed on the silicon carbide single crystal substrate 50. Specifically, the recombination promotion layer 19 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus. Next, ions are implanted into the recombination promotion layer 19. A second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by the ion implantation. As the second region 19b is formed, a first region 19a is formed on the second region 19b of the recombination promotion layer 19, and a third region 19c is formed below the second region 19b of the recombination promotion layer 19. In the ion implantation to form the second region 19b, for example, an n-type impurity such as nitrogen or phosphorus is implanted.

　次に、再結合促進層１９の上に炭化珪素エピタキシャル層４０を形成する。例えば、炭化珪素エピタキシャル層４０は、窒素などのｎ型不純物を添加したエピタキシャル成長により形成できる。 Next, a silicon carbide epitaxial layer 40 is formed on the recombination promotion layer 19. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of an n-type impurity such as nitrogen.

　次に、炭化珪素エピタキシャル層４０へのイオン注入を行う。例えば、イオン注入により、ボディ領域１２、ソース領域１３およびコンタクト領域１８が形成される。炭化珪素エピタキシャル層４０の残部がドリフト領域１１として機能する。ボディ領域１２またはコンタクト領域１８を形成するためのイオン注入においては、例えばアルミニウムなどのｐ型不純物をイオン注入する。ソース領域１３を形成するためのイオン注入においては、例えばリンなどのｎ型不純物をイオン注入する。 Next, ions are implanted into the silicon carbide epitaxial layer 40. For example, the body region 12, the source region 13, and the contact region 18 are formed by ion implantation. The remaining portion of the silicon carbide epitaxial layer 40 functions as the drift region 11. In the ion implantation for forming the body region 12 or the contact region 18, a p-type impurity such as aluminum is ion implanted. In the ion implantation for forming the source region 13, an n-type impurity such as phosphorus is ion implanted.

　以上により、炭化珪素単結晶基板５０の上に、再結合促進層１９および炭化珪素エピタキシャル層４０がこの順番で形成された炭化珪素基板１０Ａを製造できる。 By the above steps, a silicon carbide substrate 10A can be manufactured in which a recombination promotion layer 19 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ａの製造方法によれば、炭化珪素単結晶基板５０の上に再結合促進層１９を形成した後に、再結合促進層１９へのイオン注入により、再結合促進層１９の上面から離隔した位置に第２領域１９ｂを形成する。第２領域１９ｂの形成に伴って、再結合促進層１９の第２領域１９ｂの上に第１領域１９ａが形成される。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、再結合促進層１９の最表面の領域（第１領域１９ａ）の不純物濃度が低いので、再結合促進層１９の最表面において積層欠陥が形成されにくい。そのため、再結合促進層１９からドリフト領域１１に積層欠陥が引き継がれることが抑制される。また、再結合促進層１９内に不純物濃度が高い領域（第２領域１９ｂ）が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要な再結合促進層１９の厚みを低減できる。必要な再結合促進層１９の厚みが低減されると、再結合促進層１９を形成する際のエピタキシャル成長に要する時間が短縮され、製造コストが低減される。 According to the manufacturing method of the silicon carbide substrate 10A described above, after forming the recombination promotion layer 19 on the silicon carbide single crystal substrate 50, the second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by ion implantation into the recombination promotion layer 19. With the formation of the second region 19b, the first region 19a is formed on the second region 19b of the recombination promotion layer 19. The effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a. In this case, since the impurity concentration in the outermost region (first region 19a) of the recombination promotion layer 19 is low, stacking faults are unlikely to be formed on the outermost surface of the recombination promotion layer 19. Therefore, the transfer of stacking faults from the recombination promotion layer 19 to the drift region 11 is suppressed. In addition, since a region (second region 19b) with a high impurity concentration exists in the recombination promotion layer 19, the recombination of carriers is promoted. This improves recombination efficiency and reduces the required thickness of the recombination promotion layer 19. Reducing the required thickness of the recombination promotion layer 19 shortens the time required for epitaxial growth when forming the recombination promotion layer 19, thereby reducing manufacturing costs.

　図３を参照し、実施形態の第２例に係る炭化珪素基板１０Ｂについて説明する。図３は、実施形態の第２例に係る炭化珪素基板１０Ｂを示す図である。図３において、左図に炭化珪素基板１０Ｂの断面図を示し、右図に炭化珪素基板１０Ｂの不純物濃度プロファイルを示す。 With reference to FIG. 3, a silicon carbide substrate 10B according to a second example of an embodiment will be described. FIG. 3 is a diagram showing a silicon carbide substrate 10B according to a second example of an embodiment. In FIG. 3, the left figure shows a cross-sectional view of the silicon carbide substrate 10B, and the right figure shows an impurity concentration profile of the silicon carbide substrate 10B.

　炭化珪素基板１０Ｂは、再結合促進層１９が、第３領域１９ｃを有しておらず、第１領域１９ａと、第２領域１９ｂとを有する構成において、炭化珪素基板１０Ａと異なる。炭化珪素基板１０Ｂのその他の構成は、例えば炭化珪素基板１０Ａと同じである。以下、炭化珪素基板１０Ａと異なる構成を中心に説明する。 Silicon carbide substrate 10B differs from silicon carbide substrate 10A in that recombination promotion layer 19 does not have third region 19c, but has first region 19a and second region 19b. The rest of the configuration of silicon carbide substrate 10B is the same as, for example, silicon carbide substrate 10A. The following description will focus on the configuration that differs from silicon carbide substrate 10A.

　再結合促進層１９は、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第１領域１９ａは、ドリフト領域１１と接する。第２領域１９ｂは、炭化珪素単結晶基板５０の上に設けられている。第２領域１９ｂは、再結合促進層１９の上面から離隔した位置に設けられている。第２領域１９ｂは、炭化珪素単結晶基板５０と接する。 The recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The first region 19a contacts the drift region 11. The second region 19b is provided on the silicon carbide single crystal substrate 50. The second region 19b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19. The second region 19b contacts the silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ｂ、および炭化珪素基板１０Ｂを有する炭化珪素半導体装置１００によれば、再結合促進層１９が、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、炭化珪素基板１０Ａ、および炭化珪素基板１０Ａを有する炭化珪素半導体装置１００と同様の効果が得られる。 According to the silicon carbide substrate 10B and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10B described above, the recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a. In this case, the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.

　炭化珪素基板１０Ｂは、例えば炭化珪素基板１０Ａと同様の方法で製造できる。炭化珪素基板１０Ｂの製造方法によれば、炭化珪素基板１０Ａの製造方法と同様の効果が得られる。 Silicon carbide substrate 10B can be manufactured, for example, by a method similar to that for silicon carbide substrate 10A. The method for manufacturing silicon carbide substrate 10B provides the same effects as the method for manufacturing silicon carbide substrate 10A.

　図４を参照し、実施形態の第３例に係る炭化珪素基板１０Ｃについて説明する。図４は、実施形態の第３例に係る炭化珪素基板１０Ｃを示す図である。図４において、左図に炭化珪素基板１０Ｃの断面図を示し、右図に炭化珪素基板１０Ｃの不純物濃度プロファイルを示す。 With reference to FIG. 4, a silicon carbide substrate 10C according to a third example of an embodiment will be described. FIG. 4 is a diagram showing a silicon carbide substrate 10C according to a third example of an embodiment. In FIG. 4, the left figure shows a cross-sectional view of the silicon carbide substrate 10C, and the right figure shows an impurity concentration profile of the silicon carbide substrate 10C.

　炭化珪素基板１０Ｃは、再結合促進層１９に代えて、バッファ層２０を有する構成において、炭化珪素基板１０Ａと異なる。炭化珪素基板１０Ｃのその他の構成は、例えば炭化珪素基板１０Ａと同じである。以下、炭化珪素基板１０Ａと異なる構成を中心に説明する。 Silicon carbide substrate 10C differs from silicon carbide substrate 10A in that it has a buffer layer 20 instead of a recombination promotion layer 19. Other configurations of silicon carbide substrate 10C are the same as, for example, silicon carbide substrate 10A. Below, the configurations that differ from silicon carbide substrate 10A will be mainly described.

　炭化珪素基板１０Ｃは、炭化珪素単結晶基板５０と、バッファ層２０と、ドリフト領域１１とを主に有する。 The silicon carbide substrate 10C mainly includes a silicon carbide single crystal substrate 50, a buffer layer 20, and a drift region 11.

　バッファ層２０は、炭化珪素単結晶基板５０の上に設けられている。バッファ層２０は、第４領域２０ａと、第５領域２０ｂと、第６領域２０ｃとを有する。 The buffer layer 20 is provided on a silicon carbide single crystal substrate 50. The buffer layer 20 has a fourth region 20a, a fifth region 20b, and a sixth region 20c.

　第４領域２０ａは、第５領域２０ｂの上に設けられている。第４領域２０ａは、ドリフト領域１１と接する。第４領域２０ａは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第４領域２０ａのｎ型不純物の実効濃度は、炭化珪素単結晶基板５０のｎ型不純物の実効濃度よりも低い。第４領域２０ａのｎ型不純物の実効濃度は、例えば２×１０１７ｃｍ－３以上３×１０１８ｃｍ－３以下である。第４領域２０ａのｎ型不純物の実効濃度は略一定であり、第４領域２０ａとドリフト領域１１との界面においてｎ型不純物の実効濃度が第４領域２０ａの濃度からドリフト領域１１の濃度に急峻に切り替わってよい。この場合、炭化珪素半導体装置１００の抵抗が高くなりにくい。これに対し、第４領域２０ａのｎ型不純物の実効濃度がドリフト領域１１に向かって連続的に低くなる場合、炭化珪素半導体装置１００の抵抗が高くなりやすい。 The fourth region 20a is provided on the fifth region 20b. The fourth region 20a contacts the drift region 11. The fourth region 20a contains an n-type impurity such as nitrogen or phosphorus, and has an n-type. The effective concentration of the n-type impurity in the fourth region 20a is lower than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the fourth region 20a is, for example, 2×10 17 cm −3 or more and 3×10 18 cm −3 or less. The effective concentration of the n-type impurity in the fourth region 20a is approximately constant, and the effective concentration of the n-type impurity at the interface between the fourth region 20a and the drift region 11 may be abruptly switched from the concentration in the fourth region 20a to the concentration in the drift region 11. In this case, the resistance of the silicon carbide semiconductor device 100 is unlikely to be high. In contrast, when the effective concentration of n-type impurities in fourth region 20a continuously decreases toward drift region 11, the resistance of silicon carbide semiconductor device 100 is likely to increase.

　第５領域２０ｂは、第６領域２０ｃの上に設けられている。第５領域２０ｂは、バッファ層２０の上面から離隔した位置に設けられている。第５領域２０ｂは、第４領域２０ａと第６領域２０ｃとの間に設けられている。第５領域２０ｂは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第５領域２０ｂのｎ型不純物の実効濃度は、炭化珪素単結晶基板５０のｎ型不純物の実効濃度よりも高い。第５領域２０ｂのｎ型不純物の実効濃度は、例えば１×１０１９ｃｍ－３以上である。 The fifth region 20b is provided on the sixth region 20c. The fifth region 20b is provided at a position separated from the upper surface of the buffer layer 20. The fifth region 20b is provided between the fourth region 20a and the sixth region 20c. The fifth region 20b contains an n-type impurity such as nitrogen or phosphorus, and has an n-type. The effective concentration of the n-type impurity in the fifth region 20b is higher than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the fifth region 20b is, for example, 1×10 19 cm −3 or more.

　第６領域２０ｃは、炭化珪素単結晶基板５０の上に設けられている。第６領域２０ｃは、炭化珪素単結晶基板５０と接する。第６領域２０ｃは、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。第６領域２０ｃのｎ型不純物の実効濃度は、例えば第４領域２０ａのｎ型不純物の実効濃度と同じである。この場合、第６領域２０ｃは第５領域２０ｂと比較して低濃度である。そのため、炭化珪素単結晶基板５０との格子不整合が小さくなるため欠陥生成を抑制できる。第６領域２０ｃのｎ型不純物の実効濃度は、例えば２×１０１７ｃｍ－３以上３×１０１８ｃｍ－３以下である。 The sixth region 20c is provided on the silicon carbide single crystal substrate 50. The sixth region 20c is in contact with the silicon carbide single crystal substrate 50. The sixth region 20c contains n-type impurities such as nitrogen or phosphorus, and has an n-type. The effective concentration of the n-type impurities in the sixth region 20c is, for example, the same as the effective concentration of the n-type impurities in the fourth region 20a. In this case, the sixth region 20c has a lower concentration than the fifth region 20b. Therefore, the lattice mismatch with the silicon carbide single crystal substrate 50 is reduced, and thus defect generation can be suppressed. The effective concentration of the n-type impurities in the sixth region 20c is, for example, 2×10 17 cm −3 or more and 3×10 18 cm −3 or less.

　ドリフト領域１１は、バッファ層２０の上に設けられている。ドリフト領域１１は、第４領域２０ａと接する。ドリフト領域１１は、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。ドリフト領域１１のｎ型不純物の実効濃度は、例えば１×１０１４ｃｍ－３以上５×１０１６ｃｍ－３以下である。 The drift region 11 is provided on the buffer layer 20. The drift region 11 is in contact with the fourth region 20a. The drift region 11 contains an n-type impurity such as nitrogen or phosphorus and has an n-type. The effective concentration of the n-type impurity in the drift region 11 is, for example, not less than 1×10 14 cm −3 and not more than 5×10 16 cm −3 .

　以上に説明した炭化珪素基板１０Ｃ、および炭化珪素基板１０Ｃを有する炭化珪素半導体装置１００によれば、バッファ層２０が、第４領域２０ａと、第５領域２０ｂとを有する。第４領域２０ａは、第５領域２０ｂの上に設けられている。第５領域２０ｂのｎ型不純物の実効濃度は、第４領域２０ａのｎ型不純物の実効濃度よりも高い。この場合、バッファ層２０の最表面の領域（第４領域２０ａ）の不純物濃度が低いので、バッファ層２０の最表面において積層欠陥が形成されにくい。そのため、バッファ層２０からドリフト領域１１に積層欠陥が引き継がれることが抑制される。また、バッファ層２０内に不純物濃度が高い領域（第５領域２０ｂ）が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要なバッファ層２０の厚みを低減できる。必要なバッファ層２０の厚みが低減されると、バッファ層２０を形成する際のエピタキシャル成長に要する時間が短縮され、製造コストが低減される。 According to the silicon carbide substrate 10C and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10C described above, the buffer layer 20 has a fourth region 20a and a fifth region 20b. The fourth region 20a is provided on the fifth region 20b. The effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a. In this case, since the impurity concentration in the outermost region (fourth region 20a) of the buffer layer 20 is low, stacking faults are unlikely to be formed in the outermost surface of the buffer layer 20. Therefore, stacking faults are prevented from being inherited from the buffer layer 20 to the drift region 11. In addition, since a region (fifth region 20b) with a high impurity concentration exists in the buffer layer 20, carrier recombination is promoted. Therefore, the recombination efficiency is improved and the required thickness of the buffer layer 20 can be reduced. Reducing the required thickness of the buffer layer 20 shortens the time required for epitaxial growth when forming the buffer layer 20, thereby reducing manufacturing costs.

　次に、炭化珪素基板１０Ｃの製造方法について説明する。 Next, a method for manufacturing the silicon carbide substrate 10C will be described.

　まず、炭化珪素単結晶基板５０を準備する。例えば、炭化珪素単結晶基板５０は、窒素などのｎ型不純物を含み、ｎ型を有する。 First, a silicon carbide single crystal substrate 50 is prepared. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.

　次に、炭化珪素単結晶基板５０の上にバッファ層２０を形成する。具体的には、炭化珪素単結晶基板５０の上に、窒素またはリンなどのｎ型不純物を添加したエピタキシャル成長により、バッファ層２０を形成する。次に、バッファ層２０へのイオン注入を行う。イオン注入により、バッファ層２０の上面から離隔した位置に第５領域２０ｂが形成される。第５領域２０ｂの形成に伴って、バッファ層２０の第５領域２０ｂの上に第４領域２０ａが形成され、バッファ層２０の第５領域２０ｂの下に第６領域２０ｃが形成される。第５領域２０ｂを形成するためのイオン注入においては、例えば窒素またはリンなどのｎ型不純物を注入する。 Next, the buffer layer 20 is formed on the silicon carbide single crystal substrate 50. Specifically, the buffer layer 20 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus. Next, ions are implanted into the buffer layer 20. A fifth region 20b is formed at a position separated from the upper surface of the buffer layer 20 by the ion implantation. With the formation of the fifth region 20b, a fourth region 20a is formed on the fifth region 20b of the buffer layer 20, and a sixth region 20c is formed below the fifth region 20b of the buffer layer 20. In the ion implantation to form the fifth region 20b, for example, an n-type impurity such as nitrogen or phosphorus is implanted.

　次に、バッファ層２０の上に炭化珪素エピタキシャル層４０を形成する。炭化珪素エピタキシャル層４０を形成する方法は、炭化珪素基板１０Ａの製造方法において炭化珪素エピタキシャル層４０を形成する方法と同様であってよい。 Next, a silicon carbide epitaxial layer 40 is formed on the buffer layer 20. The method for forming the silicon carbide epitaxial layer 40 may be the same as the method for forming the silicon carbide epitaxial layer 40 in the method for manufacturing the silicon carbide substrate 10A.

　以上により、炭化珪素単結晶基板５０の上に、バッファ層２０および炭化珪素エピタキシャル層４０がこの順番で形成された炭化珪素基板１０Ｃを製造できる。 By the above steps, a silicon carbide substrate 10C can be manufactured in which a buffer layer 20 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ｃの製造方法によれば、炭化珪素単結晶基板５０の上にバッファ層２０を形成した後に、バッファ層２０へのイオン注入により、バッファ層２０の上面から離隔した位置に第５領域２０ｂを形成する。第５領域２０ｂの形成に伴って、バッファ層２０の第５領域２０ｂの上に第４領域２０ａが形成される。第５領域２０ｂのｎ型不純物の実効濃度は、第４領域２０ａのｎ型不純物の実効濃度よりも高い。この場合、バッファ層２０の最表面の領域（第４領域２０ａ）の不純物濃度が低いので、バッファ層２０の最表面において積層欠陥が形成されにくい。そのため、バッファ層２０からドリフト領域１１に積層欠陥が引き継がれることが抑制される。また、バッファ層２０内に不純物濃度が高い領域（第５領域２０ｂ）が存在するので、キャリアの再結合が促進される。そのため、再結合効率を向上し、必要なバッファ層２０の厚みを低減できる。必要なバッファ層２０の厚みが低減されると、バッファ層２０を形成する際のエピタキシャル成長に要する時間が短縮され、製造コストが低減される。 According to the manufacturing method of the silicon carbide substrate 10C described above, after forming the buffer layer 20 on the silicon carbide single crystal substrate 50, the fifth region 20b is formed at a position separated from the upper surface of the buffer layer 20 by ion implantation into the buffer layer 20. With the formation of the fifth region 20b, the fourth region 20a is formed on the fifth region 20b of the buffer layer 20. The effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a. In this case, since the impurity concentration in the outermost region (fourth region 20a) of the buffer layer 20 is low, stacking faults are unlikely to be formed in the outermost surface of the buffer layer 20. Therefore, stacking faults are prevented from being inherited from the buffer layer 20 to the drift region 11. In addition, since a region (fifth region 20b) with a high impurity concentration exists in the buffer layer 20, carrier recombination is promoted. Therefore, the recombination efficiency is improved and the required thickness of the buffer layer 20 can be reduced. Reducing the required thickness of the buffer layer 20 shortens the time required for epitaxial growth when forming the buffer layer 20, thereby reducing manufacturing costs.

　図５を参照し、実施形態の第４例に係る炭化珪素基板１０Ｄについて説明する。図５は、実施形態の第４例に係る炭化珪素基板１０Ｄを示す図である。図５において、左図に炭化珪素基板１０Ｄの断面図を示し、右図に炭化珪素基板１０Ｄの不純物濃度プロファイルを示す。 With reference to FIG. 5, a silicon carbide substrate 10D according to a fourth embodiment will be described. FIG. 5 is a diagram showing a silicon carbide substrate 10D according to a fourth embodiment. In FIG. 5, the left figure shows a cross-sectional view of the silicon carbide substrate 10D, and the right figure shows an impurity concentration profile of the silicon carbide substrate 10D.

　炭化珪素基板１０Ｄは、バッファ層２０が、第６領域２０ｃを有しておらず、第４領域２０ａと、第５領域２０ｂとを有する構成において、炭化珪素基板１０Ｃと異なる。炭化珪素基板１０Ｄのその他の構成は、例えば炭化珪素基板１０Ｃと同じである。以下、炭化珪素基板１０Ｃと異なる構成を中心に説明する。 Silicon carbide substrate 10D differs from silicon carbide substrate 10C in that buffer layer 20 does not have sixth region 20c, but has fourth region 20a and fifth region 20b. Other configurations of silicon carbide substrate 10D are the same as, for example, silicon carbide substrate 10C. The following description will focus on the configurations that differ from silicon carbide substrate 10C.

　バッファ層２０は、第４領域２０ａと、第５領域２０ｂとを有する。第４領域２０ａは、第５領域２０ｂの上に設けられている。第４領域２０ａは、ドリフト領域１１と接する。第５領域２０ｂは、炭化珪素単結晶基板５０の上に設けられている。第５領域２０ｂは、再結合促進層１９の上面から離隔した位置に設けられている。第５領域２０ｂは、炭化珪素単結晶基板５０と接する。 The buffer layer 20 has a fourth region 20a and a fifth region 20b. The fourth region 20a is provided on the fifth region 20b. The fourth region 20a contacts the drift region 11. The fifth region 20b is provided on the silicon carbide single crystal substrate 50. The fifth region 20b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19. The fifth region 20b contacts the silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ｄ、および炭化珪素基板１０Ｄを有する炭化珪素半導体装置１００によれば、バッファ層２０が、第４領域２０ａと、第５領域２０ｂとを有する。第４領域２０ａは、第５領域２０ｂの上に設けられている。第５領域２０ｂのｎ型不純物の実効濃度は、第４領域２０ａのｎ型不純物の実効濃度よりも高い。この場合、炭化珪素基板１０Ｃ、および炭化珪素基板１０Ｃを有する炭化珪素半導体装置１００と同様の効果が得られる。 According to the silicon carbide substrate 10D and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10D described above, the buffer layer 20 has a fourth region 20a and a fifth region 20b. The fourth region 20a is provided on the fifth region 20b. The effective concentration of n-type impurities in the fifth region 20b is higher than the effective concentration of n-type impurities in the fourth region 20a. In this case, the same effects as those of the silicon carbide substrate 10C and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10C can be obtained.

　炭化珪素基板１０Ｄは、例えば炭化珪素基板１０Ｃと同様の方法で製造できる。炭化珪素基板１０Ｄの製造方法によれば、炭化珪素基板１０Ｃの製造方法と同様の効果が得られる。 Silicon carbide substrate 10D can be manufactured, for example, by a method similar to that for silicon carbide substrate 10C. The method for manufacturing silicon carbide substrate 10D provides the same effects as the method for manufacturing silicon carbide substrate 10C.

　図６を参照し、実施形態の第５例に係る炭化珪素基板１０Ｅについて説明する。図６は、実施形態の第５例に係る炭化珪素基板１０Ｅを示す図である。図６において、左図に炭化珪素基板１０Ｅの断面図を示し、右図に炭化珪素基板１０Ｅの不純物濃度プロファイルを示す。 With reference to FIG. 6, a silicon carbide substrate 10E according to a fifth embodiment will be described. FIG. 6 is a diagram showing a silicon carbide substrate 10E according to a fifth embodiment. In FIG. 6, the left figure shows a cross-sectional view of the silicon carbide substrate 10E, and the right figure shows an impurity concentration profile of the silicon carbide substrate 10E.

　炭化珪素基板１０Ｅは、炭化珪素単結晶基板５０と再結合促進層１９との間にバッファ層２１を有する構成において、炭化珪素基板１０Ａと異なる。炭化珪素基板１０Ｅのその他の構成は、例えば炭化珪素基板１０Ａと同じである。以下、炭化珪素基板１０Ａと異なる構成を中心に説明する。 Silicon carbide substrate 10E differs from silicon carbide substrate 10A in that it has a buffer layer 21 between silicon carbide single crystal substrate 50 and recombination promotion layer 19. The rest of the configuration of silicon carbide substrate 10E is the same as, for example, silicon carbide substrate 10A. Below, the configuration that differs from silicon carbide substrate 10A will be mainly described.

　炭化珪素基板１０Ｅは、炭化珪素単結晶基板５０と、バッファ層２１と、再結合促進層１９と、ドリフト領域１１とを主に有する。 The silicon carbide substrate 10E mainly includes a silicon carbide single crystal substrate 50, a buffer layer 21, a recombination promotion layer 19, and a drift region 11.

　バッファ層２１は、炭化珪素単結晶基板５０の上に設けられている。バッファ層２１は、炭化珪素単結晶基板５０と再結合促進層１９との間に設けられている。バッファ層２１は、例えば窒素またはリンなどのｎ型不純物を含み、ｎ型を有する。バッファ層２１のｎ型不純物の実効濃度は、炭化珪素単結晶基板５０のｎ型不純物の実効濃度よりも低い。バッファ層２１のｎ型不純物の実効濃度は、例えば２×１０１７ｃｍ－３以上３×１０１８ｃｍ－３以下である。 The buffer layer 21 is provided on the silicon carbide single crystal substrate 50. The buffer layer 21 is provided between the silicon carbide single crystal substrate 50 and the recombination promotion layer 19. The buffer layer 21 contains an n-type impurity such as nitrogen or phosphorus, and has an n-type. The effective concentration of the n-type impurity in the buffer layer 21 is lower than the effective concentration of the n-type impurity in the silicon carbide single crystal substrate 50. The effective concentration of the n-type impurity in the buffer layer 21 is, for example, not less than 2×10 17 cm −3 and not more than 3×10 18 cm −3 .

　以上に説明した炭化珪素基板１０Ｅ、および炭化珪素基板１０Ｅを有する炭化珪素半導体装置１００によれば、再結合促進層１９が、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、炭化珪素基板１０Ａ、および炭化珪素基板１０Ａを有する炭化珪素半導体装置１００と同様の効果が得られる。 According to the silicon carbide substrate 10E and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10E described above, the recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a. In this case, the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.

　また、炭化珪素基板１０Ｅ、および炭化珪素基板１０Ｅを有する炭化珪素半導体装置１００によれば、炭化珪素単結晶基板５０と再結合促進層１９との間にバッファ層２１を有する。この場合、炭化珪素単結晶基板５０の上にエピタキシャル成長によりバッファ層２１を成長させる際に、炭化珪素単結晶基板５０内に存在する基底面転移が炭化珪素単結晶基板５０とバッファ層２１との界面で貫通刃状転移に転換されやすい。そのため、基底面転移がドリフト領域１１に到達することを抑制できる。その結果、ｐｎ接合に順方向通電を行った際にドリフト領域１１に積層欠陥が拡大することが抑制され、結果としてオン電圧の上昇を抑制できる。 Furthermore, according to the silicon carbide substrate 10E and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10E, the buffer layer 21 is provided between the silicon carbide single crystal substrate 50 and the recombination promotion layer 19. In this case, when the buffer layer 21 is grown by epitaxial growth on the silicon carbide single crystal substrate 50, the basal plane dislocations present in the silicon carbide single crystal substrate 50 are easily converted to threading edge dislocations at the interface between the silicon carbide single crystal substrate 50 and the buffer layer 21. Therefore, the basal plane dislocations can be prevented from reaching the drift region 11. As a result, the expansion of stacking faults in the drift region 11 is prevented when a current is applied in the forward direction to the pn junction, and as a result, the increase in the on-voltage can be prevented.

　次に、炭化珪素基板１０Ｅの製造方法について説明する。 Next, a method for manufacturing the silicon carbide substrate 10E will be described.

　まず、炭化珪素単結晶基板５０を準備する。例えば、炭化珪素単結晶基板５０は、窒素などのｎ型不純物を含み、ｎ型を有する。 First, a silicon carbide single crystal substrate 50 is prepared. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has an n-type.

　次に、炭化珪素単結晶基板５０の上にバッファ層２１を形成する。具体的には、炭化珪素単結晶基板５０の上に、窒素またはリンなどのｎ型不純物を添加したエピタキシャル成長により、バッファ層２１を形成する。 Next, a buffer layer 21 is formed on the silicon carbide single crystal substrate 50. Specifically, the buffer layer 21 is formed on the silicon carbide single crystal substrate 50 by epitaxial growth with the addition of n-type impurities such as nitrogen or phosphorus.

　次に、バッファ層２１の上に再結合促進層１９を形成する。再結合促進層１９を形成する方法は、炭化珪素基板１０Ａの製造方法において再結合促進層１９を形成する方法と同様であってよい。 Next, the recombination promotion layer 19 is formed on the buffer layer 21. The method for forming the recombination promotion layer 19 may be the same as the method for forming the recombination promotion layer 19 in the manufacturing method of the silicon carbide substrate 10A.

　次に、再結合促進層１９の上に炭化珪素エピタキシャル層４０を形成する。炭化珪素エピタキシャル層４０を形成する方法は、炭化珪素基板１０Ａの製造方法において炭化珪素エピタキシャル層４０を形成する方法と同様であってよい。 Next, a silicon carbide epitaxial layer 40 is formed on the recombination promotion layer 19. The method for forming the silicon carbide epitaxial layer 40 may be the same as the method for forming the silicon carbide epitaxial layer 40 in the method for manufacturing the silicon carbide substrate 10A.

　以上により、炭化珪素単結晶基板５０の上に、バッファ層２１および炭化珪素エピタキシャル層４０がこの順番で形成された炭化珪素基板１０Ｅを製造できる。 By the above steps, a silicon carbide substrate 10E can be manufactured in which a buffer layer 21 and a silicon carbide epitaxial layer 40 are formed in this order on a silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ｅの製造方法によれば、炭化珪素単結晶基板５０の上に再結合促進層１９を形成した後に、再結合促進層１９へのイオン注入により、再結合促進層１９の上面から離隔した位置に第２領域１９ｂを形成する。第２領域１９ｂの形成に伴って、再結合促進層１９の第２領域１９ｂの上に第１領域１９ａが形成される。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、炭化珪素基板１０Ａ、および炭化珪素基板１０Ａを有する炭化珪素半導体装置１００と同様の効果が得られる。 According to the manufacturing method of the silicon carbide substrate 10E described above, after forming the recombination promotion layer 19 on the silicon carbide single crystal substrate 50, the second region 19b is formed at a position separated from the upper surface of the recombination promotion layer 19 by ion implantation into the recombination promotion layer 19. As the second region 19b is formed, the first region 19a is formed on the second region 19b of the recombination promotion layer 19. The effective concentration of the n-type impurity in the second region 19b is higher than the effective concentration of the n-type impurity in the first region 19a. In this case, the same effects as those of the silicon carbide substrate 10A and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10A can be obtained.

　また、炭化珪素基板１０Ｅの製造方法によれば、炭化珪素単結晶基板５０の上にバッファ層２１を形成した後に、バッファ層２１の上に再結合促進層１９を形成する。この場合、炭化珪素単結晶基板５０の上にエピタキシャル成長によりバッファ層２１を成長させる際に、炭化珪素単結晶基板５０内に存在する基底面転移が炭化珪素単結晶基板５０とバッファ層２１との界面で貫通刃状転移に転換されやすい。そのため、基底面転移がドリフト領域１１に到達することを抑制できる。その結果、ｐｎ接合に順方向通電を行った際にドリフト領域１１に積層欠陥が拡大することが抑制され、結果としてオン電圧の上昇を抑制できる。 In addition, according to the manufacturing method of silicon carbide substrate 10E, after forming buffer layer 21 on silicon carbide single crystal substrate 50, recombination promotion layer 19 is formed on buffer layer 21. In this case, when buffer layer 21 is grown by epitaxial growth on silicon carbide single crystal substrate 50, basal plane dislocations present in silicon carbide single crystal substrate 50 are likely to be converted to threading edge dislocations at the interface between silicon carbide single crystal substrate 50 and buffer layer 21. Therefore, basal plane dislocations can be prevented from reaching drift region 11. As a result, the expansion of stacking faults in drift region 11 when forward current is applied to the pn junction is prevented, and as a result, an increase in on-voltage can be prevented.

　図７を参照し、実施形態の第６例に係る炭化珪素基板１０Ｆについて説明する。図７は、実施形態の第６例に係る炭化珪素基板１０Ｆを示す図である。図７において、左図に炭化珪素基板１０Ｆの断面図を示し、右図に炭化珪素基板１０Ｆの不純物濃度プロファイルを示す。 With reference to FIG. 7, a silicon carbide substrate 10F according to a sixth embodiment will be described. FIG. 7 is a diagram showing a silicon carbide substrate 10F according to a sixth embodiment. In FIG. 7, the left diagram shows a cross-sectional view of the silicon carbide substrate 10F, and the right diagram shows an impurity concentration profile of the silicon carbide substrate 10F.

　炭化珪素基板１０Ｆは、再結合促進層１９が、第３領域１９ｃを有しておらず、第１領域１９ａと、第２領域１９ｂとを有する構成において、炭化珪素基板１０Ｅと異なる。炭化珪素基板１０Ｆのその他の構成は、例えば炭化珪素基板１０Ｅと同じである。以下、炭化珪素基板１０Ｅと異なる構成を中心に説明する。 Silicon carbide substrate 10F differs from silicon carbide substrate 10E in that recombination promotion layer 19 does not have third region 19c, but has first region 19a and second region 19b. The rest of the configuration of silicon carbide substrate 10F is the same as, for example, silicon carbide substrate 10E. The following description will focus on the configuration that differs from silicon carbide substrate 10E.

　再結合促進層１９は、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第１領域１９ａは、ドリフト領域１１と接する。第２領域１９ｂは、炭化珪素単結晶基板５０の上に設けられている。第２領域１９ｂは、再結合促進層１９の上面から離隔した位置に設けられている。第２領域１９ｂは、炭化珪素単結晶基板５０と接する。 The recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The first region 19a contacts the drift region 11. The second region 19b is provided on the silicon carbide single crystal substrate 50. The second region 19b is provided at a position spaced apart from the upper surface of the recombination promotion layer 19. The second region 19b contacts the silicon carbide single crystal substrate 50.

　以上に説明した炭化珪素基板１０Ｆ、および炭化珪素基板１０Ｆを有する炭化珪素半導体装置１００によれば、再結合促進層１９が、第１領域１９ａと、第２領域１９ｂとを有する。第１領域１９ａは、第２領域１９ｂの上に設けられている。第２領域１９ｂのｎ型不純物の実効濃度は、第１領域１９ａのｎ型不純物の実効濃度よりも高い。この場合、炭化珪素基板１０Ｅ、および炭化珪素基板１０Ｅを有する炭化珪素半導体装置１００と同様の効果が得られる。 According to the silicon carbide substrate 10F and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10F described above, the recombination promotion layer 19 has a first region 19a and a second region 19b. The first region 19a is provided on the second region 19b. The effective concentration of n-type impurities in the second region 19b is higher than the effective concentration of n-type impurities in the first region 19a. In this case, the same effects as those of the silicon carbide substrate 10E and the silicon carbide semiconductor device 100 having the silicon carbide substrate 10E can be obtained.

　炭化珪素基板１０Ｆは、例えば炭化珪素基板１０Ｅと同様の方法で製造できる。炭化珪素基板１０Ｆの製造方法によれば、炭化珪素基板１０Ｅの製造方法と同様の効果が得られる。 Silicon carbide substrate 10F can be manufactured, for example, by a method similar to that for silicon carbide substrate 10E. The manufacturing method for silicon carbide substrate 10F provides the same effects as the manufacturing method for silicon carbide substrate 10E.

　上記の各不純物領域におけるｐ型不純物の実効濃度およびｎ型不純物の実効濃度は、走査型静電容量顕微鏡（ＳＣＭ：Scanning Capacitance Microscope）法または二次イオン質量分析（ＳＩＭＳ：Secondary Ion Mass Spectrometry）法などにより測定可能である。 The effective concentration of p-type impurities and the effective concentration of n-type impurities in each of the above impurity regions can be measured using a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method, for example.

　以上、実施形態について詳述したが、特定の実施形態に限定されるものではなく、請求の範囲に記載された範囲内において、種々の変形および変更が可能である。 Although the embodiments have been described in detail above, the invention is not limited to specific embodiments, and various modifications and variations are possible within the scope of the claims.

１　第１主面
２　第２主面
３　側面
４　底面
５　ゲートトレンチ
１０　炭化珪素基板
１０Ａ　炭化珪素基板
１０Ｂ　炭化珪素基板
１０Ｃ　炭化珪素基板
１０Ｄ　炭化珪素基板
１０Ｅ　炭化珪素基板
１０Ｆ　炭化珪素基板
１１　ドリフト領域
１２　ボディ領域
１３　ソース領域
１８　コンタクト領域
１９　再結合促進層
１９ａ　第１領域
１９ｂ　第２領域
１９ｃ　第３領域
２０　バッファ層
２０ａ　第４領域
２０ｂ　第５領域
２０ｃ　第６領域
２１　バッファ層
４０　炭化珪素エピタキシャル層
５０　炭化珪素単結晶基板
６０　ソース電極
６１　コンタクト電極
６２　ソース配線
７０　ドレイン電極
８１　ゲート絶縁膜
８２　ゲート電極
８３　層間絶縁膜
９０　コンタクトホール
１００　炭化珪素半導体装置 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 10A Silicon carbide substrate 10B Silicon carbide substrate 10C Silicon carbide substrate 10D Silicon carbide substrate 10E Silicon carbide substrate 10F Silicon carbide substrate 11 Drift region 12 Body region 13 Source region 18 Contact region 19 Recombination promotion layer 19a First region 19b Second region 19c Third region 20 Buffer layer 20a Fourth region 20b Fifth region 20c Sixth region 21 Buffer layer 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 90 Contact hole 100 Silicon carbide semiconductor device

Claims (9)

　第１導電型を有する炭化珪素単結晶基板と、
　前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有する炭化珪素エピタキシャル層と、
　前記炭化珪素エピタキシャル層の上に設けられ、前記第１導電型を有するドリフト層と、
　を有し、
　前記炭化珪素エピタキシャル層は、第１領域と、第２領域とを有し、
　前記第１領域は、前記第２領域の上に位置し、
　前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、
　前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い、
　炭化珪素基板。 a silicon carbide single crystal substrate having a first conductivity type;
a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate;
a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer;
having
the silicon carbide epitaxial layer has a first region and a second region;
the first region is located above the second region,
an impurity concentration of the first region is higher than an impurity concentration of the silicon carbide single crystal substrate;
The impurity concentration of the second region is higher than the impurity concentration of the first region.
Silicon carbide substrate. 　前記炭化珪素エピタキシャル層は、前記炭化珪素単結晶基板と前記第２領域との間に設けられる第３領域を有し、
　前記第３領域の不純物濃度は、前記第１領域の不純物濃度と同じである、
　請求項１に記載の炭化珪素基板。 the silicon carbide epitaxial layer has a third region provided between the silicon carbide single crystal substrate and the second region,
The impurity concentration of the third region is the same as the impurity concentration of the first region.
The silicon carbide substrate according to claim 1 . 　前記炭化珪素単結晶基板と前記炭化珪素エピタキシャル層との間に設けられ、前記第１導電型を有するバッファ層を有し、
　前記バッファ層の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低い、
　請求項１または請求項２に記載の炭化珪素基板。 a buffer layer having the first conductivity type and provided between the silicon carbide single crystal substrate and the silicon carbide epitaxial layer;
an impurity concentration of the buffer layer is lower than an impurity concentration of the silicon carbide single crystal substrate;
The silicon carbide substrate according to claim 1 . 　第１導電型を有する炭化珪素単結晶基板と、
　前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有するバッファ層と、
　前記バッファ層の上に設けられ、前記第１導電型を有するドリフト層と、
　を有し、
　前記バッファ層は、第４領域と、第５領域とを有し、
　前記第４領域は、前記第５領域の上に位置し、
　前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、
　前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い、
　炭化珪素基板。 a silicon carbide single crystal substrate having a first conductivity type;
a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate;
a drift layer having the first conductivity type provided on the buffer layer;
having
the buffer layer has a fourth region and a fifth region;
the fourth region is located above the fifth region,
an impurity concentration of the fourth region is lower than an impurity concentration of the silicon carbide single crystal substrate;
an impurity concentration of the fifth region is higher than an impurity concentration of the silicon carbide single crystal substrate;
Silicon carbide substrate. 　前記バッファ層は、前記炭化珪素単結晶基板と前記第５領域との間に設けられる第６領域を有し、
　前記第６領域の不純物濃度は、前記第４領域の不純物濃度と同じである、
　請求項４に記載の炭化珪素基板。 the buffer layer has a sixth region provided between the silicon carbide single crystal substrate and the fifth region,
The impurity concentration of the sixth region is the same as the impurity concentration of the fourth region.
The silicon carbide substrate according to claim 4 . 　第１主面と、前記第１主面と反対の第２主面とを有する炭化珪素基板を備え、
　前記炭化珪素基板は、
　第１導電型を有する炭化珪素単結晶基板と、
　前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有する炭化珪素エピタキシャル層と、
　前記炭化珪素エピタキシャル層の上に設けられ、前記第１導電型を有するドリフト層と、
　を有し、
　前記炭化珪素エピタキシャル層は、第１領域と、第２領域とを有し、
　前記第１領域は、前記第２領域の上に位置し、
　前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、
　前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い、
　炭化珪素半導体装置。 a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface;
The silicon carbide substrate is
a silicon carbide single crystal substrate having a first conductivity type;
a silicon carbide epitaxial layer having the first conductivity type provided on the silicon carbide single crystal substrate;
a drift layer having the first conductivity type provided on the silicon carbide epitaxial layer;
having
the silicon carbide epitaxial layer has a first region and a second region;
the first region is located above the second region,
an impurity concentration of the first region is higher than an impurity concentration of the silicon carbide single crystal substrate;
The impurity concentration of the second region is higher than the impurity concentration of the first region.
Silicon carbide semiconductor devices. 　第１主面と、前記第１主面と反対の第２主面とを有する炭化珪素基板を備え、
　前記炭化珪素基板は、
　第１導電型を有する炭化珪素単結晶基板と、
　前記炭化珪素単結晶基板の上に設けられ、前記第１導電型を有するバッファ層と、
　前記バッファ層の上に設けられ、前記第１導電型を有するドリフト層と、
　を有し、
　前記バッファ層は、第４領域と、第５領域とを有し、
　前記第４領域は、前記第５領域の上に位置し、
　前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、
　前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い、
　炭化珪素半導体装置。 a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface;
The silicon carbide substrate is
a silicon carbide single crystal substrate having a first conductivity type;
a buffer layer having the first conductivity type provided on the silicon carbide single crystal substrate;
a drift layer having the first conductivity type provided on the buffer layer;
having
the buffer layer has a fourth region and a fifth region;
the fourth region is located above the fifth region,
an impurity concentration of the fourth region is lower than an impurity concentration of the silicon carbide single crystal substrate;
an impurity concentration of the fifth region is higher than an impurity concentration of the silicon carbide single crystal substrate;
Silicon carbide semiconductor devices. 　第１導電型を有する炭化珪素単結晶基板の上に、前記第１導電型を有し、前記炭化珪素単結晶基板よりも不純物濃度が高い炭化珪素エピタキシャル層を形成する工程と、
　前記炭化珪素エピタキシャル層へのイオン注入により、前記炭化珪素エピタキシャル層の上面から離隔した位置に前記第１導電型を有する第２領域を形成する工程と、
　前記第２領域を形成する工程の後、前記炭化珪素エピタキシャル層の上に、前記第１導電型を有するドリフト層を形成する工程と、
　を有し、
　前記第２領域の形成に伴って、前記炭化珪素エピタキシャル層の前記第２領域の上に第１領域が形成され、
　前記第１領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高く、
　前記第２領域の不純物濃度は、前記第１領域の不純物濃度よりも高い、
　炭化珪素基板の製造方法。 forming a silicon carbide epitaxial layer having a first conductivity type on a silicon carbide single crystal substrate having the first conductivity type and having a higher impurity concentration than the silicon carbide single crystal substrate;
forming a second region having the first conductivity type at a position spaced from an upper surface of the silicon carbide epitaxial layer by ion implantation into the silicon carbide epitaxial layer;
forming a drift layer having the first conductivity type on the silicon carbide epitaxial layer after the step of forming the second region;
having
a first region is formed on the second region of the silicon carbide epitaxial layer in association with the formation of the second region;
an impurity concentration of the first region is higher than an impurity concentration of the silicon carbide single crystal substrate;
The impurity concentration of the second region is higher than the impurity concentration of the first region.
A method for manufacturing a silicon carbide substrate. 　第１導電型を有する炭化珪素単結晶基板の上に、前記第１導電型を有し、前記炭化珪素単結晶基板よりも不純物濃度が低いバッファ層を形成する工程と、
　前記バッファ層へのイオン注入により、前記バッファ層の上面から離隔した位置に前記第１導電型を有する第５領域を形成する工程と、
　前記第５領域を形成する工程の後、前記バッファ層の上に、前記第１導電型を有するドリフト層を形成する工程と、
　を有し、
　前記第５領域の形成に伴って、前記バッファ層の前記第５領域の上に第４領域が形成され、
　前記第４領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも低く、
　前記第５領域の不純物濃度は、前記炭化珪素単結晶基板の不純物濃度よりも高い、
　炭化珪素基板の製造方法。 forming a buffer layer having a first conductivity type on a silicon carbide single crystal substrate having the first conductivity type and having an impurity concentration lower than that of the silicon carbide single crystal substrate;
forming a fifth region having the first conductivity type at a position spaced from an upper surface of the buffer layer by ion implantation into the buffer layer;
forming a drift layer having the first conductivity type on the buffer layer after the step of forming the fifth region;
having
a fourth region is formed on the fifth region of the buffer layer in association with the formation of the fifth region;
an impurity concentration of the fourth region is lower than an impurity concentration of the silicon carbide single crystal substrate;
an impurity concentration of the fifth region is higher than an impurity concentration of the silicon carbide single crystal substrate;
A method for manufacturing a silicon carbide substrate.
PCT/JP2024/015148 2023-06-08 2024-04-16 Silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide substrate Ceased WO2024252795A1 (en)

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WO2018150861A1 (en) * 2017-02-20 2018-08-23 日立金属株式会社 Silicon carbide laminated substrate and production method therefor
WO2018207394A1 (en) * 2017-05-10 2018-11-15 三菱電機株式会社 Semiconductor device and manufacturing method thereof
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