WO2024253639A1 - Dispositif à semi-conducteur ayant des fils conducteurs à un seul élément couplés aux deux côtés d'une matrice, procédé de formation de celui-ci, et système le comprenant - Google Patents

Dispositif à semi-conducteur ayant des fils conducteurs à un seul élément couplés aux deux côtés d'une matrice, procédé de formation de celui-ci, et système le comprenant Download PDF

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Publication number
WO2024253639A1
WO2024253639A1 PCT/US2023/024511 US2023024511W WO2024253639A1 WO 2024253639 A1 WO2024253639 A1 WO 2024253639A1 US 2023024511 W US2023024511 W US 2023024511W WO 2024253639 A1 WO2024253639 A1 WO 2024253639A1
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WO
WIPO (PCT)
Prior art keywords
lead
die
frame
clip
housing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2023/024511
Other languages
English (en)
Inventor
Barry Lin
Tony Chiu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Priority to PCT/US2023/024511 priority Critical patent/WO2024253639A1/fr
Priority to CN202380099116.2A priority patent/CN121866898A/zh
Priority to EP23940885.9A priority patent/EP4702595A1/fr
Priority to KR1020267000144A priority patent/KR20260040221A/ko
Priority to IL325091A priority patent/IL325091A/en
Priority to TW113119701A priority patent/TW202524723A/zh
Publication of WO2024253639A1 publication Critical patent/WO2024253639A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/464—Additional interconnections in combination with leadframes
    • H10W70/466—Tape carriers or flat leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed

Definitions

  • the disclosure relates to semiconductor devices, and more specifically to an improved arrangement of a chip having a die with leads attached to both surfaces of the die and extending from the housing that encapsulates the die.
  • leads are attached to both surfaces of a die.
  • the attachment of the leads to the die’s conductive pad on the bottom surface can be accomplished by placing a first lead over a conductive pad of the die and forming a conductive connection, for example by soldering. This can be done with multiple leads and per die or dies simultaneously prior to the leads/die(s) being separated from the lead frame. Connection of one or leads to the conductive pad on a second (top) surface of the die is then carried out individually (/.e., typically not at the same time as other second leads are placed and attached) and in a more complex manner as compared to the placing and attaching of the first lead.
  • the second leads may also be multipart.
  • a system that incorporates a controller and one or more such semiconductor devices.
  • a method for manufacturing one or more semiconductor devices includes attaching a first side of each of at least one die to a respective paddle of a lead- frame strip, and attaching a second side of each of the at least one die to a respective paddle of a clip- frame strip.
  • a method for manufacturing one or more semiconductor devices includes attaching a first side of each of at least one die to a respective paddle of a lead- frame strip, and attaching a second side of each of the at least one die to a respective paddle of a clip- frame strip.
  • FIG. 1 A is a view of an NMOS power transistor, according to an embodiment
  • FIG. 1 B is a schematic symbol of the NMOS power transistor of FIG. 1A;
  • FIG. 2 is a cross-sectional transparent side view of a conventional NMOS power transistor
  • FIG. 3 is a cross-sectional transparent side view of an NMOS power transistor, according to an embodiment
  • FIGS. 4A-4C are respective plan views of a lead-frame (LF) strip, a clip-frame (CF) strip, and the CF strip disposed over, and in alignment with, the LF strip, according to an embodiment;
  • LF lead-frame
  • CF clip-frame
  • FIG. 5 is a plan view of an LF strip, according to an embodiment
  • FIG. 6 is a plan view of the LF strip of FIG. 5 with solder formed over the surfaces of the die paddles, according to an embodiment
  • FIG. 7 is a plan view of the LF strip of FIG. 6 with dies disposed over the pre-soldered die paddles, according to an embodiment
  • FIG. 8 is a plan view of the LF strip of FIG. 7 with solder formed over the exposed surfaces of the dies, according to an embodiment
  • FIG. 9 is a plan view of a CF strip aligned with, and disposed over, the LF strip of FIG. 8, and paddles of the CF strip each disposed over an exposed surface of a respective die, according to an embodiment
  • FIG. 10 is the CF strip and LF strip of FIG. 9 with the dies and portions of the leads encapsulated (housings formed), according to an embodiment
  • FIG. 11 is a flow diagram of a method for forming a semiconductor device such as the transistor of FIGS. 1A, 3, and 12, according to an embodiment
  • FIG. 13 is a cross-sectional transparent side view of a packaged NMOS power transistor having the same given footprint as the transistor of FIG. 12 and with an indication of a maximum allowable die size, according to an embodiment; and [0022]
  • FIG. 14 is a schematic diagram of a system that includes one or more of the semiconductor devices of FIGS 1 A, 3, and 12, according to an embodiment.
  • FIG. 1A is an isometric view of packaged semiconductor device, here an NMOS power transistor 100 having a package 102, according to an embodiment.
  • the power transistor 100 is suitable for many applications such as being one of the output transistors of a switching power supply (not shown in FIG. 1A).
  • the package 102 includes an optional drain pad 104, which also can be configured as a heat sink, drain leads 106 coupled to the drain pad 104, source leads 108, a gate lead 110, and a housing 112. At their ends opposite to the optional drain pad 104, the drain leads 106 may be electrically tied together.
  • VGS is greater than Vcs(th) and VDS is greater than VGS - Vcs(th)
  • the NMOS transistor 100 operates in its saturation region, during which the value of IDS is proportional to (VGS - Vcs(th)) 2 (many applications of the NMOS transistor call for configuring circuitry that includes the NMOS transistor such that the NMOS transistor operates in its saturation region).
  • the inherent body diode 130 may conduct a source-to-drain current if the source-to-drain voltage VSD is greater than the body diode’s threshold, or “turn-on,” voltage Vth.
  • the body diode 130 may conduct a source-to-drain current ISD for a relatively brief period during a discharge of a phase inductor of a switching power supply such as a buck converter.
  • FIG. 2 is a cross-sectional transparent side view of a conventional NMOS power transistor 200, which includes a die 202, a lead-frame paddle 204, a first lead 206, a second lead 208 having an internal portion 210 and an external portion 212, and a housing 214.
  • the second lead 208 is placed over, and attached to, a conductive pad (not shown in FIG. 2) on a second side (here a top) of the die 202 individually (i.e., typically not at the same time as other second leads are placed and attached) and in a more complex manner as compared to the placing and attaching of the first lead 206.
  • the internal portion 210 of the second lead 208 is attached (typically soldered) to a conductive pad on the upper side of the die 202. But if the die 202 and internal portion 210 are rotated relative to one another in a plane parallel to the die 202, or are otherwise misaligned, even by a relatively small amount, during the placing and attaching process, the resulting transistor 200 can be rendered unsuitable for use, and, therefore, can be discarded or “failed.”
  • the external portion 212 of the second lead 208 is placed and attached, by soldering or welding, to the internal portion, thus forming an attachment joint 216.
  • the attachment joint 216 is an additional point of potential failure.
  • placing and attaching second leads 208 individually is time consuming and, therefore, reduces the throughput (/.e., the number of semiconductor devices per unit time) of a process for manufacturing the transistor 200.
  • the volume occupied by the attachment joint 216 reduces, within the housing 214, the area available for the die 202 and, therefore, limits the maximum size of a die that the housing can accommodate for a given footprint of the transistor 200.
  • FIG. 3 is a cross-sectional transparent side view of an NMOS power transistor 300, which includes a die 302, a lead-frame paddle 304, a first lead 306, a second lead 308, and a housing 314, according to an embodiment.
  • the second lead 308 which, unlike the second lead 208 of FIG. 2, is a single piece (a single member) attached to a clip frame (not shown in FIG. 3), which facilitates placement of the second lead over a conductive pad (not shown in FIG. 3) on a second side (here a top) of the die 302 and attachment (typically by soldering) of the second lead to a conductive pad (not shown in FIG. 3) on the second side of the die. It is only after placing and attaching of the second lead 308 to the conductive pad on the second side of the die that the second lead is separated from the clip frame. Furthermore, because other second leads also are attached to the clip frame, multiple second leads can be attached to respective conductive pads on the second side of the die at the same time.
  • the second lead 308 is a single member, it can be less prone to causing errors than the multi-member lead 208 of FIG. 2. Furthermore, because the second lead 308 is attached to a clip frame during placing and attaching the second lead to the top side of the die, there can be fewer rotational and other misalignment errors, at least one fewer potential failure point (e.g., because there is no attachment joint such as the joint 216 of FIG. 2), the housing 314 can accommodate a larger die 302 than the housing 214 (FIG. 2), and the process for manufacturing the transistor 300 can be more reliable than the process for manufacturing the transistor 200 of FIG. 2. In addition, because multiple second leads 308 can be attached to the die 302 at the same time, the process for manufacturing the transistor 300 can be faster (/.e., higher throughput), less expensive, and/or less complex than a process for manufacturing the transistor 200 of FIG. 2.
  • the first lead 306 extends from a plane at or near a top (non-mounting) side 307 of the housing 314, bends (upwardly in FIG. 3) at a first bend 306a, has a directed (upwardly in FIG. 3) extension portion 306b, prior to bending outwardly to form a contact area 306c, which is generally aligned with a bottom (mounting) side 309 of the housing 314.
  • the second lead 308a which extends out of an opposite side of the housing 314 from the first lead 306, also includes a first bend 308a (an upward bend in FIG. 3) to extend (upwardly in FIG.
  • FIG. 4A is a plan view of a lead-frame strip 400, according to an embodiment.
  • FIG. 4B is a plan view of a clip-frame strip 402, according to an embodiment.
  • FIG. 4C is a plan view of the clip-frame strip 402 disposed over, and aligned with, the lead-frame strip 400, according to an embodiment.
  • the clip-frame strip 402 is placed over the die-populated lead-frame strip 400 and is aligned with the lead-frame strip using alignment holes or other alignment markings 410.
  • the lead-frame strip 400 and the clip-frame strip 402 are moved toward one another such that the lead-frame strip and the clip-frame strip “sandwich” the dies.
  • paddles 412 of the clip-frame strip 402 contact the tops of the dies (not shown in FIGS. 4A-4C) such that conductive pads on the tops of the dies are conductively coupled (e.g., by soldering) to leads 414 of the clip-frame strip.
  • the dies and portions of the leads 408 and 414 are encapsulated in a housing (not shown in FIGS. 4A-4C, but similar to the housings 1000 of FIG. 10) made from a suitable material, such as epoxy or ceramic, to form semiconductor chips.
  • the semiconductor chips are separated from the lead- and clip-frame strips 400 and 402.
  • the lead-frame and clip-frame strips permit multiple semiconductor chips to be formed simultaneously, the cost, complexity, and/or manufacturing time per chip can be reduced relative to a process in which the leads 208 (FIG. 2) are individually placed and coupled to pads on a semiconductor die.
  • the lead-frame and clip-frame strips 400 and 402 are shown as accommodating twenty-four dies, the lead-frame and clip-frame strips can be configured to accommodate any suitable number of dies, such as thirty two, sixty four, two hundred fifty six, or five hundred twelve.
  • the lead-frame strip can include any suitable number (e.g., twelve, sixteen, thirty two, forty eight, sixty four, seventy two, ninety six, one hundred twenty, one hundred twenty eight, one hundred forty four, one hundred sixty eight, one hundred ninety two, two hundred sixteen, two hundred forty, and two hundred fifty six) of paddles configured to accommodate any suitable number (e.g., twelve, sixteen, thirty two, forty eight, sixty four, seventy two, ninety six, one hundred twenty, one hundred twenty eight, one hundred forty four, one hundred sixty eight, one hundred ninety two, two hundred sixteen, two hundred forty, and two hundred fifty six) of dies.
  • any suitable number e.g., twelve, sixteen, thirty two, forty eight, sixty four, seventy two, ninety six, one hundred twenty, one hundred twenty eight, one hundred forty four, one hundred sixty eight, one hundred ninety two, two hundred sixteen, two hundred forty, and two hundred fifty six
  • FIG. 7 is a plan view of the lead-frame strip 500 of FIG. 6 with dies 700 disposed over the presoldered die paddles 502, according to an embodiment.
  • FIG . 8 is a plan view of the lead-frame strip 500 of FIG. 7 with solder 800 formed over the exposed surfaces of the dies 700, according to an embodiment.
  • FIG. 10 is a plan view of the resulting structure 1002 from the clip-frame strip 900 and the lead- frame strip 500 (not visible in FIG. 10) of FIG. 9 with the dies 700 (not visible in FIG. 10) of FIG. 9 and portions of the leads 504 and 904 being encapsulated in corresponding housings 1000, according to an embodiment.
  • FIG. 11 is a flow diagram 1100 of a method (sometimes called a “semiconductor process” or a “semiconductor manufacturing process”) for forming a semiconductor device such as the transistor 100 of FIG. 1 A, the transistor 300 of FIG. 3, or the transistor 1300 of FIG. 13, according to an embodiment.
  • a method sometimes called a “semiconductor process” or a “semiconductor manufacturing process” for forming a semiconductor device such as the transistor 100 of FIG. 1 A, the transistor 300 of FIG. 3, or the transistor 1300 of FIG. 13, according to an embodiment.
  • the unpopulated lead-frame strip 500 is introduced to the processing line.
  • solder 600 is formed on the die paddles 502 of the lead- frame strip 500.
  • the solder may be printed on conductive pads (not shown in FIG. 6) that are disposed on the paddles 502 and that are respectively coupled to the leads 504.
  • the solder 600 also can act as an adhesive to secure dies (see FIG. 7) to the paddles 502; alternatively, an adhesive separate from the solder can be formed, for example by printing, on portions of the paddles other than the conductive pads.
  • solder printing is a suitable solder-forming technique because it can offer precise control of the volume of solder being deposited onto the paddles 502.
  • circuitry on each of the dies 700 is coupled to a respective set of the leads 504 via the conductive pads of the paddles 502, solder, and the conductive pads of the dies 700.
  • the dies 700 can be secured to the paddles 502 by the solder 600 (e.g., adhesive solder) or by a separate adhesive.
  • solder 800 is formed on the exposed surfaces (upper surfaces in FIG. 8) of the dies 700.
  • the solder 800 may be printed on conductive pads (not shown in FIG. 8) that are disposed on the exposed surfaces of the dies 700 and that are respectively coupled to respective circuitry on the dies.
  • the solder 800 also can act as an adhesive to secure the dies 700 to paddles 902 of the clip-frame strip 900 as described below in conjunction with FIG. 9; alternatively, an adhesive separate from the solder can be formed, for example by printing, on portions of the dies’ upper surfaces other than the conductive pads.
  • solder printing is a suitable solder-forming technique because it can offer precise control of the volume of solder being deposited onto the dies 700.
  • the clip-frame strip 900 is aligned with the lead-frame strip 500.
  • the strips 500 and 900 are aligned by using one or more alignment tools (not shown in FIG. 9) to align the alignment holes or marks 506 with the corresponding alignment holes or marks 906.
  • each of the paddles 902 of the clip-frame strip is aligned with a corresponding one of the paddles 502 (see FIG. 5) of the lead-frame strip 500 and, therefore, is aligned with a corresponding one of the dies 700.
  • each of the dies 700 is effectively “sandwiched” between a corresponding pair of the paddles 502 and 902.
  • the clip-frame strip 900 is moved toward the lead-frame strip 500 while alignment is obtained to attach the paddles 902 of the clip-frame strip to the dies 700.
  • the paddles 902 are attached to the dies 700 such that the solder 800 (FIG. 8) electrically couples conductive pads (not shown in FIG. 9) on the exposed surfaces (the top surfaces in FIG. 9) of the dies to corresponding conductive pads (not shown in FIG. 9) on the die-facing surfaces of the paddles 902, where these paddle conductive pads are electrically coupled to respective sets of the leads 904.
  • the item 1110 can include a solder reflow.
  • circuitry on each of the dies 700 is coupled to a respective set of the leads 904 via the conductive pads of the paddles 902, solder, and the conductive pads on the top surfaces (the surfaces facing the paddles 902) of the dies 700.
  • the paddles 902 can be secured to the dies 700 by the solder 800 (e.g., adhesive solder) or by a separate adhesive.
  • the dies 700 of FIG. 9 are encapsulated with a suitable material to form housings 1000.
  • a suitable material for example, an epoxy or other plastic may be molded (e.g., injection or another type of molding) around the dies 700 to form the housings 1000.
  • the housings may be formed by a ceramic or may be hermetically sealed.
  • the encapsulated dies 700 may each be formed to include a respective conductive plate such as a ground plate or the drain plate 104 of FIG. 1A.
  • the resulting structure 1002 of FIG. 10 is processed postencapsulating.
  • the structure 1002 is de-junked or otherwise cleaned, the exposed portions of the leads 504 and 904 are plated (for example, with tin (Sn)), and the housings 1000 are laser marked (for example with the part number and provider).
  • each set of leads 504 or 904 may be coupled together or may be one solid piece, and may be shaped in a same manner as if the leads are separated from one another.
  • the separated semiconductor components, devices, or chips are tested.
  • the components may be subject to electrical-signal tests such as a JTAG boundary scan or electrical- and heat-stressing tests.
  • the semiconductor components, devices, or chips are sorted based on the results of the tests at item 1118.
  • the semiconductor process described in conjunction with the flow diagram 1100 can yield semiconductor components, devices, or chips (sometimes called “ICs” or “Integrated Circuits”) that are, on a per-chip basis, up to about 40% less expensive to manufacture than counterpart chips manufactured by other processes, and can increase the yield of acceptable ICs by up to about 1 .5%.
  • ICs semiconductor components, devices, or chips
  • FIG. 12 is a cross-sectional transparent side view of a conventional NMOS power transistor 1200 having a die 1202 and manufactured according to an individual-lead-placement process that is similar to the process described above in conjunction with FIG. 2 and that utilizes two-member leads 1204 (indicated along with the overall length), which are similar to the two-member leads 208 of FIG. 2.
  • FIG. 13 is a cross-sectional transparent side view of an NMOS power transistor 1300 having a die 1302 and manufactured according to the process that is described above in conjunction with FIGS. 5-11 and that utilizes single-member leads 1304 (one such lead shown in FIG. 13 and indicated along with the overall length), which are similar to the single-member leads 306 and 308 of FIG. 3.
  • single-member leads 1304 one such lead shown in FIG. 13 and indicated along with the overall length
  • the single member lead 1304 rises upwardly at a first bend 1304a from the top surface of the die 1302, then transitions to an extension portion 1304b, which extends outwardly beyond a housing 1305, and then bends downwardly at a second bend 1304c prior to extending further outwardly at a connection area 1304d, which is generally at about a same level as the lead 1306, which is connected to the bottom surface of the die 1302.
  • the leads 1304 and 1306 provide the same functionality as the lead 1204 and a lead 1206 of the conventional transistor 1200 of FIG. 12.
  • the system 1400 is a single-phase buck-converter power supply, which includes a power-supply controller 1402, a switching circuit 1404, and a filter circuit 1406, and which is configured to provide a regulated output voltage Vout to a load 1408.
  • the controller 1402 can be a conventional power-supply controller, and is configured to receive, as a feedback signal, Vout (or a derivative thereof), and also may be configured to receive, as another feedback signal, Vdrive (or a derivative thereof), depending on the control mode in which the power supply system 1400 is configured to operate. For example, if the controller 1402 employs current-mode control, then the controller may form a current-control loop that receives, as in input, the voltage Vdrive.
  • the controller 1402 is also coupled between n , which powers the controller, and circuit ground.
  • the switching circuit 1404 includes a high-side NMOS transistor 1410 and a low-side NMOS transistor 1412, which are both the same as, or similar to, the NMOS transistor 1300 of FIG. 13.
  • the high-side transistor 1410 has its drain coupled to an input voltage Vn, its gate coupled to receive a control signal Control_Highside from the controller 1402, and its source coupled to an input node 1414 of the filter circuit 1406.
  • the low-side transistor 1412 has its drain coupled to the input node 1414 of the filter circuit 1406, its gate coupled to receive a control signal Control_Lowside from the controller 1402, and its source coupled to circuit ground.
  • the filter circuit 1406 includes an inductor 1416 coupled between the input and output nodes 1414 and 1418 of the filter circuit 1406, and includes a capacitor 1420 coupled between the output node 1418 of the filter circuit and circuit ground.
  • the load 1408 can be any suitable load, such as a microprocessor, microcontroller, or other integrated circuit.
  • the power-supply controller 1402 In operation, the power-supply controller 1402 generates Control_Highside having a level that turns the transistor 1410 “on” and generates Control_Lowside having a level that turns the transistor 1412 “off.”
  • a linearly increasing current Imductor flows from Vm, through the drain-source junction of the “on” transistor 1410, and through the inductor 1416, to the capacitor 1420 and load 1408. Respective components of this linearly increasing current Imductor power the load 1408 and charge the capacitor 1420. [0080] After a period of time, the power-supply controller 1402 generates Control_Highside having a level that turns the transistor 1410 “off’ and generates Control_Lowside having a level that turns the transistor 1412 “on.”
  • a linearly decreasing current Imductor flows from circuit ground, through the source-drain junction of the “on” transistor 1412, and through the inductor 1416, to the capacitor 1420 and load 1408. Respective components of this linearly decreasing current Inductor power the load 1408 and charge the capacitor 1420.
  • the inherent body diode (see FIG. 1 B) of the transistor 1412 may be forward biased and conduct nductor for a period of time before the transistor 1412 is fully “on.”
  • the power-supply controller 1402 thereafter repeats this switching cycle, adjusting the duty cycle of the transistor 1410 in a manner that regulates Vout to a value, such as 1.1 Volts (V), for which the controller 1402 and power supply system 1400 are configured.
  • V 1.1 Volts
  • FIGS. 1A-1 B, 3-11 , and 13-14 alternate embodiments are contemplated.
  • NMOS transistor a PMOS transistor, a bipolar transistor, a BiCMOS transistor, a microcontroller, and/or a microprocessor
  • CMOS transistor a bipolar transistor
  • microcontroller a microcontroller
  • microprocessor a microprocessor
  • the system 1400 can be a power supply other than a single-phase buck converter, for example, a multi-phase buck converter with or without coupled inductors, a boost converter, a buck-boost converter, and/or a flyback converter, can be a current regulator instead of, and/or in addition to, a voltage regulator, and/or can be a system other than a power supply.
  • a single-phase buck converter for example, a multi-phase buck converter with or without coupled inductors, a boost converter, a buck-boost converter, and/or a flyback converter
  • a current regulator instead of, and/or in addition to, a voltage regulator
  • a system other than a power supply for example, a multi-phase buck converter with or without coupled inductors, a boost converter, a buck-boost converter, and/or a flyback converter, can be a current regulator instead of, and/or in addition to, a voltage regulator, and/or can be a

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Abstract

La présente invention concerne un dispositif à semi-conducteur comprenant un boîtier, une matrice disposée dans le boîtier et présentant une première surface et une seconde surface, un premier fil conducteur à un seul élément couplé électriquement à la première surface et s'étendant à travers le boîtier, et un second fil conducteur à un seul élément couplé électriquement à la seconde surface et s'étendant à travers le boîtier. Par comparaison avec les dispositifs à semi-conducteur antérieurs, un tel dispositif à semi-conducteur peut être plus facile, moins cher et/ou plus rapide à fabriquer, et/ou, pour un encombrement donné, peut contenir une matrice semi-conductrice de plus grande taille.
PCT/US2023/024511 2023-06-06 2023-06-06 Dispositif à semi-conducteur ayant des fils conducteurs à un seul élément couplés aux deux côtés d'une matrice, procédé de formation de celui-ci, et système le comprenant Ceased WO2024253639A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/US2023/024511 WO2024253639A1 (fr) 2023-06-06 2023-06-06 Dispositif à semi-conducteur ayant des fils conducteurs à un seul élément couplés aux deux côtés d'une matrice, procédé de formation de celui-ci, et système le comprenant
CN202380099116.2A CN121866898A (zh) 2023-06-06 2023-06-06 具有耦合到管芯的两侧的单构件导电引线的半导体设备、用于形成半导体设备的方法和包含半导体设备的系统
EP23940885.9A EP4702595A1 (fr) 2023-06-06 2023-06-06 Dispositif à semi-conducteur ayant des fils conducteurs à un seul élément couplés aux deux côtés d'une matrice, procédé de formation de celui-ci, et système le comprenant
KR1020267000144A KR20260040221A (ko) 2023-06-06 2023-06-06 다이의 양측에 결합된 단일 부재 전도성 리드를 갖는 반도체 디바이스, 반도체 디바이스를 형성하기 위한 방법, 및 반도체 디바이스를 포함한 시스템
IL325091A IL325091A (en) 2023-06-06 2023-06-06 A semiconductor device having conductive connections of one component connected to both sides of the chip, and a method for forming the semiconductor device, and a system comprising the same
TW113119701A TW202524723A (zh) 2023-06-06 2024-05-28 具有耦合到晶粒兩側之單構件導電引線的半導體裝置、形成半導體裝置的方法及併入半導體裝置的系統

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297729A (ja) * 1998-03-11 1999-10-29 Motorola Inc 半導体パッケ―ジおよびその形成方法
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US20060267165A1 (en) * 2003-06-23 2006-11-30 Sandisk Corporation Method for efficiently producing removable peripheral cards
US20090242977A1 (en) * 2008-03-28 2009-10-01 Kabushiki Kaisha Toshiba Semiconductor device and dc-dc converter
EP2306515A2 (fr) * 1998-06-02 2011-04-06 SILICONIX Incorporated Paquet de puces de circuit imprimé avec des conducteurs directement connectés

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297729A (ja) * 1998-03-11 1999-10-29 Motorola Inc 半導体パッケ―ジおよびその形成方法
EP2306515A2 (fr) * 1998-06-02 2011-04-06 SILICONIX Incorporated Paquet de puces de circuit imprimé avec des conducteurs directement connectés
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
US20060267165A1 (en) * 2003-06-23 2006-11-30 Sandisk Corporation Method for efficiently producing removable peripheral cards
US20090242977A1 (en) * 2008-03-28 2009-10-01 Kabushiki Kaisha Toshiba Semiconductor device and dc-dc converter

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KR20260040221A (ko) 2026-03-24
CN121866898A (zh) 2026-04-14
TW202524723A (zh) 2025-06-16
IL325091A (en) 2026-02-01
EP4702595A1 (fr) 2026-03-04

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