WO2024255890A9 - 校准链路、信号传输链路、集成电路、电磁波器件和设备 - Google Patents

校准链路、信号传输链路、集成电路、电磁波器件和设备 Download PDF

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Publication number
WO2024255890A9
WO2024255890A9 PCT/CN2024/099420 CN2024099420W WO2024255890A9 WO 2024255890 A9 WO2024255890 A9 WO 2024255890A9 CN 2024099420 W CN2024099420 W CN 2024099420W WO 2024255890 A9 WO2024255890 A9 WO 2024255890A9
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WIPO (PCT)
Prior art keywords
signal
link
calibration
main
digital
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2024/099420
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English (en)
French (fr)
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WO2024255890A1 (zh
Inventor
张展
陈嘉澍
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Calterah Semiconductor Technology Shanghai Co Ltd
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Calterah Semiconductor Technology Shanghai Co Ltd
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Priority to KR1020247043520A priority Critical patent/KR20260019370A/ko
Priority to EP24822837.1A priority patent/EP4531310A1/en
Publication of WO2024255890A1 publication Critical patent/WO2024255890A1/zh
Publication of WO2024255890A9 publication Critical patent/WO2024255890A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/12—Monitoring; Testing of transmitters for calibration of transmit antennas, e.g. of the amplitude or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/14—Monitoring; Testing of transmitters for calibration of the whole transmission and reception path, e.g. self-test loop-back
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/35—Details of non-pulse systems
    • G01S7/352—Receivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/35—Details of non-pulse systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/40—Means for monitoring or calibrating
    • G01S7/4004—Means for monitoring or calibrating of parts of a radar system
    • G01S7/4008—Means for monitoring or calibrating of parts of a radar system of transmitters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
    • G01S7/418—Theoretical aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0096—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges where a full band is frequency converted into another full band
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/15—Performance testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the technical field of electromagnetic wave devices, and in particular to a calibration link, a signal transmission link, an integrated circuit, an electromagnetic wave device, and equipment.
  • the frequency difference between the transmitted signal and the echo signal can be used to calculate the distance of the target.
  • the distance information and radial velocity information of the target can be obtained by performing Fourier transform in the fast time and slow time dimensions.
  • the direction of arrival (DOA) of the echo signal reflected by the target can also be measured through multi-antenna technology.
  • the transceiver link In order to improve the parameter estimation performance (such as distance, radial velocity and DoA) of the FMCW radar system, the transceiver link needs to be calibrated and compensated.
  • the traditional calibration method cannot calibrate the RF device in real time because a large number of peripherals are required, and the RF device parameter indicators will change with the change of the environment.
  • the embodiments of the present disclosure provide a calibration link, a signal transmission link, an integrated circuit, an electromagnetic wave device, and an apparatus.
  • a calibration link for a main signal transmission path is used to transmit electromagnetic wave signals
  • the calibration link is integrated in an integrated circuit including the main signal transmission path, and the calibration link is at least connected between the main signal transmission path and the antenna corresponding to the main signal transmission path; wherein: the calibration link can be configured to calibrate the main signal transmission path to obtain calibration information; wherein the main signal transmission path can be configured to perform calibration operations based on the calibration information obtained by the calibration link, wherein the calibrated main signal transmission path transmits electromagnetic wave signals. That is, by integrating the calibration link with the main path, the purpose of real-time calibration is achieved without the need for peripherals.
  • the calibration link calibrates the main signal transmission path before the integrated circuit leaves the factory and in at least one gap between the integrated circuit sending/receiving signals, and performs real-time compensation for the transmitted information based on the calibration information obtained from the last calibration of the calibration link.
  • the signal transmitted by the calibration link is a single-tone signal.
  • the electromagnetic wave signal is a radar signal;
  • the signal transmission main path includes a receiving main path for echo signals and/or a transmitting main path for radio frequency signals
  • the calibration link corresponds to an auxiliary transmitting link corresponding to the receiving main path and/or an auxiliary receiving link corresponding to the transmitting main path
  • the antenna corresponds to a receiving antenna corresponding to the receiving main path and/or a transmitting antenna corresponding to the transmitting main path
  • the auxiliary receiving link is connected between the transmitting main path and the corresponding transmitting antenna, and can be configured to calibrate the radio frequency signal transmitted by the transmitting main path
  • the receiving main path includes The radio frequency unit and the intermediate frequency unit are connected to the receiving antenna in sequence, and correspondingly, the auxiliary transmission link includes at least one of the intermediate frequency auxiliary transmission link corresponding to the intermediate frequency unit and the radio frequency auxiliary transmission link corresponding to the radio frequency unit, wherein the intermediate frequency auxiliary transmission link is connected to the intermediate frequency signal output end of the main receiving path, and can be configured to calibrate the intermediate
  • the auxiliary receiving link includes: a first mixer, which can be configured to mix the received signal using the local oscillator signal used in the receiving operation; a first power amplifier, which can be configured to amplify the signal output by the first mixer; a first filtering unit, which can be configured to filter the received signal to obtain a filtered signal; and a first real-number digital-to-analog converter, which can be configured to convert the digital filtered signal into an analog filtered signal.
  • the calibration link may also include a calibration transmission link corresponding to the auxiliary receiving link; wherein the calibration transmission link may be configured to perform calibration operations on the auxiliary receiving link; correspondingly, the auxiliary transmitting link performs calibration operations based on the calibration information obtained from the calibration receiving link, wherein the calibrated auxiliary receiving link performs calibration operations on the main transmission path.
  • the calibration transmission chain may include: a first signal generator, which can be configured to output a digital original signal; a second real-number digital-to-analog converter, which can be configured to convert the digital original signal into an analog original signal; a second filtering unit, which can be configured to filter the original signal to obtain a filtered signal; a second power amplifier, which can be configured to amplify the filtered signal to obtain an amplified signal; and a second mixer, which can be configured to mix the amplified signal with a local oscillator signal used in the transmission operation.
  • the calibration transmission chain may also include at least one of a second adder and a bandpass filter, wherein: the second adder is connected between the first signal generator and the second real number digital-to-analog converter, and can be configured to compensate for the signal output by the first signal generator based on a leakage signal of the local oscillator signal used by the second mixer; the bandpass filter is connected to the second mixer, and can be configured to filter the signal output by the second mixer and send the filtered signal to the calibration unit.
  • the second adder is connected between the first signal generator and the second real number digital-to-analog converter, and can be configured to compensate for the signal output by the first signal generator based on a leakage signal of the local oscillator signal used by the second mixer
  • the bandpass filter is connected to the second mixer, and can be configured to filter the signal output by the second mixer and send the filtered signal to the calibration unit.
  • the first signal source includes a second signal generator and a digital phase shift module; wherein the second signal generator is configured to generate an initial signal; and the digital phase shift module is configured to perform frequency shifting and/or phase shifting processing on the initial signal using digital orthogonal modulation.
  • the RF auxiliary transmission link can also be connected to the input end of the intermediate frequency unit; wherein: after the intermediate frequency unit completes the calibration operation, the calibrated intermediate frequency unit is used to calibrate the RF auxiliary transmission link; the calibrated RF auxiliary transmission link is used to calibrate the RF unit.
  • the RF auxiliary transmission link may include: a second signal source, which can be configured to output an original signal; a third filtering unit, which can be configured to filter the original signal to obtain a filtered signal; a third power amplifier, which can be configured to amplify the filtered signal to obtain an amplified signal; and a fourth mixer, which can be configured to mix the amplified signal with a local oscillator signal to obtain a desired signal.
  • the RF auxiliary transmission link includes at least one of an orthogonal compensation unit, a second squarer and a third adder, wherein: the orthogonal compensation unit is connected to the second signal source at one end and to the third filtering unit at the other end, and can be configured to compensate for the orthogonal imbalance of the received initial signal when the initial signal output by the second signal source is an orthogonal signal; the second squarer is connected to the signal input end of the intermediate frequency unit, and can be configured to process the signal output by the fourth mixer and output it to the calibrated intermediate frequency unit; the third adder is connected to the second signal source at one end and to the third filtering unit at the other end, and can be configured to compensate for the signal output by the second signal source according to the leakage signal of the local oscillator signal used by the fourth mixer.
  • the orthogonal compensation unit is connected to the second signal source at one end and to the third filtering unit at the other end, and can be configured to compensate for the orthogonal imbalance of the received initial signal when the initial signal output by the second signal source
  • a signal transmission link may include: a main signal transmission path, which can be configured to transmit electromagnetic wave signals; and a calibration link, which is integrated in a device including the main signal transmission path and is used to calibrate the main signal transmission path; wherein the main signal transmission path performs a calibration operation based on calibration information obtained by the calibration link, and wherein the calibrated main signal transmission path performs a transmission operation of electromagnetic wave signals.
  • the calibration link may be the calibration link described above.
  • the main signal transmission path and the calibration link are integrated in the same chip or on the same PCD board or the same PCB board.
  • An integrated circuit has at least two main signal transmission paths and the calibration link mentioned above arranged between the two main transmission paths, wherein the calibration link is shared by the two main signal transmission paths.
  • An electromagnetic wave device may include: a carrier; the integrated circuit mentioned above, which is arranged on the carrier; an antenna, which is arranged on the carrier, or the antenna and the integrated circuit are integrated into a single device and arranged on the carrier; the antenna includes a transmitting antenna and a receiving antenna; wherein the integrated circuit is connected to the antenna for transmitting electromagnetic wave signals and/or receiving electromagnetic wave signals.
  • a user terminal device may include: a device body; and the electromagnetic wave device described above, which is arranged on the device body; wherein the electromagnetic wave device is used for target detection and/or wireless communication to provide reference information for the operation of the device body.
  • the calibration link, signal transmission link, integrated circuit, electromagnetic wave device and equipment of the embodiments of the present disclosure are such that, since the calibration link is integrated into the integrated circuit including the main signal transmission path, the calibration link can perform calibration operations on the main signal transmission path in real time, and the calibration operation of the calibration link may not be affected by changes in the operating environment of the main signal transmission path, so that the main signal transmission path can obtain more accurate calibration information, thereby improving the signal processing performance of the main signal transmission path.
  • FIG. 1A is a simplified schematic diagram of a signal transmission link of an analog phase shifter architecture
  • FIG1B is a simplified schematic diagram of an analog phase shifter in the signal transmission link shown in FIG1A ;
  • FIG2 is a schematic diagram of the structure of a signal transmission link provided by an exemplary embodiment of the present disclosure
  • FIG3 is a waveform diagram of an FMCW transmission signal and an echo signal using sawtooth wave modulation
  • FIG4 is a schematic diagram of the structure of another signal transmission link provided by an exemplary embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a digital phase shifter architecture in a signal transmission link provided by an exemplary embodiment of the present disclosure
  • FIG6 is a schematic diagram of a signal transmission link including a compensation unit provided by an embodiment of the present disclosure
  • FIG7 is a schematic diagram of calibrating a main transmission path using a calibration link according to an embodiment of the present disclosure
  • FIG8 is a schematic diagram of the structure of a signal transceiver link provided by an exemplary embodiment of the present disclosure
  • FIG9 is a schematic diagram of the structure of another signal transceiver link provided by an exemplary embodiment of the present disclosure.
  • FIG10 is a schematic diagram of another transceiver link provided by an embodiment of the present disclosure.
  • FIG11 is a schematic diagram of a transceiver link including TX IQ Mod, RX IQ De-Mod and LO Freq Diff provided in an embodiment of the present disclosure
  • FIG12 is a schematic diagram of a transceiver link based on the structure shown in FIG11 combined with BIST provided by an embodiment of the present disclosure
  • FIG13 is a schematic diagram of a transceiver link including TX IQ Mod, BIST IQ Mod and RX IQ De-Mod provided in an embodiment of the present disclosure
  • FIG14 is a schematic diagram of a transceiver link including an auxiliary circuit and a BIST IQ Mod provided in an embodiment of the present disclosure
  • FIG15 is a schematic diagram of another transceiver link including an auxiliary circuit and a BIST IQ Mod provided in an embodiment of the present disclosure
  • FIG16 is a schematic diagram of the structure of a mixer provided in an embodiment of the present disclosure.
  • FIG21A is a schematic diagram of the structure of a calibration link of a main signal transmission path provided by an embodiment of the present disclosure
  • FIG22B is a schematic diagram of a first connection between a calibration link and a main receiving path provided by an embodiment of the present disclosure
  • FIG23C is a schematic diagram of the structure of the calibration transmission link in FIG22A;
  • FIG25A is a schematic diagram of a first structure of the intermediate frequency auxiliary transmission link in FIG22A;
  • FIG25B is a schematic diagram of a second structure of the intermediate frequency auxiliary transmission link in FIG22A;
  • FIG25C is a schematic diagram of the structure of the radio frequency auxiliary transmission link in FIG22A;
  • FIG25D is another schematic diagram of the structure of the RF-assisted transmission link shown in FIG25C;
  • FIG26 is a schematic diagram of an application of a calibration link corresponding to a receiving main path provided by an embodiment of the present disclosure
  • FIG27A is a schematic diagram of a first application of an intermediate frequency auxiliary transmission link provided by an embodiment of the present disclosure
  • FIG27B is a second application diagram of the intermediate frequency auxiliary transmission link provided in an embodiment of the present disclosure.
  • Radar is an electronic device that uses electromagnetic waves to detect targets.
  • the radar chip transmits a beam through a signal transmission link. When the transmitted beam encounters an obstacle, the echo reflected by the obstacle is received by the receiving antenna and transmitted to the radar chip.
  • the radar chip determines the position, distance, speed and other information of the target relative to the electromagnetic wave emission point.
  • FIG1A is a simplified schematic diagram of a signal transmission link of an analog phase shifter architecture
  • FIG1B is a simplified schematic diagram of an analog phase shifter in the signal transmission link shown in FIG1A
  • a signal generator 11 such as a phase locked loop (PLL) is used to generate a local oscillator (LO) signal (such as a swept frequency signal in the 77 GHz frequency band), which may be, for example, an FMCW signal
  • LO local oscillator
  • the analog phase shifter (Analog PS) 12 performs a phase shift operation on the received LO signal, and then radiates it to a predetermined spatial area through a transmitting antenna 13 to perform operations such as target detection and measurement
  • the corresponding analog phase shifter architecture may be as shown in FIG1B, and its specific phase shift principle may be as shown in the following formula:
  • two signals i.e., LOI and LOQ
  • LOI and LOQ are obtained by performing 0° and 90° phase shifts on the received LO signal (i.e., LOIN), and are fitted into an output signal LOOUT after being amplified by a power amplifier (PA). That is, the output signal LOOUT is phase shifted by ⁇ compared to the LOIN input signal, wherein the value of the phase shift ⁇ is determined by the amplitude A of the two signals LOI and the amplitude B of LOQ.
  • PA power amplifier
  • phase shifter architecture can also be implemented by means of a delay line unit, that is, by using the narrow-band assumption of the signal to perform phase shifting by means of time delay.
  • delay line unit that is, by using the narrow-band assumption of the signal to perform phase shifting by means of time delay.
  • ⁇ is the delay time of the delay line.
  • analog phase shifters Since the above-mentioned analog phase shifters have low phase modulation resolution and accuracy, they cannot meet the current sensor requirements. At the same time, although the phase modulation resolution and accuracy can be improved through calibration, the analog phase shifter needs to be calibrated off-line, which greatly increases the difficulty and complexity of engineering implementation and product mass production. At the same time, analog phase shifters also have serious problems such as large area, high loss, stability and channel coupling.
  • the signal transmission link adopts the analog phase shifter architecture, it has problems such as low phase modulation precision and accuracy. Therefore, it cannot meet the high performance requirements of the vehicle radar system.
  • the embodiment of the present disclosure provides a signal transmission link, which can be applied to a radar system.
  • the signal transmission link may include: a transmitting baseband digital module 201, an IQ digital-to-analog converter (DAC) module 202, a transmitting local oscillator 203, and a transmitting orthogonal modulator 204, wherein: the transmitting baseband digital module 201 may be configured to generate two orthogonal transmitting digital baseband signals and convert the two orthogonal baseband signals into a single signal.
  • DAC digital-to-analog converter
  • the orthogonal transmitting digital baseband signals are respectively sent to the I path and Q path in the IQ digital-to-analog conversion module 202, that is, the digital-to-analog conversion module 202 is configured to convert the two orthogonal transmitting digital baseband signals into two transmitting analog baseband signals; the transmitting local oscillator 203 is configured to provide a transmitting local oscillator signal TX_LO; the transmitting orthogonal modulator 204 is configured to perform frequency shifting and phase shifting operation on the transmitting local oscillator signal TX_LO based on the two transmitting analog baseband signals, so as to form a FMCW RF transmission signal after a predetermined phase shift.
  • the transmitting digital baseband signal provided by the transmitting baseband digital module 201 may include preset phase information; the digital-to-analog conversion module 202 may convert the transmitting digital baseband signal into a transmitting analog baseband signal (e.g., converting the digital signal into an analog signal without changing the phase information) by performing digital-to-analog conversion on the received transmitting digital baseband signal; the transmitting orthogonal modulator 204 may mix the received transmitting analog baseband signal with the transmitting local oscillator signal TX_LO generated by the transmitting local oscillator 203, so as to achieve a preset phase shift operation while frequency shifting the transmitting local oscillator signal based on the transmitting analog baseband signal, so as to form a FMCW RF transmission signal after a predetermined phase shift.
  • the digital-to-analog conversion module 202 may convert the transmitting digital baseband signal into a transmitting analog baseband signal (e.g., converting the digital signal into an analog signal without changing the phase information) by performing digital-to-an
  • the signal transmission link of the embodiment of the present disclosure forms a digital phase shifter architecture by using a transmitting baseband digital module 201, a digital-to-analog conversion module 202 and a transmitting orthogonal modulator 204. Since the baseband signal of the architecture is generated in the digital domain, it has better orthogonality and lower side lobes, so its phase shift phase can be generated very accurately, making the phase modulation accuracy higher, thereby realizing a vehicle-mounted radar system with a high-precision digital phase shifting function, reducing the isolation requirements between antennas, and having the advantages of small link loss, low cost, and no need for offline calibration, and can support more flexible wave transmission schemes, such as high-performance Doppler division multiplexing and frequency division multiplexing, and can support frequency response compensation in the digital domain.
  • the transmitting baseband digital module 201 provides a digital signal
  • the transmitting modulator is set as an orthogonal modulator (IQ Modulator) and the digital-to-analog conversion module 202 is set as an orthogonal digital-to-analog converter (IQ DAC).
  • IQ Modulator orthogonal modulator
  • IQ DAC orthogonal digital-to-analog converter
  • the transmitting local oscillator 203 may be a structure including a phase-locked loop (PLL), which may provide electromagnetic wave (such as laser, microwave, etc.) signals.
  • PLL phase-locked loop
  • the signal transmission link also includes: a power amplifier (PA) 205, wherein: the power amplifier 205 is configured to amplify the power of the phase-shifted RF signal and output the amplified signal to the transmitting antenna.
  • PA power amplifier
  • the signal transmission link further includes: a transmitting antenna 206, wherein: the transmitting antenna 206 is configured to radiate the amplified signal to a preset spatial area.
  • the signal amplified by the power amplifier 205 can be radiated to a preset spatial region through the transmitting antenna 206 which is packaged as an integrated device or externally. That is, the transmitting local oscillator 203, the digital phase shifter and the transmitting antenna 206 can be integrated into a device or can be separate components; for example, the transmitting local oscillator 203 and the digital phase shifter can be integrated into a package to form a SoC chip, while the transmitting antenna 206 can be connected through the peripheral port of the chip and formed on a carrier such as a PCB board.
  • the transmitting antenna 206 can also be integrated into the chip package to form AiP (Antenna in Package) or AoP (Antenna on Package), which has a chip structure with a packaged antenna.
  • AiP Antenna in Package
  • AoP Antenna on Package
  • the bandwidth of the frequency sweep signal is above 2 GHz.
  • the electromagnetic wave of the transmission signal emitted by the transmitting antenna of the frequency modulated continuous wave radar system is a high-frequency frequency modulated continuous wave
  • the echo signal received by the receiving antenna of the frequency modulated continuous wave radar system is the electromagnetic wave reflected/scattered back by the target.
  • FIG3 shows a waveform diagram of an exemplary FMCW transmission signal and an echo signal. As shown in FIG3, the frequencies of the transmission signal and the echo signal change regularly over time.
  • the frequency modulated continuous wave is generally sawtooth-shaped, triangular, etc. The present disclosure takes the sawtooth shape as an example for explanation.
  • the electromagnetic wave within each frequency modulation period T is called a chirp, and the frequency of each Chirp signal increases linearly with time.
  • the bandwidth range B of a chirp is greater than or equal to 2 GHz.
  • the transmitting end digital baseband signal is a single-tone signal
  • the transmitting end local oscillator signal is a swept frequency signal
  • the transmitting end local oscillator 203 may be configured to provide an FMCW signal in a centimeter wave band or a millimeter wave band (such as 3.1 GHz, 24 GHz, 60 GHz, 77 GHz, etc.) in microwaves
  • the transmitting end baseband digital module 201 may be configured to provide a single-tone transmitting end digital baseband signal at the MHz level (for example, 3 MHz to 5 MHz, such as 3 MHz, 4 MHz, 5 MHz, etc.), that is, the digital-to-analog conversion module 202 performs digital-to-analog conversion on the MHz level single-tone transmitting end digital baseband signal to obtain a single-tone transmitting end analog baseband signal in the corresponding frequency range
  • the transmitting end orthogonal modulator 204 may be configured to perform up-mixing or down-mixing operations on the received millimeter wave frequency band FMCW signal based on the received single-tone transmitting end analog baseband signal, so as to realize a preset phase
  • the FMCW signal in the 3.1 GHz frequency band may include a swept frequency signal between 3.1 GHz and 10.6 GHz, such as 7.163-8.812 GHz;
  • the FMCW signal in the 77 GHz frequency band may include a swept frequency signal between 76 GHz and 81 GHz, or swept frequency signals such as 76 GHz to 77 GHz, 77 GHz to 79 GHz, or 79 GHz to 81 GHz.
  • the digital baseband signal at the transmitting end is a swept frequency signal
  • the local oscillator signal at the transmitting end is a single tone signal
  • the transmitting end local oscillator 203 may be configured to provide a single-tone transmitting end local oscillator signal in a centimeter wave band or a millimeter wave band (such as 3.1 GHz, 24 GHz, 60 GHz, 77 GHz, etc.) in microwaves
  • the transmitting end baseband digital module 201 may be configured to provide a MHz (for example, 3 MHz to 5 MHz, such as 3 MHz, 4 MHz, 5 MHz, etc.) level transmitting end digital baseband FMCW signal, that is, the digital-to-analog conversion module 202 performs digital-to-analog conversion on the MHz level transmitting end digital baseband FMCW signal to obtain a transmitting end analog baseband FMCW signal in a corresponding frequency range
  • the transmitting end orthogonal modulator 204 may be configured to perform up-mixing or down-mixing operations on the received single-tone transmitting end local oscillator signal in the centimeter wave band or the millimeter wave band based on
  • the single-tone transmitting local oscillator signal in the 3.1 GHz frequency band can be a single-tone analog signal in a fixed frequency band such as 3.1 GHz, 5 GHz, 6 GHz, 8 GHz, 10.6 GHz, etc.;
  • the single-tone transmitting local oscillator signal in the 77 GHz frequency band can be a single-tone analog signal in a fixed frequency band such as 76 GHz, 77 GHz, 78 GHz, 79 GHz, 80 GHz, 81 GHz, etc.
  • the signal transmission link also includes: a low pass filter (LPF) 207, which is arranged between the digital-to-analog conversion module 202 and the transmitting end orthogonal modulator 204, and is configured to perform low pass filtering on the transmitting end analog baseband signal output by the digital-to-analog conversion module 202 and output it to the transmitting end orthogonal modulator 204.
  • LPF low pass filter
  • the transmitting end baseband digital module 201 generates two orthogonal digital baseband signals, namely, an I digital baseband signal and a Q digital baseband signal, and sends the generated digital baseband signals to the digital-to-analog conversion module 202 (including two identical DACs, namely, IQ DACs) to obtain two analog baseband signals.
  • the two analog baseband signals are then input into the low-pass filter 207 to filter out the out-of-band noise signals, and are orthogonally modulated by the transmitting end orthogonal modulator 204 to obtain the modulated RF signal, which is then radiated out through the power amplifier 205 and the transmitting antenna 206.
  • the signal transmission link may further include a direct digital frequency synthesizer (DDFS) (not shown in FIG. 2 ), which is disposed between the transmitting baseband digital module 201 and the digital-to-analog conversion module 202.
  • the direct digital frequency synthesizer may be configured to implement at least one of a variety of signal waveforms and transmission modes such as CDM (Code-Division Multiplexing), DDM (Doppler Division Multiplexing), TDM (Time-Division Multiplexing), SDM (Space Division Multiplexing), CSD (Circuit Switch Data), and Digital IF (Digital Intermediate Frequency) based on the received source signal, so as to achieve flexible configuration of the signal transmission form and the transmission waveform.
  • CDM Code-Division Multiplexing
  • DDM Doppler Division Multiplexing
  • TDM Time-Division Multiplexing
  • SDM Space Division Multiplexing
  • CSD Circuit Switch Data
  • Digital IF Digital Intermediate Frequency
  • the embodiment of the present disclosure also provides a signal transmission link, which is used in an electromagnetic wave transmitting device.
  • the signal transmission link includes a first signal source 41 and a digital phase shift module 42; wherein the first signal source 41 is configured to generate a first analog signal; and the digital phase shift module 42 is configured to use a digital orthogonal modulation method to frequency shift and/or phase shift the first analog signal to form an FMCW RF transmission signal.
  • the signal transmission link provided by the embodiment of the present disclosure includes a first signal source 41 and a digital phase shift module 42.
  • the first signal source 41 can be configured to provide a first analog signal
  • the digital phase shift module 42 can be configured to generate a phase shift signal in the digital domain.
  • the digital phase shift module 42 can also phase-shift the first analog signal based on the generated phase shift signal to perform a preset phase shift operation on the first analog signal.
  • the first signal source 41 may be a transmitting local oscillator, and the first analog signal may be a transmitting LO signal.
  • the signal transmission chain further includes a power amplifier (not shown in the figure) configured to amplify the FMCW RF transmission signal.
  • the signal transmission link further includes a transmission antenna 43 configured to radiate the power-amplified FMCW RF transmission signal to a predetermined area.
  • the signal transmission link may include a first signal source 41, a digital phase shift module (Digital PS) 42, and a transmitting antenna 43, etc.
  • the first signal source 41 may be configured to provide an LO signal
  • the digital phase shift module 42 may be configured to perform a preset phase shift operation on the received LO signal, so that the phase-shifted LO signal is radiated to a preset spatial region through the transmitting antenna 43.
  • the first signal source 41 may also be a structure including a phase-locked loop PLL, which can provide electromagnetic wave (such as laser, microwave, etc.) signals.
  • the first signal source 41, the digital phase shift module 42 and the transmitting antenna 43 may be integrated into an integrated device, or may be discrete components; for example, the first signal source 41 and the digital phase shift module 42 may be integrated into a package to form a SoC chip, etc., and the transmitting antenna 43 may be connected through the peripheral port of the chip, and formed on a carrier such as a PCB board.
  • the transmitting antenna 43 can also be integrated on the chip package to form AiP or AoP, having a chip structure with a packaged antenna.
  • the digital phase shift module 42 includes a second signal source 423, a digital-to-analog conversion module 422, and a mixer 421 connected in sequence; wherein the second signal source 423 is configured to generate a first digital signal; the digital-to-analog conversion module 422 is configured to convert the first digital signal into a second analog signal; and the mixer 421 is configured to perform frequency shifting and/or phase shifting on the first analog signal based on the second analog signal to form an FMCW RF transmission signal.
  • the digital phase shift module 42 in the embodiment of the present disclosure may include a mixer (Mixer) 421, a digital-to-analog conversion module (i.e., DAC) 422, and a second signal source (e.g., a digital baseband signal source Baseband) 423, etc., that is, the second signal source 423 may be configured to provide a first digital signal; the digital-to-analog conversion module 422 may be configured to perform digital-to-analog conversion on the received first digital signal to convert the first digital signal into a second analog signal; the mixer 421 may be configured to perform a mixing operation on the received second analog signal with the received first analog signal from the first signal source 41, so as to achieve a phase shift operation of setting the above-mentioned first analog signal using the first digital signal.
  • a mixer Memory
  • DAC digital-to-analog conversion module
  • Baseband digital baseband signal source Baseband
  • a swept frequency transmission signal may be provided based on the first signal source 41, and/or a swept frequency first digital signal may be provided based on the second signal source 423, so that after mixing by the mixer 421, a swept frequency continuous wave signal is output.
  • the first signal source 41 can be configured to provide an FMCW signal (i.e., a first analog signal) in a centimeter wave band or a millimeter wave band (such as 3.1 GHz, 24 GHz, 60 GHz, 77 GHz, etc.) in microwaves
  • the second signal source 423 can be configured to provide a first digital signal at the MHz level (e.g., 3MHz to 5MHz, such as 3MHz, 4MHz, 5MHz, etc.), that is, the digital-to-analog conversion module 422 performs digital-to-analog conversion on the first digital signal at the MHz level to obtain a second analog signal in the corresponding frequency range
  • the mixer 421 can be configured to perform up-mixing or down-mixing operations on the received millimeter wave band FMCW signal based on the received second analog signal of a fixed frequency band, so as to realize a preset phase shift operation on the FMCW signal.
  • the centimeter wave signal in the 3.1 GHz frequency band may include 3.1 GHz to 10.6 GHz, such as 3.1 GHz, 5 GHz, 5 GHz, 6 GHz, 8 GHz, 10.6 GHz, etc.;
  • the millimeter wave signal in the 77 GHz frequency band may include 76 GHz to 81 GHz signals, such as 76 GHz to 77 GHz, 77 GHz to 79 GHz, 79 GHz to 81 GHz, etc. swept frequency signals, or 76 GHz, 77 GHz, 78 GHz, 79 GHz, 80 GHz, 81 GHz, etc. fixed frequency band signals.
  • the first digital signal includes two orthogonal transmitting digital baseband signals;
  • the second signal source 423 is a transmitting baseband digital module, and the digital-to-analog conversion module 422 includes two identical digital-to-analog converters;
  • the transmitting baseband digital module is configured to generate two orthogonal transmitting digital baseband signals, and send the two orthogonal transmitting digital baseband signals to a digital-to-analog converter respectively;
  • the digital-to-analog conversion module 422 is configured to convert the two orthogonal transmitting digital baseband signals into two transmitting analog baseband signals.
  • the mixer 421 can be set as an IQ Mixer, and the digital-to-analog conversion module 422 is an IQ DAC.
  • the second signal source 423 can be configured to provide a digital baseband signal source (DDFS) for phase shifting and/or to provide a corresponding source signal as a waveform controller (Waveform Control).
  • DDFS is a phase-adjustable digital baseband signal source that generates a digital baseband signal.
  • the signal transmission link (TX digital phase shifter architecture) of the digital phase shifter architecture may include a digital baseband signal source (Baseband), a direct digital frequency synthesizer (Direct Digital Frequency Synthesizer, referred to as DDFS), an IQ digital to analog converter (Digital to Analog Convertor, referred to as DAC), a low-pass filter (Low-Pass Filter, referred to as LPF), an IQ modulator (IQ modulator/IQ Mixer), a power amplifier (Power Amplifier, PA), etc., that is, the baseband signal source is configured to provide a digital phase shift source signal (that is, the aforementioned first digital signal), and the direct digital frequency synthesizer (Direct Digital Frequency Synthesizer, referred to as DDFS), an IQ digital to analog converter (Digital to Analog Convertor, referred to as DAC), a low-pass filter (Low-Pass Filter, referred to as LPF), an IQ modulator (IQ modulator), a digital baseband
  • the digital frequency synthesizer can be configured to realize at least one of a variety of signal waveforms and wave transmission methods such as CDM (Code-Division Multiplexing), DDM (Doppler Division Multiplexing), TDM (Time-Division Multiplexing), SDM (Space Division Multiplexing), CSD (Circuit Switch Data), Digital IF (Digital Intermediate Frequency) based on the received source signal, so as to realize flexible configuration of signal transmission form and transmission waveform.
  • CDM Code-Division Multiplexing
  • DDM Doppler Division Multiplexing
  • TDM Time-Division Multiplexing
  • SDM Space Division Multiplexing
  • CSD Circuit Switch Data
  • Digital IF Digital Intermediate Frequency
  • the digital phase shifter architecture is configured to generate a baseband signal sequence in the digital domain, and can generate an analog baseband signal (i.e., a second analog signal) through a DAC, and then modulate the transmission signal to a high frequency through an orthogonal mixer, that is, because the baseband signal of the architecture is generated in the digital domain, it has better orthogonality and lower sidelobes, and therefore its phase shift phase can be generated very accurately, resulting in higher phase modulation accuracy.
  • a compensation unit can be added to the signal transmission link to solve the TX IQ imbalance (Imbalance), signal leakage (such as TX LO Leakage) and harmonic distortion (HD) caused by IQ mismatch.
  • TX compensation can be set between the TX DDFS and the IQ DAC to perform calibration and compensation operations on the signal transmission link of the digital phase shifter architecture to achieve an operation to solve at least one of the above problems.
  • the HD caused by the third-order nonlinearity of the baseband can be referred to as HD3.
  • the TX compensation unit may include at least one of a TX LO leakage compensation unit (TX LO leakage compensation), a TX IQ imbalance compensation unit (TX IQ Imbalance compensation) and a TX HD3 compensation unit (TX HD3 compensation), wherein the TX LO leakage compensation unit may be configured to be used for compensation for signal leakage, the TX IQ imbalance compensation unit may be configured to be used for compensation for IQ imbalance, and the TX HD3 compensation unit may be configured to be used for compensation for the above-mentioned HD3.
  • TX LO leakage compensation unit may be configured to be used for compensation for signal leakage
  • TX IQ imbalance compensation unit may be configured to be used for compensation for IQ imbalance
  • TX HD3 compensation unit may be configured to be used for compensation for the above-mentioned HD3.
  • the TX IQ imbalance compensation unit is configured to be used for compensation for at least one of an IQ modulator imbalance (TX IQ Modulator imbalance) and an IQ channel imbalance (IQ channel imbalance).
  • TX IQ Modulator imbalance an IQ modulator imbalance
  • IQ channel imbalance IQ channel imbalance
  • compensation unit includes at least two of the TX LO leakage compensation unit, the TX IQ imbalance compensation unit and the TX HD3 compensation unit, compensation can be performed synchronously (such as in parallel) or sequentially (such as in series) according to actual needs and signal characteristics. As shown in FIG6 , IQ compensation can be performed first, then LO compensation, and finally HD3 compensation.
  • the signal transmission link of the digital phase shifter architecture may also include an error correction module for DAC (TX DAC Board Error Correction) and an AWGN (additive white gaussian noise) module for Gaussian white noise, etc., which are not shown in the figure and can be added or deleted according to actual needs.
  • I in IQ mentioned in the embodiments of the present disclosure can be expressed as the abbreviation of In-Phase (i.e., in-phase)
  • Q can be expressed as the abbreviation of Quadrature (i.e., orthogonal)
  • RF can be expressed as the abbreviation of Radio Frequency (i.e., radio frequency).
  • the compensation operation for IQ Imbalance can be achieved by compensating the conjugate signal of the BB (baseband) signal to reversely cancel the image component, and this compensation operation mode is not affected by the calibration mode of IQ Imbalance.
  • the compensation for LO Leakage can be achieved by adjusting the DC component (i.e., DC bias) of the two IQ paths, and the calibration mode of LO Leakage has no effect on its compensation scheme.
  • the compensation methods of HD3 based on the digital pre-compensation architecture of the digital cubic module and the digital pre-compensation architecture based on the frequency doubling waveform generator module will directly affect the subsequent calibration scheme and subsequent compensation process. Specifically:
  • LO Leakage may be calibrated and compensated first, and then IQ Imbalance may be calibrated under a stable DC bias.
  • the root source of the HD3 problem i.e., the compensation coefficient of HD3
  • the compensation coefficient of HD3 may be calibrated for the two IQ paths based on the results of IQ Imbalance pre-compensation to compensate for the third harmonic distortion.
  • the compensation coefficient of HD3 can be calibrated, and IQ Imbalance can be calibrated and compensated under a stable DC bias; subsequently, the actual waveforms of the IQ and Q signals and the compensation coefficient of HD3 are calculated respectively through the compensation results, and the waveform information of the 3x and 5x frequencies that need to be pre-compensated can be inversely calculated.
  • LO Leakage may be calibrated and compensated first, and then the compensation coefficient of IQ Imbalance may be calibrated through multiple (e.g., three) observations, and then the compensation coefficient at the HD3 mirror position may be calibrated through another observation (e.g., two times); finally, the 3-fold and 5-fold frequency coefficients that need to be pre-compensated may be inversely calculated through the compensation coefficients at the HD3 and HD3 mirror positions.
  • the observations in the disclosed embodiments are used to represent operations such as testing and comparative analysis of different test results.
  • Fig. 7 is a schematic diagram of calibrating the main transmission path using a calibration link provided by an embodiment of the present disclosure.
  • the calibration link is used to calibrate the main transmission path for transmitting radio frequency signals; wherein the main transmission path includes a transmitting unit connected to a transmitting antenna, and the calibration link is integrated into an integrated circuit including the main transmission path; since the calibration link is integrated into the integrated circuit including the main transmission path, the main transmission path can be calibrated in real time, and no external device is required to perform calibration operations on the main transmission path.
  • the calibration link includes a calibration unit, which is connected between the transmitting unit and the transmitting antenna and can be configured to calibrate the radio frequency signal output by the transmitting unit; the transmitting unit can be configured to complete the calibration operation based on the calibration information obtained by the calibration link, wherein the radio frequency signal output by the calibrated transmitting unit is radiated to a predetermined area through the transmitting antenna.
  • the main transmission path may include a phase shift module PS, a power amplifier PA, a power detector PD, etc.
  • the transmission path may adopt the signal transmission link of the digital phase shift architecture (Digital Phase Shifter) described in any embodiment of the present disclosure.
  • the transmission channel can simultaneously support multiple modes such as DDM and FDM (Frequency Division Multiplexing) of multiple antennas, and can also save the calibration operation of the RF phase shifter (Phase Shifter), reduce the isolation and coupling in the phase shift system, and reduce link loss and production costs.
  • DDM and FDM Frequency Division Multiplexing
  • the transmission path of the digital phase shifter architecture can also support RF frequency response (Frequency Response) compensation, IQ imbalance and LO leakage calibration operations in the digital domain.
  • RF frequency response Frequency Response
  • relevant calibration operations can be performed by setting up a calibration link.
  • the calibration unit can calibrate the transmission unit in real time.
  • the operating environment of the calibration unit is the same as that of the transmission unit. Therefore, the calibration operation of the calibration unit may not be affected by the change of the operating environment of the transmission unit, so that the calibration unit can obtain more accurate calibration information, thereby improving the signal processing performance of the transmission unit.
  • the calibration link provided in the embodiment of the present disclosure is integrated into an integrated circuit including the main transmission path, so that the calibration link can perform calibration operations on the main transmission path in real time, and the calibration operation of the calibration link can be unaffected by changes in the operating environment of the main transmission path, so that the main transmission path can obtain more accurate calibration information, thereby improving the signal processing performance of the main transmission path.
  • the embodiment of the present disclosure also provides a signal transceiver link, including a signal transmission link and a signal receiving link, as shown in Figure 8 or Figure 9, the signal transmission link may include: a transmitting baseband digital module 201, a digital-to-analog conversion module 202, a transmitting local oscillator 203 and a transmitting orthogonal modulator 204, wherein: the transmitting baseband digital module 201 is configured to generate two orthogonal transmitting digital baseband signals, and send the generated transmitting digital baseband signals to the digital-to-analog conversion module 202; the digital-to-analog conversion module 202 is configured to convert the transmitting digital baseband signal into a transmitting analog baseband signal; the transmitting local oscillator 203 is configured to provide a transmitting local oscillator signal TX_LO; the transmitting orthogonal modulator 204 is configured to perform a phase shift operation on the transmitting local oscillator signal TX_LO based on the transmitting analog baseband signal to obtain a phase-shifted
  • the signal receiving link may include a receiving end local oscillator 302, a receiving end mixer 303, an analog-to-digital converter (ADC) 304 and a receiving end baseband digital module 305; wherein the receiving end local oscillator 302 is configured to provide a receiving end local oscillator signal; the receiving end mixer 303 is configured to perform a mixing operation on the received echo signal based on the receiving end local oscillator signal to obtain a receiving end analog baseband signal; the analog-to-digital converter 304 is configured to convert the receiving end analog baseband signal into a receiving end digital baseband signal; the receiving end baseband digital module 305 is configured to process the receiving end digital baseband signal to achieve target detection and/or wireless communication, for example, to obtain parameter information of the target such as distance, speed, angle, height and micro-motion characteristics.
  • ADC analog-to-digital converter
  • two ideal I-channel digital baseband signals and Q-channel digital baseband signals generated by the transmitting end baseband digital module 201 can obtain a very ideal complex signal after passing through the digital-to-analog conversion module 202, and the phase of the complex signal can be accurately controlled by the transmitting end baseband digital module 201.
  • the phase information of the radio frequency signal of the signal transmission link can be effectively obtained, so that phase modulation of multiple antennas can be realized.
  • the signal transmission link may further include: a power amplifier 205, wherein the power amplifier 205 is configured to amplify the power of the phase-shifted radio frequency signal and output the amplified signal to the transmission antenna.
  • the signal transmission link may further include: a transmitting antenna 206, wherein the transmitting antenna 206 is configured to radiate the amplified signal to a preset spatial region.
  • the signal receiving link may further include a receiving antenna 301, wherein the receiving antenna 301 is configured to receive an echo signal, where the echo signal is a signal formed when the signal transmitted by the signal transmitting link is reflected and/or scattered by a target object.
  • the local oscillator signal at the receiving end may be a swept frequency signal, or the local oscillator signal at the receiving end may be a single tone signal.
  • the frequency of the TX-LO signal received by the transmitting end orthogonal modulator 204 in the signal transmission link and the frequency of the RX-LO signal received by the receiving end mixer 303 in the signal receiving link may be the same.
  • the signal output by the transmitting end baseband digital module 201 is a sine wave of x MHz
  • the TX-LO signal and the RX-LO signal may both be sine waves of z GHz, wherein x and z are both positive numbers, generally between 0 and 1000.
  • the signal transmission link can have two wave transmission schemes: 1) the transmitting end local oscillator signal is swept, and the transmitting end digital baseband signal is single-tone; 2) the transmitting end local oscillator signal is single-tone, and the transmitting end digital baseband signal is swept.
  • the transmitting end local oscillator signal TX_LO, the transmitting end digital baseband signal, and the modulated transmission signal are represented by TLO(t), BB(t) and TX(t), respectively, and the subscripts I and q are used to represent the I-path signal and the Q-path signal, and the superscript a is used to represent its complex signal form, then under the two wave transmission schemes, the signals at each stage of the signal transmission link can be expressed as follows:
  • fbb is the starting frequency of the digital baseband signal at the transmitting end
  • ftlo is the starting frequency of the local oscillator signal at the transmitting end
  • RLO(t) the receiving end local oscillator signal RX_LO in the signal receiving link shown in FIG8.
  • RLO(t) the receiving end local oscillator signal RX_LO in the signal receiving link shown in FIG8.
  • ⁇ represents the time delay of the RF signal transmitted by the signal transmission link and returned to the signal receiving link after being reflected/scattered by the target.
  • the receiving antenna 301 can be connected through the peripheral port of the chip and formed on a carrier such as a PCB board.
  • the receiving antenna can also be integrated on the chip package to form AiP or AoP, that is, a chip structure with a packaged antenna.
  • the signal receiving link may further include a low noise amplifier (Low Noise Amplifier, LNA) 306, which is disposed between the receiving antenna 301 and the receiving end mixer 303, and performs low noise amplification on the echo signal received by the receiving antenna 301 before sending it to the receiving end mixer 303.
  • LNA Low Noise Amplifier
  • the signal receiving link may further include a low pass filter (LPF) 307 and a high pass filter (HPF) 308 connected in series, which are arranged between the receiving mixer 303 and the analog-to-digital converter 304.
  • the low pass filter 307 and the high pass filter 308 constitute a bandpass filter for filtering out-of-band noise.
  • the receiving mixer 303 may be a real mixer
  • the analog-to-digital converter 304 may be a real analog-to-digital converter.
  • the signal transmission link adopts a digital phase-shifting architecture
  • the signal receiving link may include a receiver of an orthogonal receiving architecture or a non-orthogonal receiving architecture. Therefore, it can effectively be compatible with sensors of receiving links of various architectures, effectively reducing the development cost of the entire transceiver link system.
  • the receiving mixer 303 may be an orthogonal mixer
  • the analog-to-digital converter 304 may be an orthogonal analog-to-digital converter.
  • the embodiment of the present disclosure adjusts the receiving mixer 303 in the signal receiving link to an IQ demodulator (IQ Demodulator), and adjusts the analog-to-digital converter 304 to an IQ ADC.
  • the echo signal received by the receiving antenna is processed by the above-mentioned low-noise amplifier 306, receiving mixer 303, low-pass filter 307, high-pass filter 308 and analog-to-digital converter 304 in sequence, and then converted into an IQ digital baseband signal.
  • the subsequent receiving baseband digital module 305 processes the IQ digital baseband signal to obtain parameter information of the target such as distance, speed, angle, altitude and micro-motion characteristics (i.e., micro-Doppler).
  • the receiving end local oscillator signal RX_LO can be expressed as:
  • the local oscillator signal at the receiving end of the signal receiving link may be a single tone signal as shown in formula (12) or formula (13) in addition to being a frequency sweep signal as shown in formula (9) or formula (11).
  • the receiving end mixer 303 is an orthogonal mixer:
  • the local oscillator signal at the receiving end is a single-tone signal
  • the embodiments of the present disclosure can expand various system-level technical solutions according to the combination of different transmission schemes and receiving schemes (for example, whether the transmitting end uses a digital baseband signal single tone, a local oscillator signal sweep frequency or a digital baseband signal sweep frequency, a local oscillator signal single tone; whether the receiving end uses a real mixer, a real analog-to-digital converter or an orthogonal mixer, an orthogonal analog-to-digital converter; whether the receiving end uses a single-tone local oscillator signal or a swept frequency local oscillator signal).
  • Figure 10 is a schematic diagram of another transceiver link provided in an embodiment of the present disclosure
  • Figure 11 is a schematic diagram of a transceiver link including TX IQ Mod, RX IQ De-Mod and LO Freq Diff provided in an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of a transceiver link based on the structure shown in Figure 11 combined with BIST provided in an embodiment of the present disclosure
  • Figure 13 is a schematic diagram of a transceiver link including TX IQ Mod, BIST IQ Mod and RX IQ De-Mod provided in an embodiment of the present disclosure.
  • a transceiver link may include a transmitting link and a receiving link, etc.
  • the transmitting link i.e., the transmitter
  • the transmitting link may include a digital baseband signal source (Baseband), a direct digital frequency synthesizer (TXDDFS), an IQ digital-to-analog converter (IQ DAC), a low-pass filter (LPF), an IQ modulator (IQ Modulator), a power amplifier (PA), etc., which are connected in sequence.
  • the signal amplified by the power amplifier is radiated to a preset spatial area through a transmitting antenna.
  • the receiving link may include a low noise amplifier (LNA), a real mixer (Real Mixer), a trans-impedance amplifier (TIA), a low-pass filter (LPF), a high-pass filter (HPF), a real digital-to-analog converter (Real ADC), etc. connected in sequence. That is, the echo signal received by the receiving antenna is processed by the above-mentioned LNA, Real Mixer, TIA, LPF, HPF and Real ADC in sequence and converted into a real digital baseband signal.
  • the subsequent digital signal processing module processes the real digital baseband signal to obtain parameter information of the target such as distance, speed, angle, height and micro-motion characteristics.
  • the frequency of the TX-LO signal received by the IQ modulator in the transmitting link and the RX-LO signal received by the Real Mixer in the receiving link can be the same.
  • the signal output by the Baseband is a sine wave of x MHz
  • the TX-LO signal and the RX-LO signal can both be sine waves of z GHz.
  • the transmitting link adopts a digital phase-shifting architecture
  • the receiving link may adopt components of an analog architecture, i.e., IQ components are not required. Therefore, the sensor of the receiving link of the analog architecture can be effectively compatible, thereby effectively reducing the development cost of the entire transceiver link system.
  • the receiving link may include a receiving antenna, that is, the receiving antenna may be connected through a peripheral port of the chip and formed on a carrier such as a PCB board.
  • the receiving antenna may also be integrated on the chip package to form AiP or AoP, that is, a chip structure with a packaged antenna.
  • the transceiver link shown in FIG11 may include a transmitting link architecture and a receiving link similar to that in FIG10 (in order to avoid redundancy, the same parts are not described here in detail), and the Real Mixer in the receiving link in FIG10 is adjusted to an IQ demodulator (IQ Demodulator), and the Real ADC is adjusted to an IQ ADC.
  • IQ Demodulator IQ Demodulator
  • the receiving link may include a low noise amplifier LNA), an IQ Demodulator (IQ Demodulator), transimpedance amplifier (TIA), low-pass filter (LPF), high-pass filter (HPF), IQ digital-to-analog converter (IQADC), etc., that is, the echo signal received by the receiving antenna is processed by the above-mentioned LNA, IQ Demodulator, TIA, LPF, HPF and IQ ADC in sequence and converted into an IQ digital baseband signal.
  • the subsequent digital signal processing module processes the IQ digital baseband signal to obtain parameter information of the target such as distance, speed, angle, altitude and micro-motion characteristics (i.e. micro-Doppler).
  • the transmitting link when performing self-calibration based on the transceiver link shown in FIG11, as long as the signal output port of the transmitting link is directly connected to the signal input port of the receiving link through a transmission line, that is, the transmitting link directly sends the transmitting signal to the receiving link through the transmission line, so as to realize the self-calibration operation of the receiving and/or transmitting link without passing through the transmitting antenna and the receiving antenna.
  • the transmitting link directly sends the transmitting signal to the receiving link through the transmission line, so as to realize the self-calibration operation of the receiving and/or transmitting link without passing through the transmitting antenna and the receiving antenna.
  • the TX-LO signal can be a sine wave of z GHz.
  • the RX-LO signal is converted into a digital signal after being processed by the down-mixer (i.e., the IQ Demodulator in the receiving link), low-pass filtering, and high-pass filtering, so as to perform TX IQ imbalance calibration.
  • the transmitting link (the Transmitter, TX, shown in the figure) can be calibrated by adding a receiving link (the Receiver, RX shown in the figure), and the TXIQ imbalance compensation unit in the transmitting link performs compensation operations based on the calibrated data.
  • the transmitting link (the Transmitter, TX, shown in the figure) can also be calibrated by multiplexing the receiving link (the Receiver, RX shown in the figure) actually used for signal transmission and reception, and the TX IQ imbalance compensation unit in the transmitting link and/or receiving link performs compensation operations based on the calibrated data.
  • FIG. 11 is a signal link for TX IQ imbalance.
  • the TX IQ imbalance compensation unit in FIG. 11 can be replaced by a TX HD3 compensation unit to solve the TX HD3 problem. Similar implementations can also be performed in other embodiments. For the sake of simplicity, they will not be described in detail later.
  • the RX-LO port of the IQ Demodulator of the receiving link shown in FIG11 is provided with an internal self-test module (Built-in Self-Test, referred to as BIST) module, that is, as shown in FIG12, based on the transceiver link structure shown in FIG11, the IQ BIST architecture is provided at the RX-LO port of the IQ Demodulator of the receiving link, so as to input an LO signal with a preset frequency deviation at the RX-LO port of the IQ Demodulator of the receiving link.
  • BIST Bust-in Self-Test
  • the IQ BIST composed of a phase angle converter and an IQ modulator (IQ Modulator) uses the received TX-LO signal through the phase angle converter through the IQ modulator, and forms a frequency-deviation signal based on the frequency deviation signal of another input signal BIST-LO of the IQ modulator to input the frequency-deviation signal to the RX-LO port of the IQ Demodulator.
  • the TX-LO signal is a z GHz sine wave
  • the BIST-LO signal is a y MHz sine wave
  • the frequency-shifted signal input to the RX-LO port of the IQ Demodulator is (z GHz - y MHz).
  • x, y, and z are all schematic values, and the specific values may be the same or different.
  • the transmit link of the digital phase shifter architecture can also be calibrated by multiplexing the receive link in the transceiver link; wherein, in other embodiments, the calibration operation of the transmit link using the receive link, and the calibration operation of the receive link using the transmit link, can be implemented by multiplexing the corresponding receive link or transmit link in the link that actually performs signal transmission and reception, and can also be implemented by adding a corresponding calibration receive link or calibration transmit link to implement the calibration operation of the corresponding transmit link or receive link in the link that actually performs signal transmission and reception.
  • the IQBIST may include a phase angle converter and an IQ modulator (IQ Modulator).
  • the phase angle converter is used to realize the separate calibration of the I and Q paths in the transmit link of the digital architecture, while the other input signal BIST-LO of the IQ modulator may be a y MHz sine wave, which is used to simulate the characteristics related to the echo signal formed by the reflection of the transmit signal by the target.
  • x, y, and z are all positive numbers, and x ⁇ y ⁇ z, which can generally be between 0 and 1000.
  • a TX IQ imbalance compensation unit (TX IQ Imbalance Compensation) may be set in the transmitting link (for example, between TXDDFS and IQ DAC), and/or a TX IQ imbalance compensation unit (TX IQ Imbalance Compensation) may be set in the receiving link (for example, after Real ADC), so that the transmitted and/or received signals can be supplemented based on the calibration parameters (or coefficients) obtained by the above self-calibration operation to solve problems such as IQ imbalance.
  • TX IQ Imbalance Compensation may be set in the transmitting link (for example, between TXDDFS and IQ DAC), and/or a TX IQ imbalance compensation unit (TX IQ Imbalance Compensation) may be set in the receiving link (for example, after Real ADC), so that the transmitted and/or received signals can be supplemented based on the calibration parameters (or coefficients) obtained by the above self-calibration operation to solve problems such as IQ imbalance.
  • the above-mentioned IQ BIST module may be disposed between the signal output port of the transmitting link and the signal input port of the receiving link, that is, the transmitting link directly sends the transmitting signal to the receiving link through the IQ BIST module, so as to realize self-calibration operation of the receiving link and/or the transmitting link without passing through the transmitting antenna and the receiving antenna.
  • TX IQ Imbalance compensation TX IQ Imbalance compensation
  • TXLO leakage compensation TXLO leakage compensation
  • TXHD3 compensation HD3 compensation unit
  • Figure 14 is a schematic diagram of a transceiver link including an auxiliary circuit and a BIST IQ Mod provided in an embodiment of the present disclosure
  • Figure 15 is a schematic diagram of another transceiver link including an auxiliary circuit and a BIST IQ Mod provided in an embodiment of the present disclosure.
  • a transceiver link may include a transmitting link, a receiving link, and a calibration link.
  • the transmitting link may include a TX digital baseband signal source (TX Baseband), a direct digital frequency synthesizer (TX DDFS), a compensation unit (Compensation), an IQ digital-to-analog converter (IQDAC), a low-pass filter (LPF), an IQ modulator (IQ Modulator), and a power amplifier (PA), etc., which are connected in sequence.
  • the signal amplified by the power amplifier is radiated to a preset spatial area through a transmitting antenna.
  • a calibration module may be provided between the transmitting link and the receiving link, and the calibration compensation unit may be configured to multiplex the receiving link to perform operations such as calibration on the transmitting link of the above-mentioned digital phase shifter architecture.
  • the compensation unit may be based on the parameters or coefficients obtained by the calibration operation of the calibration module to implement compensation operations on the transmitting signal at the transmitting link end.
  • a corresponding receiving compensation unit may be provided in the receiving link simultaneously or separately, that is, at this time, the receiving compensation unit may be based on the parameters or coefficients obtained by the above-mentioned calibration operation to implement compensation for the echo signal at the receiving link end.
  • the intermediate frequency signal is then input to a preset node in the receiving link to implement the calibration operation in the transmitting link.
  • the auxiliary circuit unit may be an orthogonal demodulator circuit, and the output end of the auxiliary circuit unit may be connected to any node among the nodes between the TIA and the HPF, the HPF and the VGA, and the VGA and the Real ADC in the receiving link.
  • the I and Q branches may be respectively connected to different transmitting links, as shown in FIG14, that is, the transmitting link is calibrated by multiplexing two receiving links.
  • the compensation units such as the LO compensation unit (TX LO leakage compensation), the IQ compensation unit (TX IQ Imbalance compensation) and/or the HD3 compensation unit (TX HD3 compensation) in the above-mentioned compensation module (TX compensation) may be used to implement compensation operations corresponding to the problems of LO leakage, IQ Imbalance and HD3 in the transmitting link of the digital phase shifter architecture based on the parameters obtained by calibration.
  • the above-mentioned BIST unit may include a phase angle converter and an IQ modulator (IQ Modulator) connected in sequence
  • the auxiliary circuit unit may include an LNA, an IQ De-Modulator and a TIA connected in sequence, that is, the phase angle converter receives the RF signal output from the transmission link, and one input end of the IQ Modulator is connected to the output end of the phase angle converter, and the other input end receives the BIST-LO signal of y MHz to generate a preset echo signal.
  • the LNA sends the received echo signal to an input end of the IQ De-Modulator after amplification, and the other input end of the IQ De-Modulator is used to receive the RX-LO signal of z GHz.
  • the two output branches of the IQ De-Modulator i.e., the I branch and the Q branch
  • the TX LO signal can be used as a single tone signal for point-by-point calibration; at the same time, the TXLO signal can also be used as a swept frequency signal for large bandwidth calibration operations, and even the swept frequency bandwidth calibration can be used once to implement the calibration operation for the swept frequency signal of the entire frequency band.
  • the compensation coefficient of IQ Imbalance can be obtained in the time domain (Time-Domain) based on spectrum analysis, and can also be obtained in the frequency domain (Frequency-Domain) based on the spectrum peak ratio.
  • the ideal compensation coefficient in order to further improve the accuracy of the IQ Imbalance compensation coefficient, can be approximated by iterative calibration and compensation, or the ideal compensation coefficient can be obtained by multi-observation calibration and compensation.
  • FIG. 16 is a schematic diagram of the structure of the mixer 421 provided in the embodiment of the present disclosure.
  • the mixer 421 includes a voltage-current converter (V/I Converter), a current switch (Current Switch) and a current-voltage converter (I/VConverter).
  • the voltage-current converter converts the received voltage signal into a current signal;
  • the current switch is connected to the voltage-current converter and the second signal generator, and is used to process the current signal output by the voltage-current converter using the local oscillator signal;
  • the current-voltage converter is connected to the current switch, and is used to convert the current signal output by the current switch into a voltage signal.
  • the current signal output by the voltage-current converter contains a harmonic signal corresponding to the baseband signal.
  • the HD caused by the third-order nonlinearity of the baseband can be referred to as HD3.
  • the harmonic caused by the fifth-order nonlinearity is called HD5.
  • the current switch processes the current signal output by the voltage-current converter, the frequency of the harmonic is converted to the RF band after up-conversion. Since the operation complexity of suppressing the harmonic signal in the RF band is high, the hardware cost is high. If the harmonic signal in the RF band is not removed, it will affect the signal quality of the radar reception and transmission, and thus affect the accuracy of the radar measurement.
  • the compensation unit is used to input the generated cancellation signal into the signal transmission link to cancel the harmonic signal in the radio frequency signal.
  • the compensation unit is independent of the first signal generator.
  • the compensation unit uses feedback or according to the characteristics of the transmission wave to input the generated cancellation signal into the signal transmission link to cancel the harmonic signal in the radio frequency signal output by the signal transmission link.
  • the cancellation signal has the characteristics of opposite phase and similar amplitude to the harmonic signal transmitted in the radio frequency transmission circuit, so as to achieve the purpose of suppressing the harmonic signal.
  • the compensation unit generates a compensation signal including a cancellation effect according to parameters such as the phase, frequency, or amplitude of the baseband signal generated by the first signal generator, or even the path length combined with the LO signal.
  • FIG5 shows an example of a transmitter in which a compensation unit is connected to a signal transmission link.
  • the compensation unit is a TX compensation unit.
  • the TX compensation unit includes a generator (not shown) that can generate a cancellation signal according to the characteristics of the transmission wave.
  • the cancellation signal generator can be exemplified by a TX HD3 compensation unit as shown in FIG6.
  • the baseband processor controls the orthogonal digital baseband signal generated by the TX DDFS, and the TX compensation unit generates an orthogonal compensation signal according to the parameters of the orthogonal digital signal, and merges the orthogonal compensation signal and the orthogonal digital signal and sends them to the IQ DAC to convert them into analog baseband signals.
  • the mixer i.e., the IQ modulator in Figure 5
  • the PA amplifies the mixed signal and outputs it through the transmitting antenna.
  • the compensation signal cancels out at least part of the harmonic signals in the radio frequency transmission circuit, such as the HD3 harmonic signal. Therefore, the clutter in the transmitted radio frequency signal will be greatly reduced.
  • the radio frequency signal can be an FMCW signal.
  • the compensation unit generates a compensation signal according to the harmonic information obtained through the feedback of the RF transmission circuit.
  • Figure 17 is a schematic diagram of the structure of the compensation unit in the transmitter shown in Figure 5. As shown in Figure 17, the compensation unit includes an acquisition circuit and a cancellation signal generator.
  • the acquisition circuit is coupled to the RF transmission circuit, and is used to acquire the signal in the RF transmission circuit to obtain an acquisition signal.
  • the acquisition signal (or sampling signal) can reflect the waveform information (also called harmonic parameters) in the harmonic signal, such as the phase of the main frequency signal, the phase of the harmonic signal, the frequency of the harmonic signal, the frequency of the main frequency signal, the power of the harmonic signal, the power of the main frequency signal, etc.
  • the harmonic parameters reflected by the acquisition signal are related to the information carried by the signal that can be acquired by the acquisition circuit.
  • the acquisition circuit is a power acquisition circuit
  • the corresponding acquisition signal includes the power of the main frequency.
  • the acquisition signal reflects the phase of the main frequency signal, the phase of the harmonic signal, the frequency of the harmonic signal, the frequency of the main frequency signal, the power of the harmonic signal, the power of the main frequency signal, etc.
  • At least one of the above harmonic parameters can be extracted by analog circuits.
  • the power of the main frequency signal is output through a coupler and a power detector.
  • the advantage of the digital circuit in the radar chip in frequency domain calculation is used to extract harmonic parameters.
  • a signal identical to the signal transmitted at the coupling point is obtained as a collection signal.
  • the collection signal carries the main frequency signal and the harmonic signal.
  • the collection signal is converted into a digital signal by an ADC and handed over to the digital circuit for calculation in the frequency domain to obtain more harmonic parameters.
  • the input end of the acquisition circuit is connected to the output end or the signal detection end of the mixer.
  • This method can detect the harmonic signal generated by the voltage-current converter and has a simplified acquisition circuit.
  • the input end of the acquisition circuit is connected to the detection end between the voltage-current converter and the current switch, and is coupled to the ADC.
  • the input end of the acquisition circuit is connected to the RF output end or RF detection end of the RF transmission circuit.
  • the RF output end is exemplified as the output end of the RF transmission circuit.
  • the RF detection end is exemplified as the input end or output end of at least one PA in the RF transmission circuit. This method can acquire more accurate harmonic parameters in the RF transmission circuit, but has a more complex circuit structure.
  • the acquisition circuit can obtain the acquisition signal through part or all of the circuits in the BIST module.
  • the input end of the acquisition circuit is coupled to the RF output end, which includes a down converter, a filter, etc. in sequence, and is connected to the IQ ADC to output a digital acquisition signal.
  • the down converter, the filter, etc. can reuse the BIST module or the receiver.
  • the collected signal is input to a cancellation signal generator, which is at least one circuit in the compensation unit.
  • the cancellation signal generator is connected to the first signal generator, so that the signal received by the radio frequency transmitting circuit includes both the baseband signal and the cancellation signal.
  • the cancellation signal generator includes the cancellation signal generator mentioned above and a digital circuit for extracting harmonic information, wherein the digital circuit for extracting harmonic information can be configured independently, or at least partially shared with the digital circuit in the radar chip.
  • the digital circuit for extracting harmonic information uses, for example, a digital circuit for processing difference frequency baseband signals in a radar chip to extract harmonic information such as harmonic frequency, main frequency, and main frequency power, and provides the information to a cancellation signal generator.
  • the cancellation signal generator generates a cancellation signal according to the received parameters.
  • the digital circuit for extracting harmonic information extracts the main frequency amplitude in the collected signal, and calculates the harmonic amplitude based on the difference between the preset main frequency amplitude and the harmonic amplitude.
  • the cancellation signal generator generates a harmonic signal compensation signal based on the calculated harmonic amplitude and other pre-configured harmonic parameters.
  • the pre-configured harmonic parameters can be calculated based on the sweep frequency range, phase, etc. of the main frequency signal to be transmitted by the radar chip.
  • the cancellation signal generator in the cancellation signal generator can be configured independently with the first signal generator, or at least partially shared.
  • the cancellation signal generated by the cancellation signal generator is input into the first signal generator, so that the baseband signal output by the first signal generator includes the cancellation signal.
  • the cancellation signal generator may include a third harmonic generator and a fifth harmonic generator.
  • the compensation unit further includes an adder, coupled to the cancellation signal generator and the first signal generator, to combine the baseband signal generated by the first signal generator and the cancellation signal generated by the cancellation signal generator.
  • the cancellation signal includes a cancellation signal Signal_HD3 generated by the third harmonic generator to cancel the third harmonic, and a cancellation signal Signal_HD5 generated by the fifth harmonic generator to cancel the fifth harmonic.
  • the cancellation signals Signal_HD3 and Signal_HD5 and the baseband signal generated by the first signal generator are combined by the adder and output to the RF transmission circuit.
  • the transmitter circuit examples provided in the present application that use feedback to pre-input a cancellation signal into a radio frequency transmitting circuit can ensure that the radio frequency signal transmitted by the chip contains sufficiently low harmonic signals under different environments.
  • the present application also provides a method for canceling harmonic signals in the above transmitter using a feedback mechanism, including:
  • Step 10 performing a collection operation on the signal in the signal transmission link to obtain a collection signal; wherein the signal transmission link is used to generate a radio frequency signal for radar detection, wherein the radio frequency signal includes a harmonic signal.
  • Step 20 Detect the collected signal, generate a cancellation signal for canceling the harmonic signal, and output the cancellation signal to the signal transmission link.
  • the method provided in the embodiment of the present application performs a collection operation on the signal in the signal transmission link to obtain a collection signal, and uses the collection signal to generate a cancellation signal, and outputs it to the signal transmission link, so as to use the cancellation signal to suppress the harmonic signal in the radio frequency signal and reduce the harmonic component in the radio frequency signal, thereby improving the signal quality of the radio frequency signal output by the transmitter, and further improving the receiving performance of the receiver for the radio frequency signal.
  • FIG11 shows an example of using a feedback mechanism to extract harmonic information in a transmitter so that the compensation unit generates a corresponding cancellation signal.
  • the compensation unit includes a TX HD3 compensation unit as an example.
  • the TX HD3 compensation unit generates a compensation signal according to the waveform characteristics of the received signal.
  • the feedback mechanism can be executed in the calibration mode of the radar chip to prevent the signal transmission power of the radar chip from being weakened during normal detection.
  • LO Leakage may be calibrated and compensated first, and then the compensation coefficients of HD3 and IQ Imbalance may be calibrated simultaneously through multiple (e.g., three) observations, and then the compensation coefficients at the HD3 mirror position may be calibrated again (e.g., twice); finally, the 3x and 5x frequency coefficients that need to be pre-compensated may be inversely calculated through the compensation coefficients at the HD3 and HD3 mirror positions.
  • the observations provided in the embodiments of the present disclosure are used to represent operations such as testing and comparative analysis of different test results.

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Abstract

一种校准链路、信号传输链路、集成电路、电磁波器件和设备。所述信号传输主通路用于传输电磁波信号，所述校准链路集成在包括所述信号传输主通路的集成电路中，所述校准链路至少连接至所述信号传输主通路与所述信号传输主通路对应的天线之间；其中：所述校准链路，可配置为用于对信号传输主通路进行校准，得到校准信息；其中，所述信号传输主通路，可配置为用于基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路传输电磁波信号。

Description

校准链路、信号传输链路、集成电路、电磁波器件和设备
本申请要求于2023年6月14日提交中国专利局、申请号为202310702586.5、发明名称为“信号发射、校准、补偿及收发链路，IQ混频器、集成电路、传感器及设备”的中国专利申请的优先权，2023年12月31日提交中国专利局、申请号为202311873028.1、发明名称为“一种校准链路、信号接收链路、电磁波器件和集成电路”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于电磁波器件技术领域，尤其涉及一种校准链路、信号传输链路、集成电路、电磁波器件和设备。
背景技术
在调频连续波(Frequency Modulated Continuous Wave，FMCW)雷达中，利用发射信号和回波信号之间的频率差可以计算目标的距离，其中目标距离越远，对应的中频信号的频率也就越大；而距离越近的目标，对应的差频信号的频率也就越小。在收到多个连续的脉冲信号后，通过在快时间和慢时间维度上进行傅里叶变换，能够得到目标的距离信息和径向速度信息。此外，还可以通过多天线技术实现对目标反射的回波信号的波达方向(Direction Of Arrival，DOA)的测量。
为了提高FMCW雷达系统的参数估计(如，距离、径向速度和DoA)估计性能，需要对收发链路进行校准和补偿，但是传统的校准方式不能实时地校准射频器件，因为需要利用大量的外设，而射频器件参数指标是会随着环境的改变而改变的。
发明内容
本公开实施例提供了一种校准链路、信号传输链路、集成电路、电磁波器件和设备。
一种信号传输主通路的校准链路，所述信号传输主通路用于传输电磁波信号，所述校准链路集成在包括所述信号传输主通路的集成电路中，所述校准链路至少连接至所述信号传输主通路与所述信号传输主通路对应的天线之间；其中：所述校准链路，可配置为用于对信号传输主通路进行校准，得到校准信息；其中，所述信号传输主通路，可配置为用于基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路传输电磁波信号。即通过将校准链路与主通路集成为一体，进而在无需外设的情况下，达到实时地校准的目的。
示例性的，所述校准链路在所述集成电路出厂前、在所述集成电路发/收信号的间隙中至少一个对所述信号传输主通路进行校准，并基于所述校准链路上一次校准所得到的校准信息，对所传输的信息进行实时补偿。
示例性的，所述集成电路中设置有至少两路所述信号传输主通路；其中，任一路所述校准链路，可配置为用于对至少两路所述信号传输主通路进行校准。
示例性的，所述校准链路所传输的信号为单音信号。
示例性的，所述电磁波信号为雷达信号；所述信号传输主通路包括回波信号的接收主通路和/或射频信号的发射主通路，所述校准链路对应包括所述接收主通路对应的辅助发射链路和/或所述发射主通路对应的辅助接收链路，所述天线对应包括所述接收主通路对应的接收天线和/或所述发射主通路对应的发射天线；所述辅助接收链路连接于所述发射主通路与对应所述发射天线之间，可配置为用于对所述发射主通路所发射的射频信号进行校准；以及所述接收主通路包括与接收天线依次相连的射频单元和中频单元，对应的，所述辅助发射链路包括与所述中频单元对应的中频辅助发射链路和与所述射频单元对应的射频辅助发射链路中的至少一个，其中所述中频辅助发射链路连接于所述接收主通路的中频信号输出端，可配置为用于对所述接收主通路所接收的回波信号进行下降频后得到的中频信号进行校准；所述射频辅助发射链路连接于所述接收主通路与对应所述接收天线之间，可配置为用于对所述接收主通路所接收的回波信号进行校准。
示例性的，所述辅助接收链路包括：第一混频器，可配置为用于利用接收操作所使用的本振信号对接收的信号进行混频处理；第一功率放大器，可配置为用于对第一混频器输出的信号进行放大处理；第一滤波单元，可配置为用于对接收的信号进行滤波处理，得到滤波信号；第一实数数模转换器，可配置为用于将数字的滤波信号转换为模拟的滤波信号。
示例性的，所述辅助接收链路还可包括：第一加法器，与所述第一实数数模转换器相连，可配置为用于根据第一混频器使用的本振信号的泄露信号，对所述第一实数数模转换器输出的信号进行补偿。
示例性的，所述校准链路还可包括所述辅助接收链路对应的校准发射链路；其中，所述校准发射链路，可配置为用于对所述辅助接收链路进行校准操作；对应的，所述辅助发射链路基于所述校准接收链路得到的校准信息进行校准操作，其中校准后的辅助接收链路对所述发射主通路进行校准操作。
示例性的，所述校准发射链路可包括：第一信号产生器，可配置为用于输出数字的原始信号；第二实数数模转换器，可配置为用于将数字的原始信号的转换为模拟的原始信号；第二滤波单元，可配置为用于对原始信号进行滤波处理，得到滤波信号；第二功率放大器，可配置为用于对滤波信号进行放大处理，得到放大信号；第二混频器，可配置为用于利用发射操作所使用本振信号对所述放大信号进行混频处理。
示例性的，所述校准发射链路还可包括第二加法器和带通滤波器中的至少一个，其中：所述第二加法器，连接于第一信号产生器与第二实数数模转换器之间，可配置为根据第二混频器所使用的本振信号的泄露信号，对第一信号产生器输出的信号进行补偿；所述带通滤波器，与所述第二混频器相连，可配置为用于对所述第二混频器输出的信号进行滤波处理，并将滤波处理后的信号发送给校准单元。
示例性的，所述中频辅助发射链路可包括：所述中频辅助发射链路包括第一信号源和第三实数数模转换器；其中第一信号源，可被配置为用于输出数字的中频校准信号；第三实数数模转换器，可被配置为用于将数字的中频校准信号的转换为模拟的中频校准信号；或者，所述中频辅助发射链路包括第四实数数模转换器、第三混频器和第一平方器；其中所述第四实数数模转换器，可被配置为用于将预设的数字的信号转换为模拟的信号；所述第三混频器，可被配置为用于将第四实数数模转换器输出的信号和本振信号进行混频处理，得到混频信号；所述第一平方器，可被配置为用于对混频信号进行平方处理，得到所述中频校准信号。
示例性的，所述第一信号源包括第二信号产生器和数字移相模块；其中，所述第二信号产生器被配置为生成初始信号；以及所述数字移相模块被配置为采用数字正交调制方式对所述初始信号进行频率搬移和/或移相处理。
示例性的，所述射频辅助发射链路还可与所述中频单元的输入端相连；其中：在所述中频单元完成校准操作后，利用校准后的中频单元对射频辅助发射链路进行校准；利用校准后的射频辅助发射链路对所述射频单元进行校准。
示例性的，所述射频辅助发射链路可包括；第二信号源，可被配置为用于输出原始信号；第三滤波单元，可被配置为用于对原始信号进行滤波处理，得到滤波信号；第三功率放大器，可被配置为用于对滤波信号进行放大处理，得到放大信号；第四混频器，可被配置为用于利用本振信号对所述放大信号进行混频处理，得到所需信号。
示例性的，所述射频辅助发射链路包括正交补偿单元、第二平方器和第三加法器中的至少一个，其中：所述正交补偿单元，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可被配置为用于在所述第二信号源输出的初始信号为正交信号时，对接收的初始信号的正交失衡进行补偿；所述第二平方器，与所述中频单元的信号输入端相连，可配置为对所述第四混频器输出的信号进行处理，并输出给校准后的中频单元；所述第三加法器，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可配置为根据第四混频器所使用的本振信号的泄露信号，对第二信号源输出的信号进行补偿。
一种信号传输链路，可包括：信号传输主通路，可配置为用于传输电磁波信号；以及校准链路，集成于包括有所述信号传输主通路的器件中，以用于对所述信号传输主通路进行校准；其中，所述信号传输主通路基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路执行信电磁波信号的传输操作。
示例性的，所述校准链路可为上文所述的校准链路。示例性的，所述信号传输主通路与所述校准链路集成于同一芯片内或同一PCD板或同一PCB板上。
一种集成电路，所述集成电路具有至少两条信号传输主通路以及设置在所述两条发射主通路之间的上文所述的校准链路，其中所述校准链路供所述两条信号传输主通路共有。
一种电磁波器件，可包括：承载体；上文所述的集成电路，设置在所处承载体上；天线，设置在所述承载体上，或者所述天线与所述集成电路集成为一体器件设置在所述承载体上；所述天线包括发射天线和接收天线；其中，所述集成电路与所述天线连接，用于发射电磁波信号和/或接收电磁波信号。
一种用户终端设备，可包括：设备本体；以及设置于所述设备本体上的上文所述的电磁波器件；其中，所述电磁波器件用于目标检测和/或无线通信，以向所述设备本体的运行提供参考信息。
本公开实施例的校准链路、信号传输链路、集成电路、电磁波器件和设备，由于校准链路集成于包括有所述信号传输主通路的集成电路中，使得校准链路能实时对信号传输主通路进行校准操作，且校准链路的校准操作可以不受信号传输主通路的运行环境的变化而变化，使得信号传输主通路能够得到更加精确的校准信息，从而提高信号传输主通路的信号处理性能。
附图概述
图1A为模拟移相器架构的信号发射链路的简易示意图；
图1B为图1A所示信号发射链路中模拟移相器的简易示意图；
图2为本公开示例性实施例提供的一种信号发射链路的结构示意图；
图3为一种采用锯齿波调制的FMCW发射信号和回波信号的波形示意图；
图4为本公开示例性实施例提供的另一种信号发射链路的结构示意图；
图5为本公开示例性实施例提供的一种信号发射链路中数字移相器架构的示意图；
图6为本公开实施例提供的一种包含有补偿单元的信号发射链路的示意图；
图7本公开实施例提供的利用校准链路对发射主通路进行校准的示意图；
图8为本公开示例性实施例提供的一种信号收发链路的结构示意图；
图9为本公开示例性实施例提供的另一种信号收发链路的结构示意图；
图10为本公开实施例提供的另一种收发链路的示意图；
图11为本公开实施例提供的一种包含TX IQ Mod、RX IQ De-Mod和LO Freq Diff的收发链路的示意图；
图12为本公开实施例提供的一种基于图11所示结构结合BIST的收发链路的示意图；
图13为本公开实施例提供的一种包含TX IQ Mod、BIST IQ Mod和RX IQ De-Mod的收发链路的示意图；
图14为本公开实施例提供的一种包含辅助电路和BIST IQ Mod的收发链路的示意图；
图15为本公开实施例提供的另一种包含辅助电路和BIST IQ Mod的收发链路的示意图；
图16为本公开实施例提供的一种混频器的结构示意图；
图17为本公开实施例提供的一种发射机中补偿单元的结构示意图；
图18为本公开实施例提供的一种基于三次方模块的数字预补偿HD3架构的示意图；
图19为本公开实施例提供的一种基于倍频波形发生器模块的数字预补偿HD3架构的示意图；
图20为本公开实施例提供的一种基于数字移相器架构发射链路的校准补偿示意图；
图21A为本公开实施例提供的信号传输主通路的校准链路的结构示意图；
图21B为图21A所示的校准链路的部署示意图；
图22A为本公开实施例提供的校准链路与发射主通路之间的连接示意图；
图22B为本公开实施例提供的校准链路与接收主通路之间的第一连接示意图；
图22C为本公开实施例提供的校准链路与接收主通路之间的第二连接示意图；
图23A为图22A中辅助接收链路的结构示意图；
图23B为图23A中辅助接收链路的另一结构示意图；
图23C为图22A中校准发射链路的结构示意图；
图23D为图23C中校准发射链路的另一结构示意图；
图24为本公开实施例提供的发射主通路对应的校准链路的应用示意图；
图25A为图22A中中频辅助发射链路的第一结构示意图；
图25B为图22A中中频辅助发射链路的第二结构示意图；
图25C为图22A中射频辅助发射链路的结构示意图；
图25D为图25C所示射频辅助发射链路的另一结构示意图；
图26为本公开实施例提供的接收主通路对应的校准链路的应用示意图；
图27A为本公开实施例提供的中频辅助发射链路的第一应用示意图；
图27B为本公开实施例提供的中频辅助发射链路的第二应用示意图。
详述
雷达是利用电磁波探测目标的电子设备，雷达芯片通过信号发射链路发射波束，当发射波束遇到障碍物时，经由障碍物反射回来的回波经过接收天线接收，传输至雷达芯片，经过雷达芯片判断目标相对电磁波发射点的位置、距离、速度等信息。随着微电子等技术的发展，雷达逐渐得到广泛的应用，尤其是毫米波雷达(如汽车雷达)，由于其具有尺寸较小的天线，在自动驾驶、智能家居设备及工业自动化器件中得到了广泛的应用。目前，雷达的小型化和集成化成为当下发展的趋势。
图1A为模拟移相器架构的信号发射链路的简易示意图，图1B为图1A所示信号发射链路中模拟移相器的简易示意图。如图1A所示，针对一个发射链路而言，传感器在发射信号时，通过诸如由锁相环(Phase Locked Loop，PLL)所构成的信号产生器11来生成本振(Local Oscillato，LO)信号(如77GHz频段的扫频信号)，例如可以是FMCW信号；模拟移相器(Analog PS)12针对所接收的LO信号进行移相操作后，经发射天线13辐射至预定的空间区域内，以进行目标检测及测量等操作。可选的，图1A所示的发射链路结构中，对应的模拟移相器架构可如图1B所示，其具体的移相原理可如下式所示：
其中
即通过对所接收的LO信号(即LOIN)分别进行0°和90°移相后得到两路信号(即LOI和LOQ)，并经功率放大器(PA)放大后拟合为一路输出信号LOOUT，即该输出信号LOOUT相较于LOIN输入信号移相θ，其中该移相θ的值是由两路信号LOI的幅度A和LOQ的幅度B所决定。
另外，上述的模拟移相器架构还可通过延迟线(Delay Line Unit)的方式实现，即利用信号的窄带假设(Narrow-band assumption)，通过时延的方式进行移相，其原理如下式所示：
其中，τ为延迟线所延迟时间。
由于上述的模拟移相器的调相精度(Resolution)、调相准确度(Accuracy)均较低，从而无法满足当前传感器的需求。同时，虽然可通过校准来提升其调相精度和调相准确度，但需要对模拟架构的移相器进行离线(off-line)的校准，进而会使得工程实现及产品量产的难度及复杂度大幅提升。同时，模拟移相器还存在面积大、损耗大、以及稳定性和通道耦合等比较严重的问题。
由于采用模拟移相器架构的信号发射链路，存在调相精度及调相准确度均较低等问题，因此，其无法满足车载雷达系统的高性能需求。
如图2所示，本公开实施例提供了一种信号发射链路，该信号发射链路可应用于雷达系统中，该信号发射链路可包括：发端基带(Baseband)数字模块201、IQ数模转换(Ditial-to-Analog Converter，DAC)模块202、发端本振器203和发端正交调制器204，其中：发端基带数字模块201，可被配置为生成两路正交的发端数字基带信号，并将两路正交的发端数字基带信号分别送入IQ数模转换模块202中的I路和Q路中，即数模转换模块202，被配置为将两路正交的发端数字基带信号转换为两路发端模拟基带信号；发端本振器203，被配置为提供发端本振信号TX_LO；发端正交调制器204，被配置为基于两路发端模拟基带信号，对发端本振信号TX_LO进行频率搬移的同时进行移相操作，以形成预定移相后的FMCW射频发射信号。
本公开实施例中，发端基带数字模块201提供的发端数字基带信号中可包括预设的相位信息；数模转换模块202可通过对所接收的发端数字基带信号进行数模转换，以将发端数字基带信号转换为发端模拟基带信号(如在不改变相位信息的情况下，将数字信号转换为模拟信号)；发端正交调制器204则可将所接收的发端模拟基带信号与发端本振器203生成的发端本振信号TX_LO进行混频操作，以达到基于发端模拟基带信号对发端本振信号进行频率搬移的同时进行预设的移相操作，以形成预定移相后的FMCW射频发射信号。
本公开实施例的信号发射链路，通过使用发端基带数字模块201、数模转换模块202和发端正交调制器204组成了数字移相器架构，由于该架构的基带信号是在数字域产生的，有更好的正交性和更低的旁瓣，因此其移相相位可以非常准确产生，使得调相精度更高，从而实现了带有高精度的数字移相功能的车载雷达系统，降低了天线之间隔离度的需求，同时具有链路损耗小、成本低、无需离线校准的优点，并且可以支持更为灵活的发波方案，比如高性能的多普勒分复用和频分复用等，且能够支持在数字域进行频率响应补偿。
本公开实施例中，由于发端基带数字模块201提供的是数字信号，为了进一步适配信号特性，发端调制器设置为正交调制器(IQ Modulator)，数模转换模块202设置为正交数模转换器(IQ DAC)。
本公开实施例中，发端本振器203可以为包含有锁相环(Phase-Locked Loop，PLL)的架构，可提供电磁波(例如激光、微波等)信号。
在一些示例性实施方式中，该信号发射链路还包括：功率放大器(Power Amplifier，PA)205，其中：功率放大器205，被配置为对移相后的射频信号进行功率放大并将放大后的信号输出至发射天线。
在一些示例性实施方式中，该信号发射链路还包括：发射天线206，其中：发射天线206，被配置为将放大后的信号向预设空间区域辐射。
本公开实施例中，经功率放大器205放大后的信号可通过封装为一体或外置的发射天线206辐射至预设的空间区域中。即，发端本振器203、数字移相器和发射天线206等可集成为一体的器件，也可为相互分立的元器件；例如，发端本振器203和数字移相器可集成于一封装体中形成诸如SoC芯片(chip)等，而发射天线206则可通过芯片的外设端口连接，形成在诸如PCB板等载体上。同时，一些可选的实施例中，发射天线206还可集成在芯片的封装上形成AiP(Antenna in Package)或者AoP(Antenna on Package)，具有封装天线的芯片结构。
在一些示例性实施方式中，扫频信号的频带宽度在2GHz以上。例如，针对雷达而言，调频连续波雷达系统的发射天线发出的发射信号的电磁波为高频调频连续波，调频连续波雷达系统的接收天线接收的回波信号是目标物反射/散射回来的电磁波。图3示出了一种示例性的FMCW发射信号和回波信号的波形示意图。如图3所示，发射信号和回波信号的频率随时间规律变化。调频连续波一般为锯齿形、三角形等，本公开以锯齿形为例进行说明，每个调频周期T内的电磁波称为一个啁啾(Chirp)，每个Chirp的信号的频率随时间线性增加。本公开实施例中，一个啁啾的带宽范围B大于或等于2GHz。
在一些示例性实施方式中，发端数字基带信号为单音信号，发端本振信号为扫频信号。
本公开实施例中，发端本振器203可被配置为用于提供微波中的厘米波频段或毫米波频段(如3.1GHz、24GHz、60GHz、77GHz等频段)的FMCW信号，发端基带数字模块201可被配置为用于提供MHz(例如3MHz～5MHz，如3MHz、4MHz、5MHz等)级别的单音发端数字基带信号，即数模转换模块202对MHz级别的单音发端数字基带信号进行数模转换后得到对应频率范围的单音发端模拟基带信号，发端正交调制器204可被配置为基于所接收的单音发端模拟基带信号对所接收的毫米波频段的FMCW信号进行上混频或者下混频操作，以实现对FMCW信号进行预设移相的操作。
示例性的，3.1GHz频段的FMCW信号可包括3.1GHz～10.6GHz之间的扫频信号，如7.163-8.812GHz；77GHz频段的FMCW信号可包括76GHz～81GHz的扫频信号，或者，76GHz～77GHz、77GHz～79GHz、79GHz～81GHz等扫频信号。
在另一些示例性实施方式中，发端数字基带信号为扫频信号，发端本振信号为单音信号。
本公开实施例中，发端本振器203可被配置为用于提供微波中的厘米波频段或毫米波频段(如3.1GHz、24GHz、60GHz、77GHz等频段)的单音发端本振信号，发端基带数字模块201可被配置为用于提供MHz(例如3MHz～5MHz，如3MHz、4MHz、5MHz等)级别的发端数字基带FMCW信号，即数模转换模块202对MHz级别的发端数字基带FMCW信号进行数模转换后得到对应频率范围的发端模拟基带FMCW信号，发端正交调制器204可被配置为基于所接收的发端模拟基带FMCW信号对所接收的厘米波频段或毫米波频段的单音发端本振信号进行上混频或者下混频操作，以实现对单音发端本振信号进行预设移相和扫频的操作。
示例性的，3.1GHz频段的单音发端本振信号可以为3.1GHz、5GHz、6GHz、8GHz、10.6GHz等固定频段的单音模拟信号；77GHz频段的单音发端本振信号可以为76GHz、77GHz、78GHz、79GHz、80GHz、81GHz等固定频段的单音模拟信号。
在一些示例性实施方式中，该信号发射链路还包括：低通滤波器(Low Pass Filter，LPF)207，设置在数模转换模块202和发端正交调制器204之间，被配置为对数模转换模块202输出的发端模拟基带信号进行低通滤波并输出至发端正交调制器204。
如图2所示，发端基带数字模块201产生两路正交的数字基带(Baseband)信号，即I路数字基带信号和Q路数字基带信号，并将产生的数字基带信号送入数模转换模块202(包含两个完全相同的DAC，即IQ DAC)中，得到两路模拟基带信号。然后将两路模拟基带信号输入低通滤波器207，滤除带外噪声信号，并通过发端正交调制器204进行正交调制，得到调制后的射频信号，再通过功率放大器205以及发射天线206，将调制后的射频信号辐射出去。
在一些示例性实施方式中，信号发射链路还可以包括直接数字频率合成器(Direct Digital Frequency Synthesizer，DDFS)(图2中未示出)，设置在发端基带数字模块201和数模转换模块202之间，直接数字频率合成器可被配置为基于所接收的源信号实现CDM(Code-Division Multiplexing，码分复用)、DDM(DopplerDivision Multiplexing，多普勒分割复用)、TDM(Time-Division Multiplexing，时分复用)、SDM(Space Division Multiplexing，空分复用)、CSD(Circuit Switch Data，电路交换数据)、Digital IF(Digital Intermediate Frequency，数字中频)等多种信号波形及发波方式中的至少一种，以实现信号发射形式及发射波形的灵活配置。
如图4所示，本公开实施例还提供了一种信号发射链路，应用电磁波发射器件中，该信号发射链路包括第一信号源41和数字移相模块42；其中，第一信号源41被配置为生成第一模拟信号；以及数字移相模块42被配置为采用数字正交调制方式对第一模拟信号进行频率搬移和/或移相，以形成FMCW射频发射信号。
本公开实施例提供的信号发射链路，包括第一信号源41和数字移相模块42，第一信号源41可被配置为用于提供第一模拟信号，数字移相模块42则可被配置为用于在数字域产生移相信号，数字移相模块42还可基于所产生的移相信号对第一模拟信号进行移相，以将第一模拟信号进行预设的移相操作。
在一些示例性实施方式中，第一信号源41可以为发端本振器，第一模拟信号可以为发端本征(LO)信号。
在一些示例性实施方式中，该信号发射链路还包括功率放大器(图中未示出)，被配置为对FMCW射频发射信号进行放大。
在一些示例性实施方式中，该信号发射链路还包括发射天线43，被配置将经功率放大后的FMCW射频发射信号向预定区域进行辐射。
如图4所示，在一些可选的实施例中，该信号发射链路可包括第一信号源41、数字移相模块(Digital PS)42和发射天线43等，即第一信号源41可被配置为用于提供LO信号，数字移相模块42则可被配置为用于对所接收的LO信号进行预设移相操作，以使得移相后的LO信号经发射天线43辐射到预设空间区域中。其中，第一信号源41也可为包含有锁相环PLL的架构，可提供电磁波(例如激光、微波等)信号。其中，第一信号源41、数字移相模块42和发射天线43可集成为一体的器件，也可为相互分立的元器件；例如，第一信号源41和数字移相模块42可集成于一封装体中形成诸如SoC芯片(chip)等，而发射天线43则可通过芯片的外设端口连接，形成在诸如PCB板等载体上。同时，一些可选的实施例中，发射天线43还可集成在芯片的封装上形成AiP或者AoP，具有封装天线的芯片结构。
在一些示例性实施方式中，数字移相模块42包括依次连接的第二信号源423、数模转换模块422和混频器421；其中，第二信号源423被配置为生成第一数字信号；数模转换模块422被配置为将第一数字信号转换为第二模拟信号；混频器421被配置为基于第二模拟信号对第一模拟信号进行频率搬移和/或移相，以形成FMCW射频发射信号。
如图4所示，本公开实施例中的数字移相模块42可包括混频器(Mixer)421、数模转换模块(即DAC)422和第二信号源(如数字基带信号源Baseband)423等，即第二信号源423可被配置为用于提供第一数字信号；数模转换模块422则可被配置为用于对所接收的第一数字信号进行数模转换，以将第一数字信号转换为第二模拟信号；混频器421则可被配置为用于将所接收的第二模拟信号与所接收的来自第一信号源41的第一模拟信号进行混频操作，以达到利用第一数字信号对上述的第一模拟信号进行设定的移相操作。可选的，当上述的信号发射链路提供扫频信号时，例如提供FMCW激光信号或FMCW微波信号时，可基于第一信号源41提供扫频发射信号，和/或基于第二信号源423提供扫频第一数字信号，以使得经过混频器421混频后，输出扫频连续波信号。
在一些可选的实施例中，基于图4所示的结构，第一信号源41可被配置为用于提供微波中的厘米波频段或毫米波频段(如3.1GHz、24GHz、60GHz、77GHz等频段)FMCW信号(即第一模拟信号)，第二信号源423可被配置为用于提供MHz(例如3MHz～5MHz，如3MHz、4MHz、5MHz等)级别的第一数字信号，即数模转换模块422对MHz级别的第一数字信号进行数模转换后得到对应频率范围的第二模拟信号，混频器421可被配置为基于所接收的固定频段的第二模拟信号对所接收的毫米波频段的FMCW信号进行上混频或者下混频操作，以实现对FMCW信号进行预设移相的操作。
在一些可选的实施例中，3.1GHz频段的厘米波信号可包括3.1GHz～10.6GHz，例如3.1GHz、、5GHz、5GHz、6GHz、8GHz、10.6GHz等；77GHz频段的毫米波信号可包括76GHz～81GHz的信号，例如76GHz～77GHz、77GHz～79GHz、79GHz～81GHz等扫频信号，或者76GHz、77GHz、78GHz、79GHz、80GHz、81GHz等固定频段信号。
在一些示例性实施方式中，第一数字信号包括两路正交的发端数字基带信号；第二信号源423为发端基带数字模块，数模转换模块422包括两个相同的数模转换器；发端基带数字模块，被配置为生成两路正交的发端数字基带信号，并将两路正交的发端数字基带信号分别送入一个数模转换器；数模转换模块422，被配置为将两路正交的发端数字基带信号转换为两路发端模拟基带信号。
基于图4所示的结构，由于第二信号源423提供的是第一数字信号，为了进一步适配信号特性，混频器421可设置为IQ Mixer，数模转换模块422为IQ DAC。同时，第二信号源423可被配置为用于提供用于移相的数字基带信号源(DDFS)和/或作为波形控制器(Waveform Control)提供对应的源信号。其中，DDFS为一种相位可调的数字基带信号源，其产生数字基带信号。
如图5所示，数字移相器架构的信号发射链路(TX digital phase shifter architecture)可包括数字基带信号源(Baseband)、直接数字频率合成器(Direct Digital Frequency Synthesizer，简称DDFS)、IQ数模转换器(Digital to Analog Convertor，简称DAC)、低通滤波器(Low-Pass Filter，简称LPF)、IQ调制器(IQ modulator/IQ Mixer)、功率放大器(Power Amplifier，PA)等，即基带信号源被配置为用于提供数字移相源信号(即前述第一数字信号)，直接数字频率合成器可被配置为基于所接收的源信号实现CDM(Code-Division Multiplexing，码分复用)、DDM(Doppler Division Multiplexing，多普勒分割复用)、TDM(Time-Division Multiplexing，时分复用)、SDM(Space Division Multiplexing，空分复用)、CSD(Circuit Switch Data，电路交换数据)、Digital IF(Digital Intermediate Frequency，数字中频)等多种信号波形及发波方式中的至少一种，以实现信号发射形式及发射波形的灵活配置。其中，经功率放大器放大后的信号可通过封装为一体或外置的发射天线辐射至预设的空间区域中。
针对本公开实施例中的数字移相器架构的信号发射链路，由于数字移相器架构被配置为可在数字域产生基带信号序列，并可通过DAC产生模拟基带信号(即第二模拟信号)，然后经过正交混频器将发射信号调制到高频，即因为该架构的基带信号是在数字域产生的，有更好的正交性和更低的旁瓣，因此其移相相位可以非常准确产生，使得调相精度更高。
在一些可选的实施例中，针对数字移相器架构的信号发射链路，当采用RF LO扫频实现所发射信号为FMCW信号时，针对所可能出现的因IQ失配(Mismatch)而引起的TX IQ失衡(Imbalance)、信号泄漏(如TX LO Leakage)谐波失真(harmonic distortion,简称HD)等问题，还可在该信号发射链路增设补偿单元。如图5所示，可通过在TX DDFS与IQ DAC之间设置TX补偿单元(TX compensation)，以对数字移相器架构的信号发射链路进行校准(calibration)及补偿(compensation)等操作，以到达解决上述问题中的至少之一的操作。其中，由基带的三阶非线性所引起的HD可简称为HD3。
在一些可选的实施例中，如图6所示，TX补偿单元(TX compensation)可包括TX LO泄漏补偿单元(TX LO leakage compensation)、TX IQ失衡补偿单元(TX IQ Imbalance compensation)和TX HD3补偿单元(TX HD3 compensation)中的至少一个，其中，TX LO泄漏补偿单元可被配置为用于针对信号泄漏(leakage)而进行的补偿操作，TX IQ失衡补偿单元可被配置为用于针对IQ失衡而进行的补偿操作，TX HD3补偿单元可被配置为用于针对上述的HD3而进行的补偿操作。其中，TX IQ失衡补偿单元被配置为可用于对IQ调制器失衡(TX IQ Modulator imbalance)、IQ通道失衡(IQ channel imbalance)中的至少一个进行补偿操作。另外，当补偿单元包括TX LO泄漏补偿单元、TX IQ失衡补偿单元和TX HD3补偿单元中的至少两个时，可以依据实际需求及信号特性等同步进行补偿(如并联方式)，也可依次进行补偿(如串联方式)，如图6所示可以先进行IQ补偿、然后再进行LO补偿，最后进行HD3补偿等操作。
在一些可选的实施例中，针对数字移相器架构的信号发射链路，还可包括有针对DAC的误差校正模块(TX DAC Board Error Correction)和针对高斯白噪声的AWGN(additive white gaussian noise)模块等，图中未示出，具体的可根据实际需求而增设或删减。其中，本公开实施例中提及的IQ中I可表示为In-Phase(即同相)的简称，Q表示为Quadrature(即正交)的简称，RF可表示为Radio Frequency(即射频)的简称。
在一个可选的实施例中，针对IQ Imbalance的补偿操作，可通过补偿BB(基带)信号的共轭信号来反向抵消镜像分量的方式实现，且该补偿操作方式不受IQ Imbalance的校准方式的影响。针对LO Leakage的补偿则可通过调节IQ两路的DC分量(即直流偏置)来实现，同样该LO Leakage的校准方式对其补偿方案不产生影响。针对HD3，由于正交混频器V/I Converter的3阶谐波失真是产生HD3的主要来源，而谐波失真会受到直流偏置的影响，因此当发射链路的LO Leakage和HD3均需要校准时，则需要在进行LO Leakage的校准后再进行HD3的校准，以确保HD3校准的精准性能；当发射链路的LO Leakage、IQ失衡和HD3均需要校准时，则在进行LO Leakage的校准后再进行IQ失衡的校准，最后再进行HD3的校准，以确保的精准性能。
另外，基于数字三次方模块的数字预补偿架构和基于倍频波形发生器模块的数字预补偿架构的HD3的补偿方式，会直接影响后续的校准方案和后续的补偿流程。具体的：
在一个可选的实施例中，针对基于数字三次方模块的数字预补偿架构，可先校准并补偿LO Leakage后，在稳定的DC偏置下，校准IQ Imbalance，并继续补偿IQ Imbalance后，分别对IQ两路依据IQ Imbalance预补偿的结果，再校准出HD3问题的根本来源，即HD3的补偿系数，去补偿三次谐波失真。
在一个可选的实施例中，针对基于倍频波形发生器模块的数字预补偿架构，可在校准并补偿LO Leakage后，校准得到HD3的补偿系数，并在稳定的DC偏置下校准IQ Imbalance，以及补偿IQ Imbalance；后续通过补偿后的结果，分别计算出IQ两路信号的实际波形，HD3的补偿系数，反算出需要预补偿的3倍频和5倍频的波形信息。
在另一个可选的实施例中，针对基于倍频波形发生器模块的数字预补偿架构，可先校准并补偿LO Leakage，然后通过多次(如三次)观测以先校准出IQ Imbalance的补偿系数，之后再通过再次观测(如两次)来校准出HD3镜像位置处的补偿系数；最后通过HD3和HD3镜像位置处的补偿系数反算出需要预补偿的3倍频和5倍频系数。需要说明的是，本公开实施例中的观测用以表示测试以及不同测试结果比较分析等操作。
图7为本公开实施例提供的利用校准链路对发射主通路进行校准的示意图。如图7所示，该校准链路用于对用于发射射频信号的发射主通路进行校准；其中所述发射主通路包括与发射天线相连的发射单元，所述校准链路集成于包括有所述发射主通路的集成电路中；由于校准链路集成于包括有所述发射主通路的集成电路中，能实时地校准发射主通路，也无需外部设备对发射主通路进行校准操作。
其中，所述校准链路包括校准单元，所述校准单元连接至所述发射单元与所述发射天线之间，可配置为用于对所述发射单元输出的射频信号进行校准；所述发射单元，可配置为用于基于所述校准链路得到的校准信息完成校准操作，其中校准后的发射单元输出的射频信号通过所述发射天线辐射至预定区域。
其中，该发射主通路(Transmitter)可包括移相模块PS、功率放大器PA、功率检测器PD等，例如该发射通路可采用本公开任一实施例所阐述的数字移相架构(Digital Phase Shifter)的信号发射链路，具体可参见相关图示及文字描述，在此便不予赘述。由于发射通路采用的是数字移相器架构，以在实现更加精准的移相操作的同时，使得发射通道能够同时支持多天线的DDM、FDM(Frequency Division Multiplexing，频分复用)等多个模式，还可省去RF移相器(Phase Shifter)的校准操作，降低移相系统中隔离度和耦合度，减小链路损耗及生产制造成本。另外，针对所引入可能存在的TX IQ失配(Mismatch)、LO泄漏(leakage)等问题，该数字移相器架构的发射通路还可支持在数字域进行RF频率响应(Frequency Response)补偿、IQ不平衡和LO泄漏的校准操作等。
针对发射通路中存在的TX IQ失配(Mismatch)、LO泄漏(leakage)、频率响应等问题，可通过设置校准链路来进行相关的校准操作。
由于校准链路集成于包括有所述发射主通路的集成电路中，因此，校准单元能实时地校准发射单元，另外，该校准单元与发射单元的运行环境相同，因此，校准单元的校准操作可以不受发射单元的运行环境的变化而变化，使得校准单元能够得到更加精确的校准信息，从而提高发射单元的信号处理性能。
本公开实施例提供的校准链路，由于校准链路集成于包括有所述发射主通路的集成电路中，使得校准链路能实时对发射主通路进行校准操作，且校准链路的校准操作可以不受发射主通路的运行环境的变化而变化，使得发射主通路能够得到更加精确的校准信息，从而提高发射主通路的信号处理性能。
本公开实施例还提供了一种信号收发链路，包括信号发射链路和信号接收链路，如图8或图9所示，信号发射链路可以包括：发端基带数字模块201、数模转换模块202、发端本振器203和发端正交调制器204，其中：发端基带数字模块201，被配置为生成两路正交的发端数字基带信号，并将生成的发端数字基带信号送入数模转换模块202中；数模转换模块202，被配置为将发端数字基带信号转换为发端模拟基带信号；发端本振器203，被配置为提供发端本振信号TX_LO；发端正交调制器204，被配置为基于发端模拟基带信号对发端本振信号TX_LO进行移相操作，得到移相后的射频信号。
信号接收链路可以包括收端本振器302、收端混频器303、模数转换器(Analog-to-Digital Converter，ADC)304和收端基带数字模块305；其中，收端本振器302，被配置为提供收端本振信号；收端混频器303，被配置为基于收端本振信号对所接收的回波信号进行混频操作，得到收端模拟基带信号；模数转换器304，被配置为将收端模拟基带信号转换为收端数字基带信号；收端基带数字模块305，被配置为对收端数字基带信号进行处理，以实现目标检测和/或无线通信，例如，得到目标的诸如距离、速度、角度、高度及微运动特性等参数信息。
本公开实施例中，通过发端基带数字模块201产生的两路理想的I路数字基带信号和Q路数字基带信号，经由数模转换模块202后，可以得到非常理想的复信号，且该复信号的相位可以通过发端基带数字模块201精确控制。通过如图8或如图9所示的信号收发链路中的接收机结构，能够有效获取信号发射链路的射频信号的相位信息，从而可以实现多天线的相位调制。
在一些示例性实施方式中，信号发射链路还可以包括：功率放大器205，其中，功率放大器205，被配置为对移相后的射频信号进行功率放大并将放大后的信号输出至发射天线。
在一些示例性实施方式中，信号发射链路还可以包括：发射天线206，其中，发射天线206，被配置为将放大后的信号向预设空间区域辐射。
在一些示例性实施方式中，信号接收链路还可以包括接收天线301，其中，接收天线301，被配置为接收回波信号，回波信号为信号发射链路所发射的信号被目标物反射和/或散射而形成的信号。
在一些示例性实施方式中，收端本振信号可以为扫频信号，或者，收端本振信号可以为单音信号。
本公开实施例中，在上述信号收发链路中，针对信号发射链路中的发端正交调制器204所接收的TX-LO信号与信号接收链路中的收端混频器303所接收的RX-LO信号的频率可相同。例如，假设发端基带数字模块201输出的信号为x MHz的正弦波(sine wave)，则TX-LO信号和RX-LO信号则可同为z GHz的正弦波(sine wave)，其中，x、z均为正数，一般可在0～1000之间。
下面通过图8所示的信号收发链路对本公开的原理进行介绍。如前所述，对于FMCW雷达系统而言，信号发射链路可以有两种发波方案：1)发端本振信号扫频，发端数字基带信号单音；2)发端本振信号单音，发端数字基带信号扫频。假设发端本振信号TX_LO、发端数字基带信号、调制后的发射信号分别用TLO(t)、BB(t)和TX(t)来表示，并用下标I和q表示I路信号和Q路信号，用上标a表示其复信号形式，则在两种发波方案下，信号发射链路各阶段的信号可以表示如下：
1)发端本振信号扫频，发端数字基带信号单音：



2)发端本振信号单音，发端数字基带信号扫频：



其中，为FMCW信号的扫频斜率，fbb为发端数字基带信号的起始频率，ftlo为发端本振信号的起始频率，为发端数字基带信号的初始相位，为发端本振信号的初始相位。
假设图8所示的信号接收链路中的收端本振信号RX_LO用RLO(t)来表示，本实施例中，假设收端本振信号RX_LO为扫频信号，则RLO(t)可以表示为：
其中，frlo为收端本振信号的起始频率，Φ0为收端本振信号的初始相位，那么，信号发射链路发射的射频信号，经过目标反射/散射后产生回波信号，经过接收天线301、收端混频器303和收端低通滤波器307后可得：
其中，τ代表信号发射链路发射的射频信号经过目标反射/散射后返回信号接收链路的时延。
上式说明：上述两种扫频方式，均可以通过控制发端数字基带信号的初始相位来进行精确的相位调制，从而实现高精度高准确度的移相，避免了在高频进行直接移相。
在一些可选的实施例中，接收天线301可通过芯片的外设端口连接，形成在诸如PCB板等载体上。同时，在另一些可选的实施例中，接收天线也可集成在芯片的封装上形成AiP或者AoP，即具有封装天线的芯片结构。
在一些示例性实施方式中，信号接收链路还可以包括低噪声放大器(Low Noise Amplifier，LNA)306，设置在接收天线301和收端混频器303之间，对接收天线301接收的回波信号进行低噪声放大后，再送入收端混频器303。
在一些示例性实施方式中，信号接收链路还可以包括串联连接的低通滤波器(Low Pass Filter，LPF)307和高通滤波器(High Pass Filter，HPF)308，设置在收端混频器303和模数转换器304之间，低通滤波器307和高通滤波器308组成带通滤波器，用于滤除带外噪声。
在一些示例性实施方式中，如图8所示，在信号接收链路中，收端混频器303可以为实数混频器，模数转换器304可以为实数模数转换器。
本公开实施例中，虽然信号发射链路采用数字移相架构，但是，信号接收链路可包括正交接收架构或非正交接收架构的接收机，因此，能够有效的兼容各种架构的接收链路的传感器，有效降低整个收发链路系统的开发成本。
在另一些示例性实施方式中，如图9所示，在信号接收链路中，收端混频器303可以为正交混频器，模数转换器304可以为正交模数转换器。
为了匹配数字移相器架构的信号发射链路，本公开实施例将信号接收链路中的收端混频器303调整为IQ解调器(IQ Demodulator)，同时将模数转换器304调整为IQ ADC，经接收天线接收的回波信号依次经上述的低噪声放大器306、收端混频器303、低通滤波器307、高通滤波器308及模数转换器304处理后，转换为IQ数字基带信号，后续的收端基带数字模块305对该IQ数字基带信号处理可得到目标的诸如距离、速度、角度、高度及微运动特性(即微多普勒)等参数信息。
当收端混频器303为正交混频器且收端本振信号为扫频信号时，收端本振信号RX_LO可以表示为：
在另一些示例性实施方式中，信号接收链路的收端本振信号除了为式(9)或式(11)所示的扫频信号外，还可以为式(12)或式(13)所示的单音信号。
收端混频器303为实数混频器：RLO(t)＝cos(2πfrlot+Φ0)  (12)。
收端混频器303为正交混频器：
当收端本振信号为单音信号时，只需要在收端基带数字模块305中增加数字域的信号处理流程(包括数字域混频操作)，同样可以得到需要的数字基带信号。
综上所述，本公开实施例根据不同的发射方案和接收方案的搭配组合(例如，发端采用数字基带信号单音、本振信号扫频还是采用数字基带信号扫频、本振信号单音；收端采用实数混频器、实数模数转换器还是采用正交混频器、正交模数转换器；收端采用单音本振信号还是采用扫频本振信号)，可以拓展出多种系统级别的技术方案。
图10为本公开实施例提供的另一种收发链路的示意图，图11为本公开实施例提供的一种包含TX IQ Mod、RX IQ De-Mod和LO Freq Diff的收发链路的示意图，图12为本公开实施例提供的一种基于图11所示结构结合BIST的收发链路的示意图，图13为本公开实施例提供的一种包含TX IQ Mod、BIST IQ Mod和RX IQ De-Mod的收发链路的示意图。
下面基于本公开实施例提供的所记载的发射链路结构，针对其所构成的收发链路进行说明：
如图10所示，一种收发链路，可包括发射链路和接收链路等。发射链路(即发射机)可包括依次连接的数字基带信号源(Baseband)、直接数字频率合成器(TXDDFS)、IQ数模转换器(IQ DAC)、低通滤波器(LPF)、IQ调制器(IQ Modulator)、功率放大器(power amplifier，PA)等，同时经功率放大器放大后的信号经发射天线向预设空间区域进行辐射。接收链路则可包括依次连接的低噪声放大器(low noise amplifier，简称LNA)、实数混频器(Real Mixer)、跨阻放大器(Trans-Impedance Amplifier，简称TIA)、低通滤波器(LPF)、高通滤波器(High-Pass Filter，简称HPF)、实数数模转换器(Real ADC)等，即经接收天线接收的回波信号依次经上述的LNA、Real Mixer、TIA、LPF、HPF及Real ADC处理后，转换为实数数字基带信号，后续的数字信号处理模块对该实数数字基带信号处理可得到目标的诸如距离、速度、角度、高度及微运动特性等参数信息。
其中，上述收发链路中，针对发射链路中的IQ调制器所接收的TX-LO信号与接收链路中的Real Mixer所接收的RX-LO信号的频率可相同。例如，如图10所示，若是Baseband输出的信号为x MHz的正弦波(sinewave)，则TX-LO信号和RX-LO信号则可同为z GHz的正弦波(sinewave)。
在图10所示的实施例中，其发射链路采用的数字移相架构，而接收链路则可采用模拟架构的元器件，即不用采用IQ的元器件的，所以能够有效的兼容模拟架构的接收链路的传感器，有效降低整个收发链路系统的开发成本。
可选的，在本申请的实施例中，接收链路可包含有接收天线，即该接收天线可通过芯片的外设端口连接，形成在诸如PCB板等载体上。同时，一些可选的实施例中，接收天线也可集成在芯片的封装上形成AiP或者AoP，即具有封装天线的芯片结构。
在一些可选的实施例中，为了匹配数字移相器架构的发射链路，可针对接收链路对应进行相关的调整，如图11所示的收发链路中，可包含基于图10中类似的发射链路架构和接收链路(为了避免赘述，相同的部分具体在此便不予阐述)，将图10中接收链路中的Real Mixer调整为IQ解调器(IQ Demodulator)，同时将Real ADC调整为IQ ADC，即此时接收链路则可包括依次连接的低噪声放大器LNA)、IQ解调器(IQ Demodulator)、跨阻放大器(TIA)、低通滤波器(LPF)、高通滤波器(HPF)、IQ数模转换器(IQADC)等，即经接收天线接收的回波信号依次经上述的LNA、IQ Demodulator、TIA、LPF、HPF及IQ ADC处理后，转换为IQ数字基带信号，后续的数字信号处理模块对该IQ数字基带信号处理可得到目标的诸如距离、速度、角度、高度及微运动特性(即微多普勒)等参数信息。
同时，基于图11所示的收发链路进行自校准时，只要将发射链路的信号输出端口与接收链路的信号输入端口直接通过传输线连接，即发射链路通过该传输线直接将发射信号发送至接收链路中，以在不经过发射天线和接收天线情况下，实现收和/或发链路的自校准操作。其中，此时发射链路中的IQ调制器所接收的TX-LO信号与接收链路中的IQ Demodulator所接收的RX-LO信号之间具有一定的频偏。例如，如图11所示，若是Baseband输出的信号为x MHz的正弦波(sinewave)，则TX-LO信号可为z GHz的正弦波(sinewave)，此时RX-LO信号经下混频器(即接收链路中的IQ Demodulator)、低通滤波、高通滤波处理后，转为数字信号，以便进行TX IQ失衡校准。
在一些可选的实施例中，如图11所示，可通过增加接收链路(如图中所示的Receiver，RX)对发射链路(如图中所示的Transmitter，TX)进行校准，并通过发射链路中的TXIQ不平衡补偿单元基于校准的数据进行补偿操作。同时，也可通过复用实际用于信号发收的接收链路(如图中所示的Receiver，RX)对发射链路(如图中所示的Transmitter，TX)进行校准，通过发射链路和/或接收链路中的TX IQ不平衡补偿单元基于校准的数据进行补偿操作。其中，图11是针对TX IQ失衡的信号链路。由于TX谐波信号问题的信号链路与TX IQ失衡的信号链路的工作原理相似，可以将图11中的TX IQ失衡补偿单元替换为TX HD3补偿单元用于解决TX HD3的问题。在其他的实施例中也可进行类似的实施，为了阐述简便，后续便不予赘述。
在一些可选的实施例中，基于图11所示结构的基础上，为了实现收发链路精准校准，图11所示的接收链路的IQ Demodulator的RX-LO端口设置内部自测试模块(Built-in Self-Test，简称BIST)模块，即如图12所示的，在图11所示收发链路结构的基础上，在接收链路的IQ Demodulator的RX-LO端口设置IQ BIST架构，以实现在接收链路的IQ Demodulator的RX-LO端口输入具有预设频偏的LO信号。例如，通过相位角度转换器和IQ调制器(IQ Modulator)等所构成IQ BIST，利用所接收的诸如TX-LO信号经相位角度转换器通过IQ调制器，以基于该IQ调制器的另一路输入信号BIST-LO的频偏信号形成频偏后的信号输入至IQ Demodulator的RX-LO端口。例如，若TX-LO的信号为zGHz的正弦波，而BIST-LO的信号为y MHz的正弦波，则得到输入至IQ Demodulator的RX-LO端口的频偏后的信号为(zGHz-yMHz)。需要说明的是，不同的实施例之间，x、y、z均为示意值，具体的数值可相同或不相同。
在一些可选的实施例中，基于图12中所示收发链路结构的IQ BIST架构，还可通过复用收发链路中的接收链路针对数字移相器架构的发射链路进行校准；其中，在其他实施例中，涉及到利用接收链路对发射链路的校准操作，以及利用发射链路对接收链路的校准操作，均可通过复用实际进行信号收发的链路中对应的接收链路或者发射链路实现上述的校准操作，也可通过增设对应的校准接收链路或者校准发射链路来实现对实际进行信号收发的链路中对应的发射链路或者接收链路的校准操作。
可选的，该IQBIST可包括相位角度转换器和IQ调制器(IQ Modulator)，相位角度转换器用于实现对数字架构的发射链路中I路和Q路的分别校准，而IQ调制器的另一路输入信号BIST-LO则可为y MHz的正弦波(sine wave)，用于模拟发射信号被目标反射所形成回波信号相关的特性，其中图12中的x、y、z均为正数，且x≠y≠z，一般可在0至1000之间。
可选的，在图12所示的收发链路中，还可在发射链路中(例如在的TXDDFS与IQ DAC之间)设置TX IQ不平衡补偿单元(TX IQ Imbalance Compensation)，和/或在接收链路中(例如在Real ADC之后)设置TX IQ不平衡补偿单元(TX IQ Imbalance Compensation)，即可基于上述自校准操作所得到的校准参数(或系数)对所发射和/或接收的信号进行补充，以解决诸如IQ不平衡等问题。
在一些可选的实施例中，基于图12所示的结构，如图13所示，可将上述的IQ BIST模块设置在发射链路的信号输出端口与接收链路的信号输入端口之间，即，发射链路通过该IQ BIST模块直接将发射信号发送至接收链路中，以在不经过发射天线和接收天线情况下，实现收链路和/或发链路的自校准操作。
需要说明的是，在图11至13所示的发射链路结构中，其仅示例出IQ补偿单元(TX IQ Imbalance compensation)，在实际的应用中，也可基于实际需求，于发射链路中增加LO补偿单元(TXLO leakage compensation)和HD3补偿单元(TXHD3compensation)等，以构成包含有LO补偿单元(TX LO leakage compensation)、IQ补偿单元(TX IQ Imbalance compensation)和/或HD3补偿单元(TX HD3 compensation)等单元的补偿单元(TX compensation)。
图14为本公开实施例提供的一种包含辅助电路和BIST IQ Mod的收发链路的示意图，图15为本公开实施例提供的另一种包含辅助电路和BIST IQ Mod的收发链路的示意图。
如图14所示，一种收发链路，结合图9和图13所示的结构及相关描述，该收发链路可包括发射链路、接收链路和校准链路。其中发射链路可包括依次连接的TX数字基带信号源(TX Baseband)、直接数字频率合成器(TX DDFS)、补偿单元(Compensation)、IQ数模转换器(IQDAC)、低通滤波器(LPF)、IQ调制器(IQ Modulator)和功率放大器(power amplifier，PA)等，同时经功率放大器放大后的信号经发射天线向预设空间区域进行辐射。接收链路则可包括依次连接的低噪声放大器(low noise amplifier，简称LNA)、实数混频器(Real Mixer)、跨阻放大器(Trans-Impedance Amplifier，简称TIA)、高通滤波器(High-Pass Filter，简称HPF)、可变自动增益放大器(Variable Gain Amplifier，简称VGA)、实数数模转换器(RealADC)和用于TXRF校准(Calibration)的RX Baseband等，即经接收天线接收的回波信号依次经上述的LNA、Real Mixer、TIA、HPF、VGA及Real ADC等处理后，转换为实数数字基带信号，后续的数字信号处理模块对该实数数字基带信号处理可得到目标的诸如距离、速度、角度、高度及微运动特性等参数信息。
其中，针对发射链路，通过设置在TX DDFS与IQ DAC之间的补偿单元(TX compensation)可包括LO补偿单元(TX LO leakage compensation)、IQ补偿单元(TX IQ Imbalance compensation)以及HD3补偿单元(TX HD3 compensation)等单元，用以实现针对数字移相器架构的发射链路中的LO leakage、IQ Imbalance及HD3等对应的补偿操作。
在一些可选的实施例中，在发射链路与接收链路之间还可设置有校准模块，该校准补偿单元可被配置用于复用接收链路对上述的数字移相器架构的发射链路进行校准等操作。同时，补偿单元则可基于该校准模块的校准操作所获取的参数或系数，以在发射链路端就可以实现对发射信号的补偿操作。而在其他的实施例中，还可同时或单独的在接收链路中设置对应的接收补偿单元，即此时接收补偿单元可基于上述校准操作所获取的参数或系数等，以在接收链路端实现对回波信号的补偿。
如图14所示，上述的校准模块可包括BIST单元和辅助电路单元(auxiliary circuit)等，即发射链路的输出端口通过BIST单元和辅助电路单元连接至接收链路中Real Mixer与Real ADC之间的任一节点上，如发射链路中的IQ Modulator基于x MHz的数字移相基带信号和z GHz的LO信号，生成(z GHz土x MHz)的射频信号后，经输出端口输出至BIST单元，该BIST单元对于接收的射频信号进行y MHz的频偏操作后得到(z GHz土x MHz土y MHz)的模拟回波信号，再利用辅助单元中的IQ De-Modulator进行降频后，以得到预设的中频信号(z GHz土x MHz土yMHz-z GHz＝±x MHz土y MHz)后，该中频信号输入至接收链路中预设节点，以实现对发射链路中的校准操作。
可选的，辅助电路单元可为正交解调器电路，该辅助电路单元的输出端可连接至接收链路中的TIA与HPF之间的节点、HPF与VGA之间的节点、VGA与Real ADC之间的节点中的任一节点上。另外，为了最大程度的复用接收链路的结构，一路发射链路的输出端口通过BIST单元和辅助电路单元后，I、Q两条支路还可分别连接至不同的发射链路上，即如图14所示，即通过复用两路接收链路来对一路发射链路进行校准。其中，在完成针对发射链路的校准后，可利用上述的补偿模块(TX compensation)中的LO补偿单元(TX LO leakage compensation)、IQ补偿单元(TX IQ Imbalance compensation)和/或HD3补偿单元(TX HD3 compensation)等补偿单元，用以基于校准所得到的参数实现针对数字移相器架构的发射链路中的LO leakage、IQ Imbalance及HD3等问题对应的补偿操作。
在一些的可选的实施例中，上述的BIST单元可包括依次连接的相位角度转换器和IQ调制器(IQ Modulator)，辅助电路单元可包括依次连接的LNA、IQ De-Modulator和TIA，即相位角度转换器接收从发射链路输出的射频信号，而IQ Modulator的一个输入端连接相位角度转换器的输出端，另一个输入端则接收y MHz的BIST-LO信号，用以生成预设的回波信号。LNA则将接收的回波信号经放大后发送至IQ De-Modulator-个输入端，IQ De-Modulator另一个输入端则用于接收z GHz的RX-LO信号后，该IQ De-Modulator的两个输出支路(即I支路和Q支路)分别经TIA后连接至各自对应的接收链路中相应的节点，以将生成的预设的中频信号输出至两个接收链路，进而在实现校准操作的同时，更加高效的复用接收链路设计。
需要说明的是，针对本公开实施例提供的的校准操作，若是发射链路发射的是扫频信号，在实际的校准操作时，可采用TX LO信号为单tone信号进行逐点校准；同时，也可以采用TXLO信号为扫频信号进行大带宽的校准操作，甚至可采用扫频带宽校准一次实现针对全频段的扫频信号的校准操作。
基于图14所示的结构，为了进一步的将数字移相器架构的发射链路中，诸如HD3、LO Leakage、IQ Imbalance等压制预设的程度，可通过级联至少两个BIST单元的方式来实现；如图15所示，通过两个串联的BIST单元，可将因上述缺陷而导致的噪声压制在-50dB的程度，从而有效的降低相关链路模拟器件的开发设计的难度。
在一些可选的实施例中，基于本申请实施例所记载的数字移相器架构的发射链路的基础上，在针对IQ Imbalance进行校准及补偿操作时，可在时域(Time-Domain)基于频谱分析得到IQ Imbalance的补偿系数，也可在频域(Frequency-Domain)基于频谱谱峰比值得到IQ Imbalance的补偿系数。
在一些可选的实施例中，为了进一步提升IQ Imbalance补偿系数的精准性，还可通过迭代校准及补偿的方式来逼近理想的补偿系数，也可通过多观测校准及补偿的方式来得到理想的补偿系数。
例如，针对迭代校准及补偿的方式，可基于前后两次校准补偿的补偿系数之间的大小关系，或者该两次校准补偿的补偿系数之间的差值是否满足预设迭代条件，来确定是否停止迭代操作，并以停止迭代操作时所得到的补偿系数作为当前场景中，最终的补偿系数进行后续的操作。针对多观测校准及补偿的方式，则可通过多次(例如三次)校准补偿操作后，分别对各次操作得到的测量数据进行FFT(快速傅里叶变换)并获取相应的幅度和相位信息后，可将测量做差并归一化处理得到相关的数据，并构建出观测矩阵；后续基于对该观测矩阵求逆的得到数据反向求解出对应的补偿系数。
在一些可选的实施例中，基于上述得到IQ Imbalance补偿系数类似的思想，也可采用诸如迭代校准及补偿的方式，或者多次观测校准及补偿的方式来得到LO leakage和/或HD3的补偿系数。
在上述带有补偿单元的发射机各示例中提及了关于解决发射机中谐波失真的问题。经研究发现，一些谐波失真的原因可能来自于发射机中的混频器等包含非线性特点的器件。
以图16为例，图16为本公开实施例提供的混频器421的结构示意图。如图16所示，混频器421包括电压电流转换器(V/I Converter)、电流开关(Current Switch)和电流电压转换器(I/VConverter)。其中，所述电压电流转换器将接收的电压信号转换为电流信号；所述电流开关与所述电压电流转换器和所述第二信号发生器相连，用于利用本振信号对电压电流转换器输出的电流信号进行处理；所述电流电压转换器与所述电流开关相连，用于对所述电流开关输出的电流信号转换为电压信号。
在上述结构中，由于电压电流转换器设置有晶体管放大器，基于晶体管放大器的非线性特性以及基带信号的频率较低的特性，使得电压电流转换器输出的电流信号存在基带信号对应的谐波信号。例如，由基带的三阶非线性所引起的HD可简称为HD3。类似地，五阶非线性所引起的谐波称为HD5。在电流开关处理电压电流转换器输出的电流信号时，谐波的频率经过上变频处理后变为射频频段。由于抑制射频频段的谐波信号的操作复杂度较高，硬件成本较高。如果对射频频段的谐波信号不进行去除，会影响雷达收发的信号质量，进而影响雷达测量的准确度。
所述补偿单元用于将所生成的抵消信号输入至信号发射链路，以抵消所述射频信号中的谐波信号。其中，所述补偿单元与所述第一信号发生器相互独立。
为此，补偿单元可包括抵消信号发生器。利用补偿单元输出的抵消信号能够抑制射频信号中的谐波信号，减少射频信号中谐波分量，从而提高发射机输出的射频信号的信号质量。
在本公开实施例提供的，针对信号发射链路中的谐波信号，补偿单元利用反馈或根据发射波的特点，将所生成的抵消信号输入至信号发射链路，以抵消所述信号发射链路所输出的射频信号中的谐波信号。其中该抵消信号具有与射频发射电路中所传输的谐波信号具有相位相反、幅值相近等特点，以达到抑制谐波信号的目的。
在一些示例中，补偿单元根据第一信号发生器所产生的基带信号的相位、频率、或幅值，甚至与LO信号合并的路径长度等参数，产生包含抵消作用的补偿信号。
例如，图5中示出了一种将补偿单元接入信号发射链路中的发射机示例。在图5所示结构中，补偿单元为TX补偿单元。TX补偿单元中包含可根据发射波的特点生成抵消信号发生器(未予图示)。所述抵消信号发生器可举例为如图6中所示的TX HD3补偿单元。
其中，基带处理器(图5中简称为基带框)控制TX DDFS生成的正交数字的基带信号，TX补偿单元根据所述正交数字信号的参数，生成正交补偿信号，将正交补偿信号和正交数字信号合并并发送给IQ DAC以转换为模拟的基带信号。通过LPF滤波处理后，交由混频器(即，图5中的IQ调制器)进行混频处理，得到基于TX LO信号和模拟基带信号混频的射频信号，PA对混频信号进行放大处理后通过发射天线输出。其中，该补偿信号抵消了射频发射电路中至少部分的谐波信号，如HD3谐波信号。因此，所发射的射频信号中的杂波将大大减少。射频信号可为FMCW信号。
在另一些示例中，补偿单元根据经射频发射电路反馈而得到的谐波信息，来生成补偿信号。参见图17，图17为图5所示发射机中补偿单元的结构示意图。如图17所示，所述补偿单元包括采集电路和抵消信号发生器。
其中，所述采集电路耦接所述射频发射电路，用于采集所述射频发射电路中的信号，得到采集信号。所述采集信号(或称采样信号)能反映谐波信号中的波形信息(又称谐波参数)，如主频信号的相位、谐波信号的相位，谐波信号的频率，主频信号的频率，谐波信号的功率，主频信号的功率等。
需要说明的是，所述采集信号所反映的谐波参数与采集电路所能采集的信号所携带的信息相关。例如，采集电路为一种功率采集电路，则相应的采集信号包含主频的功率。又如，采集电路利用接收机的至少部分电路，则采集信号反映主频信号的相位、谐波信号的相位、谐波信号的频率、主频信号的频率、谐波信号的功率、主频信号的功率等。
上述至少一种谐波参数可藉由模拟电路来提取。例如，通过耦合器和功率检测器来输出主频信号的功率。或利用雷达芯片中的数字电路在频域计算的优势，来提取谐波参数。例如，通过耦接射频发射电路，来获取与耦接处传输的信号相同的信号作为采集信号。该采集信号中携带主频信号和谐波信号。采集信号经ADC转为数字信号，并交由数字电路在频域计算以得到更多谐波参数。
在一种实现方式中，所述采集电路的输入端与所述混频器的输出端或信号检测端相连。该种方式可检测到因电压电流转换器所产生的谐波信号，且具有简化的采集电路。例如图18、19所示结构中的一种连接方式，该采集电路的输入端连接在电压电流转换器和电流开关之间的检测端，并与ADC耦接。
在另一种方式中，所述采集电路的输入端连接所述射频发射电路的射频输出端或射频检测端相连。其中，所述射频输出端举例为射频发射电路的输出端。射频检测端举例为射频发射电路中至少一级PA的输入端或输出端。该种方式可采集到射频发射电路中的更准确的谐波参数，但具有较复杂的电路结构。
在一些包含BIST模块的芯片中，采集电路可藉由BIST模块中的部分或全部电路获取采集信号。例如，参见图19所示，采集电路的输入端耦接射频输出端，其依次包括下变频器、滤波器等，并连接IQ ADC，以输出数字的采集信号。其中，下变频器、滤波器等可复用BIST模块或接收机。
所采集的采集信号输入至抵消信号发生器。其中，所述抵消信号发生器为补偿单元中的至少一种电路。该抵消信号发生器与所述第一信号发生器相连，使得射频发射电路接收的信号同时包括基带信号和抵消信号。
例如，抵消信号发生器包括前述提及的抵消信号发生器，以及提取谐波信息的数字电路。其中，提取谐波信息的数字电路可独立配置，或至少部分的共用于雷达芯片中数字电路。
其中，提取谐波信息的数字电路举例利用雷达芯片中用于处理差频基带信号的数字电路来提取谐波频率、主频频率、主频功率等谐波信息，并提供给抵消信号发生器。抵消信号发生器根据所接收的参数生成抵消信号。
又如，提取谐波信息的数字电路提取采集信号中的主频幅度，并根据预设的主频幅度和谐波幅度之间的差异，计算出谐波幅度。抵消信号发生器根据所计算出的谐波幅度和预配置的其他谐波参数，生成谐波信号补偿信号。其中，该预配置的各谐波参数可根据雷达芯片待发射的主频信号的扫频范围、相位等计算得到。
所述抵消信号发生器中的抵消信号发生器可与第一信号发生器独立配置，或至少部分的共用。例如，抵消信号发生器所产生的抵消信号输入第一信号发生器，使得第一信号发生器所输出的基带信号中包含有所述抵消信号。其中，抵消信号发生器可包括三次谐波发生器和五次谐波发生器。
又如，所述补偿单元中还包括加法器，耦接抵消信号发生器和第一信号发生器，以合并第一信号发生器所产生的基带信号以及所述抵消信号发生器所产生的抵消信号。本实施例中，抵消信号包括三次谐波发生器所产生的抵消三次谐波的抵消信号Signal_HD3，和五次谐波发生器所产生的抵消五次谐波的抵消信号Signal_HD5。抵消信号Signal_HD3和Signal_HD5以及第一信号发生器所产生的基带信号通过加法器合并，并输出至射频发射电路。
综上可见，本申请提供的采用反馈方式向射频发射电路中预输入抵消信号的发射机各电路示例，可在不同环境下，保证芯片所发射的射频信号中含有足够低的谐波信号。
为了在芯片使用过程中能按照芯片的实际运行环境有效地对谐波信号进行抑制，例如考虑环境温度对半导体器件的影响等，本申请还提供一种利用反馈机制对上述发射机中的谐波信号进行信号抵消方法，包括：
步骤10、对信号发射链路中的信号进行采集操作，得到采集信号；其中，所述信号发射链路用于产生雷达探测用的射频信号，其中所述射频信号中包含谐波信号。
步骤20、检测所述采集信号，生成用于抵消所述谐波信号的抵消信号，并输出至所述信号发射链路。
本申请实施例提供的方法，对信号发射链路中的信号进行采集操作，得到采集信号，并利用采集信号生成抵消信号，并输出至信号发射链路，从而利用抵消信号抑制射频信号中的谐波信号，减少射频信号中谐波分量，从而提高发射机输出的射频信号的信号质量，进而提高接收机对射频信号的接收性能。
下面结合附图11至图20，举例发射机及其工作过程：
例如，图11中示出了一种利用反馈机制提取发射机中的谐波信息，使得补偿单元产生相应的抵消信号的示例。在图11所示结构中，以补偿单元包括TX HD3补偿单元为例。TX HD3补偿单元根据接收信号的波形特点生成补偿信号。其中，该反馈机制可在雷达芯片的校准模式下执行，以防止削弱雷达芯片正常探测时的信号发射功率。
发射机中的基带处理器(如图11中的基带框)控制TX DDFS生成的正交数字的基带信号，经TX补偿单元产生的正交数字的抵消信号合并后发送给IQ DAC，以转换为模拟的基带信号。该模拟的基带信号中混合有用于抵消发射链路中谐波信号的模拟的抵消信号。该模拟的基带信号通过LPF滤波处理后进入第一混频器(即，图11中的IQ调制器)。第一混频器利用TX LO对接收的滤波信号进行混频处理，得到射频信号。该射频信号经耦合通过接收机输出至补偿单元中的TX HD3校准电路(如图11中的TX HD3校准框)。其中，所述TX HD3校准电路可视为一种提取谐波信息的数字电路。
在接收机中，LNA对发射机输出的信号进行放大处理后，输出给第二混频器(即，图11中的IQ解调器)，得到解调信号，将解调信号发送给跨阻放大器进行放大处理，再依次经过LPF和HPF后，再经过IQ ADC进行模数转换操作后发送给TX HD3校准电路。该TX HD3校准电路从反馈的信号中提取发射机中的谐波信息，并通过上层控制器转换为产生抵消信号所需的参数，并提供给TX HD3补偿单元。其中，TX HD3校准电路所获取的谐波信息举例包括以下一种或多种参数：谐波信号(或主频信号)的初始相位、起始频率、截止频率、频率变化时长、中心频率等。TX HD3校准单元或上层控制器根据谐波信息确定补偿单元中用于生成抵消信号的参数，如初始相位、抵消信号的频率，时延等。
需要说明的是，上述各示例中涉及三次谐波和/或五次谐波等谐波的抵消操作，可根据发射机的需求而定。
在一些可选的实施例中，基于本申请实施例所记载的数字移相器架构的发射链路的基础上，在针对HD3进行校准及补偿操作时，基于有源混频器中HD3的产生主要源头为V/I Converter的非线性中三次谐波，所以可通过如图18所示的基于三次方模块的补偿架构，或者如图19所示的基于三倍频波形发生器的补偿结构来实现。
图20为本公开实施例提供的一种基于数字移相器架构发射链路的校准补偿示意图。如图20所示，基于本公开实施例提供的针对IQ Imbalance、LO leakage和HD3校准补偿操作的相关技术内容：针对IQ Imbalance的补偿操作，可通过补偿BB(基带)信号的共轭信号来反向抵消镜像分量的方式实现，且该补偿操作方式不受IQ Imbalance的校准方式的影响。针对LO Leakage的补偿则可通过调节IQ两路的DC分量(即直流偏置)来实现，同样该LO Leakage的校准方式对其补偿方案不产生影响。针对HD3，由于正交混频器V/I Converter的3阶谐波失真是产生HD3的主要来源，而谐波失真会受到直流偏置的影响，因此当发射链路的LO Leakage和HD3均需要校准时，则需要在进行LO Leakage的校准后再进行HD3的校准，以确保HD3校准的精准性能。
另外，基于数字三次方模块的数字预补偿架构和基于倍频波形发生器模块的数字预补偿架构的HD3的补偿方式，会直接影响后续的校准方案和后续的补偿流程。具体的：
在一个可选的实施例中，针对基于数字三次方模块的数字预补偿架构，可先校准并补偿LO Leakage后，在稳定的DC偏置下，校准出HD3问题的根本来源，即HD3的补偿系数；随后校准IQ Imbalance，并继续补偿IQ Imbalance后，分别对IQ两路依据IQ Imbalance预补偿的结果，去补偿三次谐波失真。
在一个可选的实施例中，针对基于倍频波形发生器模块的数字预补偿架构，可在校准并补偿LO Leakage后，校准得到HD3的补偿系数，并在稳定的DC偏置下校准IQ Imbalance，以及补偿IQ Imbalance；后续通过补偿后的结果，分别对IQ两路依据IQ Imbalance预补偿的结果，去补偿三次谐波失真。
在另一个可选的实施例中，针对基于倍频波形发生器模块的数字预补偿架构，可校准并补偿LO Leakage后，校准得到HD3的补偿系数，并在稳定的DC偏置下校准IQ Imbalance，以及补偿IQ Imbalance；后续通过补偿后的结果，分别计算出IQ两路信号的实际波形，HD3的补偿系数，反算出需要预补偿的3倍频和5倍频的波形信息。
在另一个可选的实施例中，针对基于倍频波形发生器模块的数字预补偿架构，可先校准并补偿LO Leakage，然后通过多次(如三次)观测以同时校准出HD3和IQ Imbalance的补偿系数，之后再通过再次观测(如两次)来校准出HD3镜像位置处的补偿系数；最后通过HD3和HD3镜像位置处的补偿系数反算出需要预补偿的3倍频和5倍频系数。需要说明的是，本公开实施例提供的的观测用以表示测试以及不同测试结果比较分析等操作。
参见图20所示结构可知，该采集电路具有两条采集支路，且两条采集支路能够动态切换；其中，一条采集支路的输入端连接在电压电流转换器和电流开关之间；另一条采集支路的输入端连接在功率放大器的输出端，且该采集支路设置有IQ解调器；此外，图20所示结构中，该采集电路还设置有多路选择器(Multiplexers)，其中该多路选择器的输入端分别连接两个采集支路的输出端，输出端用于输出所述采集信号。
在图18至图20所示结构中，该采集信号可以为模拟信号，即，该采集电路的输出端与IQ ADC相连；或者，该采集信号可以为数字信号，则该采集电路至少包括IQ ADC。
需要说明的是，当信号发射链路发送的射频信号不是正交信号时，则图18至图20中采集电路可以利用非正交元器件来完成。例如，可以利用单端的下变频混频器代替IQ解频器，可以使用单端的模数转换器代替IQ ADC。
下面对本申请实施例提供的校准链路进行说明：
在图7所示校准链路中，校准链路可以对包括模拟移相的发射主通路(例如，图1A所示的信号发射链路)进行校准，或者，对包括数字移相器的发射主通路(例如，图4所示的信号发射链路)进行校准。除此以外，本申请实施例还可以对接收主通路进行校准。
基于上述说明可知，本公开实施例系统一种信号传输主通路的校准链路，具体如图21A所示。
参见图21A可知，信号传输主通路用于传输电磁波信号，所述校准链路集成在包括所述信号传输主通路的集成电路中，由于校准链路集成于包括有所述信号传输主通路的集成电路中，能实时地校准信号传输主通路，也无需外部设备对信号传输主通路进行校准操作。
所述校准链路至少连接至所述信号传输主通路与所述信号传输主通路对应的天线之间，以便校准链路与信号传输主通路构成信号传输操作，从硬件结构上支持对信号传输主通路的校准操作。
具体的，所述校准链路，可配置为用于对信号传输主通路进行校准，得到校准信息；
在本申请实施例中，该信号传输主通路可以为对用于发射射频信号的发射主通路，或者，用于接收回波信号的接收主通路。
在信号传输主通路为发射主通路时，所述校准链路至少获取信号传输主通路输出的信号，基于对发射主通路输出的信号进行接收操作，以得到校准信息；在信号传输主通路为接收主通路时，所述校准链路至少向接收主通路输出信号，基于信号传输主通路对所述校准链路输出的信号的处理结果，得到校准信息。
对应的，所述信号传输主通路，可配置为用于基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路传输电磁波信号。
由于所述信号传输主通路基于校准信息进行校准操作，可以有效提升信号传输主通路的信号传输质量，从而使得校准后的信号传输主通路所传输的电磁波信号的信号质量得到提升。
进一步的，由于校准链路集成于包括有所述信号传输主通路的集成电路中，因此，校准链路能够根据需要实时地校准信号传输主通路；另外，由于校准链路与信号传输主通路的运行环境(如，温度、湿度、老化时长)存在高度的相似性，因此，校准链路的校准操作与信号传输主通路的运行环境保持高度的一致，使得校准链路能够得到更加精确的校准信息，从而提高信号传输主通路的信号处理性能。
在所述信号传输主通路出厂前和在所述信号传输主通路在正式投入所使用后中至少一个条件下，所述校准链路对信号传输主通路执行校准操作。
其中，集成电路出厂前可以为量产测试或者在集成为无线电设备后量产测试时。
在量产测试时可以模拟信号传输主通路的不同运行环境，基于上述运行环境进行校准，可以得到较为通用的校准信息。
在一些可选的实施例中，所述集成电路出厂前可在量产测试或者在集成为无线电设备后量产测试时进行校准，并将校准获得的校准信息预存存储介质中，后续在无线电设备运行时直接调用该校准信息对所传输的信号进行校准。
在信号传输主通路作为无线电设备的一部分正式投入使用后，由于不同无线电设备的使用时长、运行环境存在一定差异，会对信号传输主通路的性能造成不同程度的影响，因此，在信号传输主通路正式投入使用后，还可以利用校准链路对信号传输主通路进行校准。
具体的，可以在信号传输主通路传输信号的间隙，所述校准链路对所述信号传输主通路进行校准操作。其中，在信号传输主通路为发射主通路时，所述传输信号的间隔可以相邻两次执行射频信号的发射操作之间的空闲时间；在信号传输主通路为接收主通路时，所述传输信号的间隔可以相邻两次执行回波信号的接收操作之间的空闲时间。
在一些可选的实施例中，在满足启动校准操作的预设条件时，校准链路对信号传输主通路进行校准操作。
具体的，基于集成电路的运行环境变化对于其性能参数的影响，以及器件老化等不良影响，设置启动校准操作的条件，例如预定的时间(如间隔1分钟、1小时或1天等预设时间段，具体可基于应用场景进行设定，如主要考虑环境变化影响时则可设置较短的时间(如30s，或者每帧信号的间隙等)，如考虑器件老化则可设置为1年，且还可基于老化变化参数设置非等间隔的时间片段)；同时，还可以基于诸如温度、压力、湿度等外部环境的变化来设置校准启动的条件，例如温度上升5℃启动一次，也可设置当温度达到预设值时启动校准操作等，对应压力、湿度等参数也可以对应单独或综合(如温度达到80℃、湿度达到70％等)设置启动校准操作的条件。同时也可基于历史的校准数据对当前集成电路或电子设备的运行情况进行预测或评估，一旦达到预设的阈值还可以直接进行示警、启动安全功能等操作。
对于信号传输主通路，在校准链路每完成一次校准操作后，均采用最新得到的校准信息进行校准操作，并利用校准操作进行信号传输操作。即，校准链路基于所述校准链路上一次校准所得到的校准信息，对所传输的信息进行实时补偿。
由于校准链路每完成一次校准操作后最新得到的校准信息均能准确地反映信号传输主通路在当前的运行环境的校准信息，因此，利用最新得到的校准信息进行校准操作，能够保证信号传输主通路所使用的校准信息的准确性，从而为提高信号传输主通路的信号传输质量提供支持。
在一个示例性实施例中，所述校准链路所传输的信号为单音信号。其中，单音信号，也叫单频信号，即只有一个恒定频率的信号，可以是正弦信号或是余弦信号。其中单音信号的频率可以根据接收该单音信号的电路结构进行设置。
在对信号传输主通路进行校准操作时，使用单音信号作为校准链路传输的校准信号，可以降低校准操作中信号处理的复杂度，提高校准效率。
另外，在校准链路传输的信号为正交信号时，校准链路的元器件为正交器件。
图21B为图21A所示的校准链路的部署示意图。如图21B所示，集成电路中设置有至少两路所述信号传输主通路。其中，至少两路信号传输主通路通常为信号传输功能相同的至少两个主通路，例如，均为发射主通路或均为接收主通路。
在集成电路中，信号传输功能相同的主通路通常集成部署在电路板中的同一区域，且相邻的两个主通路之间存在间隔。
考虑到信号传输干扰而信号传输距离所产生的损耗，可以在信号传输功能相同且相邻的两个信号传输主通路之间设置校准链路，使得该校准链路分别与两个信号传输主通路相连。以此类推，可以在集成电路设置至少一路校准链路。其中任一路所述校准链路，可配置为用于对至少两路所述信号传输主通路进行校准。
进一步的，所述电磁波信号可为雷达信号，所述信号传输主通路包括回波信号的接收主通路和/或射频信号的发射主通路。
图22A为本公开实施例提供的校准链路与发射主通路之间的连接示意图。如图22A所示，所述校准链路对应包括所述发射主通路对应的辅助接收链路，其中所述辅助接收链路连接于所述发射主通路与对应所述发射天线之间，可配置为用于对所述发射主通路所发射的射频信号进行校准。
在一个示例性实施例中，所述发射主通路包括中频处理电路和射频处理电路，其中所述中频处理电路用于对基带信号进行处理，得到中频信号；所述射频处理电路用于对中频信号进行处理，得到射频信号。
辅助接收链路先对发射单元中的中频处理电路进行校准操作，以使得校准完成后的中频处理电路输出的中频信号是经过校准后的信号，从而提高射频处理电路接收的信号质量，降低输入信号对射频处理电路的校准过程中产生误差。
在完成中频处理电路的校准后，再利用校准单元再对发射单元中的射频处理电路进行校准。由于利用校准后的中频处理电路输出的信号作为射频处理电路的输入信号，可以降低中频处理电路的性能偏差对射频处理电路的校准的影响，提高射频处理电路的校准操作的准确性。
进一步的，所述校准链路还包括所述辅助接收链路对应的校准发射链路；其中，所述校准发射链路，可配置为用于对所述辅助接收链路进行校准操作；对应的，所述辅助发射链路基于所述校准接收链路得到的校准信息进行校准操作，其中校准后的辅助接收链路对所述发射主通路进行校准操作。
利用校准发射链路对辅助接收链路进行校准操作，可以提高辅助接收链路的信号处理性能，利用信号性能得到提高的辅助接收链路对发射主通路进行校准，可以提高发射主通路的校准操作的准确性。
图22B和图22C为本公开实施例提供的校准链路与接收主通路之间的连接示意图。如图22B所示，所述校准链路对应包括所述接收主通路对应的辅助发射链路。
所述接收主通路包括与接收天线依次相连的射频单元和中频单元；其中，所述中频单元用于对接收的信号进行中频处理，并输出给所述射频单元；所述射频单元用于对中频单元输出的信号进行射频处理并输出。其中，所述校准链路包括射频辅助发射链路和中频辅助发射链路中的至少一个。
请参见图22B，所述中频辅助发射链路连接于所述接收主通路的中频信号输出端，可配置为用于对所述接收主通路所接收的回波信号进行下降频后得到的中频信号进行校准；其中，所述中频单元，可配置为基于所述中频辅助发射链路得到的校准信息进行校准操作，其中校准后的中频单元对射频单元输出的信号进行信号处理。
请参见图22B，所述射频辅助发射链路，连接于所述接收主通路与对应所述接收天线之间，可配置为用于对所述接收主通路所接收的回波信号进行校准。其中，所述射频单元，可配置为基于所述射频辅助发射链路得到的校准信息进行校准操作，其中校准后的射频单元对经所述接收天线接收的回波信号进行信号处理。
在所述辅助发射链路包括中频辅助发射链路和射频辅助发射链路时，可以按照如下步骤对接收主通路进行校准操作，可包括：利用中频辅助发射链路对中频单元进行校准操作；利用校准后的中频单元对射频辅助发射链路进行校准；利用校准后的射频辅助发射链路对所述射频单元进行校准。
由于利用校准后的中频单元对射频辅助发射链路进行校准，可以提高射频辅助发射链路的信号处理性能，利用信号性能得到提高的射频辅助发射链路对射频单元进行校准，可以提高射频单元的校准操作的准确性。
可选的，在图22A、图22B以及图22C中，信号传输主通路和天线之间还可以设置有功率检测器(Power Detector，PD)，其中PD可以用于对信号主通路的功率信息进行检测。
在图22A和图22C中，所述校准链路可以连接在PD和信号传输主通路之间。实现对信号传输主通路的校准操作；或者，所述校准链路可以连接在PD和天线之间，以实现对信号传输主通路和PD的校准操作。
下面对校准链路中的各链路进行分别说明：
图23A、图23B、图23C以及图23D均为本公开实施例中发射主通路对应的校准链路中各链路的结构示意图。其中：
图23A为图22A中辅助接收链路的结构示意图。如图23A所示，所述辅助接收链路包括：第一混频器，可配置为用于利用接收操作所使用的本振信号对接收的信号进行混频处理；第一功率放大器，可配置为用于对第一混频器输出的信号进行放大处理；第一滤波单元，可配置为用于对接收的信号进行滤波处理，得到滤波信号；第一实数数模转换器，可配置为用于将数字的滤波信号转换为模拟的滤波信号。
其中，第一混频器和第一功率放大器构成的电路，用于模拟回波信号的接收主通路中的射频处理功能；第一滤波单元和第一实数数模转换器构成的电路，用于模拟回波信号的接收主通路中的中频处理功能。从信号传输功能可知，上述辅助接收链路还可用于构成信号的接收链路。
图23B为图23A中辅助接收链路的另一结构示意图。如图23B所示，所述辅助接收链路还包括：第一加法器，与所述第一实数数模转换器相连，可配置为用于根据第一混频器使用的本振信号的泄露信号，对所述第一实数数模转换器输出的信号进行补偿。
第一加法器能够针对辅助发射链路中第一混频器所使用的本振信号的泄露问题，对第一实数数模转换器输出的信号进行补偿，保证辅助接收链路中传输的信号的准确性。
图23C为图22A中校准发射链路的结构示意图。如图23C所示，所述校准发射链路包括：第一信号产生器，可配置为用于输出数字的原始信号；第二实数数模转换器，可配置为用于将数字的原始信号的转换为模拟的原始信号；第二滤波单元，可配置为用于对原始信号进行滤波处理，得到滤波信号；第二功率放大器，可配置为用于对滤波信号进行放大处理，得到放大信号；第二混频器，可配置为用于利用发射操作所使用本振信号对所述放大信号进行混频处理。
其中，第一信号产生器和第二实数数模转换器构成的电路，用于模拟射频信号的发射主通路中的中频处理功能；第二功率放大器和第二混频器构成的电路，用于模拟射频信号的发射主通路中的射频处理功能。从信号传输功能可知，上述辅助接收链路还可用于构成信号的发射链路。
图23D为图23C中校准发射链路的另一结构示意图。如图23D所示，所述校准发射链路还包括第二加法器和带通滤波器(Band Pass Filter，BPF)中的至少一个，其中所述第二加法器，连接于第一信号产生器与第二实数数模转换器之间，可配置为根据第二混频器所使用的本振信号的泄露信号，对第一信号产生器输出的信号进行补偿；所述带通滤波器，与所述第二混频器相连，可配置为用于对所述第二混频器输出的信号进行滤波处理，并将滤波处理后的信号发送给校准单元。
其中，第一加法器能够针对校准发射链路中的本振信号的泄露问题，对第一信号产生器输出的的信号进行补偿，保证校准发射链路输出的信号的准确性。
其中，BPF可被配置用于滤除校准发射链路的LO leakage所产生的直流信号。即校准辅发射单元可被配置用于产生多个稳定的不同频率的单音(Tone)信号，以实现对辅助接收链路的校准操作。
其中，校准发射链路使用的本振信号与辅助接收链路使用的本振信号由于使用同一本振信号的产生电路，因此，二者的本振信号的频率存在差值，例如，可以满足如下条件，即，RF Tone GEN LO-校准单元LO＝5MHz或10MHz。
图24为本公开实施例提供的发射主通路对应的校准链路的应用示意图。如图24所示，辅助接收链路可包括依次连接的混频器Mixer、TIA、LPF、HPF、IQ ADC、加法器和RF校准模块(RF  Calib)，即通过将混频器的一个输入端接收本振信号，另一个输入端则在沿信号传输方向(即图中所示的箭头方向)连接至发射主通路PD之前的节点，或者在移相器(模块)之后的任一节点。例如连接至PA的输出端(同步实现对PA的校准)、PA的输入端等，以通过该校准单元对发射通路进行校准操作。其中，发射主通路中的本振信号的频率与辅助接收链路中本振信号的频率之间具有设定的差频，以使得该两个信号之间存在错频，以模拟真实的收发信号回路。
在一个可选的实施例中，为了进一步提升校准精度，针对辅助接收链路还可设置对应的校准电路(即校准发射链路单元)，例如图24所示校准发射链路，可包括依次连接的TX DDFS、加法器、Real DAC、LPF、放大器、乘法器和带通滤波器(Band Pass Filter，简称BPF)，其中的加法器可被配置用于对TX LO泄漏(TX LO leakage Waveform)进行校准补偿，而乘法器则可被配置用于补偿RF Tone Gen LO泄漏(leakage)，BPF可被配置用于滤除校准辅助单元的LO leakage所产生的直流信号。即校准辅助单元可被配置用于产生多个稳定的不同频率的单音(Tone)信号，以实现对校准单元的校准操作。
在一些可选的实施例中，如图24所示，可先利用校准发射链路对辅助发射链路进行校准，然后利用校准后的辅助接收链路单元对包括诸如PA在内的发射主通道(Transmitter)的校准，例如对PA输出端的PD、发射主通道中的移相器、DAC到PA输出的总增益以及频率响应等器件及电路的校准。
具体的，如图24所示，可先通过利用校准发射链路产生多个稳定的且不同频率的单音信号对辅助接收链路单元进行校准，然后基于校准后的辅助接收链路来校准发射主通路的IQ不平衡、本振泄漏、频率响应不一致等问题。
图25A、图25B、图25C以及图25D均为本公开实施例中接收主通路对应的校准链路中各链路的结构示意图。其中：
图25A为图22A中中频辅助发射链路的第一结构示意图。如图25A所示，所述中频辅助发射链路包括：所述中频辅助发射链路包括第一信号源和第三实数数模转换器；其中第一信号源，可被配置为用于输出数字的中频校准信号；第三实数数模转换器，可被配置为用于将数字的中频校准信号的转换为模拟的中频校准信号。其中，可以根据中频单元接收的信号的频率，设置中频校准信号的频率。
利用第一信号源生成数字的中频校准信号，可以提高中频校准信号的产生效率，再通过第三实数数模转换器进行信号的转换，以便得到中频单元支持接收的信号。
在一个示例性实施例中，第一信号源可以对接收的数字信号进行分频处理，其中分频处理得到的信号频率在中频单元支持的频率范围内。
在另一个示例性实施例中，还可以通过数字移相器对信号进行处理，将数字移相器处理后的信号作为中频校准信号。例如，参见图25A所示，所述第一信号源包括第二信号产生器和数字移相模块；其中，所述第二信号产生器被配置为生成初始信号；以及所述数字移相模块被配置为采用数字正交调制方式对所述初始信号进行频率搬移和/或移相处理。
图25B为图22A中中频辅助发射链路的第二结构示意图。如图25B所示，所述中频辅助发射链路包括所述中频辅助发射链路包括第四实数数模转换器、第三混频器和第一平方器；其中所述第四实数数模转换器，可被配置为用于将预设的数字的信号转换为模拟的信号；所述第三混频器，可被配置为用于将第四实数数模转换器输出的信号和本振信号进行混频处理，得到混频信号；所述第一平方器，可被配置为用于对混频信号进行平方处理，得到所述中频校准信号。其中，该第四实数数模转换器的个数可以为一个或至少两个。
利用第三混频器利用本振信号与第四实数数模转换器输出的信号进行混频处理，得到近似单音信号的混频信号，再通过第一平方器对混频信号进行平方处理，得到单音信号，作为所述中频校准信号。
图25C为图22A中射频辅助发射链路的结构示意图。如图25C所示，所述射频辅助发射链路包括；第二信号源，可被配置为用于输出原始信号；第三滤波单元，可被配置为用于对原始信号进行滤波处理，得到滤波信号；第三功率放大器，可被配置为用于对滤波信号进行放大处理，得到放大信号；第四混频器，可被配置为用于利用本振信号对所述放大信号进行混频处理，得到所需信号。
其中，第二信号源和第三滤波单元构成的电路，用于模拟信号的发射主通路中中频信号的处理功能；第三功率放大器和第四混频器构成的电路，用于信号的发射主通路中射频信号的处理功能。从信号传输功能可知，该射频辅助发射链路可用作信号的发射链路。
在一些示例性实施例中，第二信号源可以利用直接数字频率合成器生成数字信号，可以提高信号的产生效率，再通过数模转换器进行信号的转换，得到所述原始信号。
图25D为图25C所示射频辅助发射链路的另一结构示意图。如图25D所示，所述射频辅助发射链路包括正交补偿单元、第二平方器和第三加法器中的至少一个，其中：
所述正交补偿单元，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可被配置为用于在所述第二信号源输出的初始信号为正交信号时，对接收的初始信号的正交失衡进行补偿。在第二信号源输出的正交信号后，通过对正交信号之前进行正交失衡的补偿，可以有效避免后续信号处理中正交失衡的进一步恶化，有效保证信号质量。
第二平方器，与所述中频单元的信号输入端相连，可配置为对所述第四混频器输出的信号进行处理，并输出给校准后的中频单元。利用第二平方器可以有效去除因正交失衡问题造成的第四混频器输出的信号存在的残留边带问题，保证信号输出的准确性，从而为射频辅助发射链路的校准提供支持。
第三加法器，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可配置为根据第四混频器所使用的本振信号的泄露信号，对第二信号源输出的信号进行补偿。第三加法器能够针对校准发射链路中的本振信号的泄露问题，对第二信号源输出的信号进行补偿，保证射频辅助发射链路输出的信号的准确性。
图26为本公开实施例提供的接收主通路对应的校准链路的应用示意图。如图26所示，接收主通路可包括与接收天线依次连接地LNA、混频器、TIA、LPF、HPF、Real ADC、加法器和基带处理模块(BB processor)。其中：
中频辅助发射链路可包括依次连接的分频器和实数ADC，其中中频辅助发射链路中的实数ADC的输出端与TIA的信号输入端相连；中频辅助发射链路可包括依次连接的TX DDFS、IQ失衡补偿模块、加法器、IQ DAC、LPF、TIA以及混频器，其中混频器的输出端可切换地与连接在PD与接收天线之间，或者，连接在TIA的信号输入端。
在图26所示结构中，可以利用中频辅助发射链路输出中频校准信号，实现对中频单元的校准，至少完成对接收主通路中基带处理模块和Real ADC的校准；再利用射频辅助发射链路向TIA的信号输出端输出信号，利用基带处理模块对信号的处理结果，实现对射频辅助发射链路的校准，至少完成对TX LO泄露和IQ失衡的校准操作；最后，射频辅助发射链路向接收主通路中LNA的信号输入端输出信号，对接收主通路中的RX LO泄露问题和RX频率响应问题进行校准。其中，射频辅助发射链路可被配置用于产生多个稳定的不同频率的单音(Tone)信号，以实现对接收主通路中射频单元的校准操作。可以将射频辅助发射链路的输出端连接至PD与接收天线之间，或者，连接至LNA的信号输入端等，从而实现包括对LNA的输入端的PD、LNA至Real ADC的总增益以及频率响应的辅助校准。
图27A和图27B为本公开实施例提供的中频辅助发射链路的应用示意图。图27A和图27B的区别在于，图27A和图27B所使用的DAC的个数不同。其中：
图27A所使用的DAC的个数为一个，将DAC1作为信号源，通过混频器利用接收主通路所使用的本振信号对DAC1输出的信号进行下变频处理，再通过平方器去除混频器输出的信号的残留边带，得到所需的中频校准信号。
图27B所使用DAC的个数为两个，其中DAC1产生的信号的比特数高于DAC2产生的信号的比特数，例如，DAC1为10-bit DAC，DAC2为1-bit DAC；另外，图27B中两个DAC输出的信号的处理方式也存在差异，DAC1输出的信号由混频器处理，而DAC2输出的信号由分频器处理，因此，DAC1的时钟频率要明显低于DAC2的时钟频率，其中DAC1的时钟频率可以与接收主通路中的ADC的时钟频率一致，如可以为60MHz，而DAC2的时钟频率要为更高的频率，可以为1.2GHz。
其中，分频器输出的信号经DAC2处理得到中频校准信号，其中，该中频校准信号可以切换地输出至TIA的信号输入端、HPF的信号输入端、VGA的信号输入端或者ADC的信号输入端，从而完成对中频单元中不同元件或元件组合的校准。
本公开实施例提供一种信号传输链路包括：信号传输主通路，可配置为用于传输电磁波信号；以及校准链路，集成于包括有所述信号传输主通路的器件中，以用于对所述信号传输主通路进行校准；其中，所述信号传输主通路基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路执行信电磁波信号的传输操作。
需要说明的是，上述校准链路可为本申请任一实施例所阐述的任一校准链路。其中，信号传输主通路与所述校准链路集成于同一芯片内或同一PCD板或同一PCB板上，以支持对信号传输主通路的实时检测。
另外，在信号传输主通路邻近区域有部署空间时，可以优先将校准链路部署在距离该信号传输主通路尽量近的距离，以降低信号传输中损耗和干扰对校准结果的影响。
本申请实施例提供的信号发射链路，由于校准链路集成于包括有所述信号传输主通路的集成电路中，使得校准链路能实时对信号传输主通路进行校准操作，且校准链路的校准操作可以不受信号传输主通路的运行环境的变化而变化，使得信号传输主通路能够得到更加精确的校准信息，从而提高信号传输主通路的信号处理性能。
另外，本公开实施例提供的集成电路具有相邻且间隔设置的两条信号传输主通路以及设置在所述两条信号传输主通路之间的上文任一所述的校准链路，其中所述校准链路供所述两条信号传输主通路共有。
进一步的，该集成电路，可包括上述任一项的信号收发链路。可选的，该集成电路可为毫米波雷达芯片(chip or die)。在一些可选的实施例中，所述集成电路可为AiP(Antenna-In-Package，封装内天线)芯片结构、AoP(Antenna-On-Package，封装上天线)芯片结构或AoC(Antenna-On-Chip，片上天线)芯片结构。
根据本公开的另一些实施例，本公开实施例还提出一种电磁波器件。该电磁波器件可包括天线，以及如前所述的集成电路。其中，集成电路与天线电连接，用于收发电磁波信号。例如，该电磁波器件可包括：承载体、如上述任一实施例所述的集成电路和天线等，所述集成电路可设置在承载体上；天线可设置在承载体上(即此时该天线可为设置PCB板上的天线，也可为RoP(Radiator on Package)天线结构，即通过在封装上设置辐射结构Radiator，并在Radiator周围用球围成波导结构，RF信号通过辐射结构过渡到该波导结构中，再由波导结构转换到外接天线)，或者与所述集成电路集成为一体器件设置在所述承载体上(即此时该天线可为AiP、AoP或AoC结构中所设置的天线)；其中，所述集成电路与天线连接(即此时传感芯片或集成电路未集成有天线，如常规的SoC等)，用于收发电磁波信号。其中，承载体可以为印刷电路板PCB。
本公开实施例提供了一种设备，可包括：设备本体；以及设置于设备本体上的如上述的电磁波器件；其中，电磁波器件用于目标检测和/或通信，以向设备本体的运行提供参考信息。
本公开实施例还提供了一种电子设备，该电子设备可以通用计算设备的形式表现。电子设备的组件可以包括但不限于：至少一个处理单元、至少一个存储单元、连接不同系统组件(包括存储单元和处理单元)的总线、显示单元等。其中，存储单元存储有程序代码，程序代码可以被处理单元执行，使得处理单元执行本说明书描述的根据本公开各种示例性实施方式的方法。存储单元可以包括易失性存储单元形式的可读介质，例如随机存取存储单元(RAM)和/或高速缓存存储单元，还可以进一步包括只读存储单元(ROM)。
存储单元还可以包括具有一组(至少一个)程序模块的程序/实用工具，这样的程序模块包括但不限于：操作系统、一个或者多个应用程序、其它程序模块以及程序数据，这些示例中的每一个或某种组合中可能包括网络环境的实现。
总线可以为表示几类总线结构中的一种或多种，包括存储单元总线或者存储单元控制器、外围总线、图形加速端口、处理单元或者使用多种总线结构中的任意总线结构的局域总线。
电子设备也可以与一个或多个外部设备(例如键盘、指向设备、蓝牙设备等)通信，还可与一个或者多个使得用户能与该电子设备交互的设备通信，和/或与使得该电子设备能与一个或多个其它计算设备进行通信的任何设备(例如路由器、调制解调器等等)通信。这种通信可以通过输入/输出(I/O)接口进行。并且，电子设备还可以通过网络适配器与一个或者多个网络(例如局域网(LAN)，广域网(WAN)和/或公共网络，例如因特网)通信。网络适配器可以通过总线与电子设备的其它模块通信。应当明白，尽管图中未示出，可以结合电子设备使用其它硬件和/或软件模块，包括但不限于：微代码、设备驱动器、冗余处理单元、外部磁盘驱动阵列、RAID系统、磁带驱动器以及数据备份存储系统等。
例如，本公开实施例中的电子设备还可包括：设备本体；以及设置于设备本体上的如上述任一实施例中所阐述的电磁波器件；其中，该电磁波器件可用于实现目标检测和/或无线通信等功能。
具体地，在上述实施例的基础上，在本公开的一个可选的实施例中，电磁波器件可以设置在设备本体的外部，或者设置在设备本体的内部，而在本公开的其他可选的实施例中，电磁波器件还可以一部分设置在设备本体的内部，一部分设置在设备本体的外部。本公开实施例对此不作限定，具体可视情况而定。
在一个可选的实施例中，上述设备本体可为应用于诸如智慧城市、智能住宅、交通、智能家居、消费电子、安防监控、工业自动化、舱内检测(如智能座舱)、医疗器械及卫生保健等领域的部件及产品。例如，该设备本体可为智能交通运输设备(如汽车、自行车、摩托车、船舶、地铁、火车等)、安防设备(如摄像头)、液位/流速检测设备、智能穿戴设备(如手环、眼镜等)、智能家居设备(如扫地机器人、门锁、电视、空调、智能灯等)、各种通信设备(如手机、平板电脑等)等，以及诸如道闸、智能交通指示灯、智能指示牌、交通摄像头及各种工业化机械臂(或机器人)等，也可为用于检测生命特征参数的各种仪器以及搭载该仪器的各种设备，例如汽车舱内生命特征检测、室内人员监控、智能医疗设备、消费电子设备等。
本公开实施例还提供了一种非瞬时性计算机可读存储介质，其上存储有计算机可读指令，当指令被处理器执行时，使得处理器执行如上述的信号发射方法。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、或者网络设备等)执行根据本公开实施方式的上述方法。
软件产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以为但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
计算机可读存储介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可读程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。可读存储介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。可读存储介质上包含的程序代码可以用任何适当的介质传输，包括但不限于无线、有线、光缆、RF等等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本公开操作的程序代码，程序设计语言包括面向对象的程序设计语言-诸如Java、C++等，还包括常规的过程式程序设计语言-诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络，包括局域网(LAN)或广域网(WAN)，连接到用户计算设备，或者，可以连接到外部计算设备(例如利用因特网服务提供商来通过因特网连接)。
上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被一个该设备执行时，使得该计算机可读介质实现前述功能。
本领域技术人员可以理解上述各模块可以按照实施例的描述分布于装置中，也可以进行相应变化唯一不同于本实施例的一个或多个装置中。上述实施例的模块可以合并为一个模块，也可以进一步拆分成多个子模块。
根据本公开的实施例，提出一种计算机程序，包括计算机程序或指令，该计算机程序或指令被处理器执行时，可以执行以上描述的方法。在一个可选的实施例中，上述集成电路可以为毫米波雷达芯片。集成电路中的数字功能模块的种类可以根据实际需求确定。例如，在毫米波雷达芯片，收端基带数字模块可以用于诸如距离维多普勒变换、速度维多普勒变换、恒虚警检测、波达方向检测、点云处理等，用于获取目标的距离、水平角、俯仰角、速度、高度、微多普勒运动特性、形状、尺寸、表面粗糙度及介电特性等信息。
需要说明的是，无线电器件可通过发射及接收无线电信号实现诸如目标检测和/或通信等功能，以向设备本体提供检测目标信息和/或通讯信息，进而辅助甚至控制设备本体的运行。
例如，当上述的设备本体应用于先进驾驶辅助系统(即ADAS)时，作为车载传感器的无线电器件(如毫米波雷达)则可辅助ADAS系统实现诸如自适应巡航、自动刹车辅助(即AEB)、盲点检测预警(即BSD)、辅助变道预警(即LCA)、倒车辅助预警(即RCTA)、泊车辅助、后方车辆示警、防撞、行人探测等应用场景。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的较佳实施例及所运用技术原理，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开专利的保护范围由所附的权利要求范围决定。

Claims (21)

  1. 一种信号传输主通路的校准链路，所述信号传输主通路用于传输电磁波信号，所述校准链路集成在包括所述信号传输主通路的集成电路中，所述校准链路至少连接至所述信号传输主通路与所述信号传输主通路对应的天线之间；其中：
    所述校准链路，可配置为用于对信号传输主通路进行校准，得到校准信息；
    其中，所述信号传输主通路，可配置为用于基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路传输电磁波信号。
  2. 如权利要求1所述的校准链路，其特征在于：所述校准链路在所述集成电路出厂前、在所述集成电路发/收信号的间隙中至少一个对所述信号传输主通路进行校准，并基于所述校准链路上一次校准所得到的校准信息，对所传输的信息进行实时补偿。
  3. 如权利要求1所述的校准链路，其特征在于：所述集成电路中设置有至少两路所述信号传输主通路；其中，任一路所述校准链路，可配置为用于对至少两路所述信号传输主通路进行校准。
  4. 如权利要求1所述的校准链路，其特征在于，所述校准链路所传输的信号为单音信号。
  5. 如权利要求1至4中任一项所述的校准链路，其特征在于：
    所述电磁波信号为雷达信号；
    所述信号传输主通路包括回波信号的接收主通路和/或射频信号的发射主通路，所述校准链路对应包括所述接收主通路对应的辅助发射链路和/或所述发射主通路对应的辅助接收链路，所述天线对应包括所述接收主通路对应的接收天线和/或所述发射主通路对应的发射天线；
    所述辅助接收链路连接于所述发射主通路与对应所述发射天线之间，可配置为用于对所述发射主通路所发射的射频信号进行校准；以及
    所述接收主通路包括与接收天线依次相连的射频单元和中频单元，对应的，所述辅助发射链路包括与所述中频单元对应的中频辅助发射链路和与所述射频单元对应的射频辅助发射链路中的至少一个，其中所述中频辅助发射链路连接于所述接收主通路的中频信号输出端，可配置为用于对所述接收主通路所接收的回波信号进行下降频后得到的中频信号进行校准；所述射频辅助发射链路连接于所述接收主通路与对应所述接收天线之间，可配置为用于对所述接收主通路所接收的回波信号进行校准。
  6. 如权利要求5所述的校准链路，其特征在于，所述辅助接收链路包括：
    第一混频器，可配置为用于利用接收操作所使用的本振信号对接收的信号进行混频处理；
    第一功率放大器，可配置为用于对第一混频器输出的信号进行放大处理；
    第一滤波单元，可配置为用于对接收的信号进行滤波处理，得到滤波信号；
    第一实数数模转换器，可配置为用于将数字的滤波信号转换为模拟的滤波信号。
  7. 如权利要求6所述的校准链路，其特征在于，所述辅助接收链路还包括：
    第一加法器，与所述第一实数数模转换器相连，可配置为用于根据第一混频器使用的本振信号的泄露信号，对所述第一实数数模转换器输出的信号进行补偿。
  8. 如权利要求5至7任一项所述的校准链路，其特征在于：
    所述校准链路还包括所述辅助接收链路对应的校准发射链路；
    其中，所述校准发射链路，可配置为用于对所述辅助接收链路进行校准操作；对应的，所述辅助发射链路基于所述校准接收链路得到的校准信息进行校准操作，其中校准后的辅助接收链路对所述发射主通路进行校准操作。
  9. 如权利要求8所述的校准链路，其特征在于，所述校准发射链路包括：
    第一信号产生器，可配置为用于输出数字的原始信号；
    第二实数数模转换器，可配置为用于将数字的原始信号的转换为模拟的原始信号；
    第二滤波单元，可配置为用于对原始信号进行滤波处理，得到滤波信号；
    第二功率放大器，可配置为用于对滤波信号进行放大处理，得到放大信号；
    第二混频器，可配置为用于利用发射操作所使用本振信号对所述放大信号进行混频处理。
  10. 如权利要求9所述的校准链路，其特征在于，所述校准发射链路还包括第二加法器和带通滤波器中的至少一个，其中：
    所述第二加法器，连接于第一信号产生器与第二实数数模转换器之间，可配置为根据第二混频器所使用的本振信号的泄露信号，对第一信号产生器输出的信号进行补偿；
    所述带通滤波器，与所述第二混频器相连，可配置为用于对所述第二混频器输出的信号进行滤波处理，并将滤波处理后的信号发送给校准单元。
  11. 如权利要求5所述的校准链路，其特征在于，所述中频辅助发射链路包括：
    所述中频辅助发射链路包括第一信号源和第三实数数模转换器；其中第一信号源，可被配置为用于输出数字的中频校准信号；第三实数数模转换器，可被配置为用于将数字的中频校准信号的转换为模拟的中频校准信号；
    或者，
    所述中频辅助发射链路包括第四实数数模转换器、第三混频器和第一平方器；其中所述第四实数数模转换器，可被配置为用于将预设的数字的信号转换为模拟的信号；所述第三混频器，可被配置为用于将第四实数数模转换器输出的信号和本振信号进行混频处理，得到混频信号；所述第一平方器，可被配置为用于对混频信号进行平方处理，得到所述中频校准信号。
  12. 如权利要求11所述的校准链路，其特征在于：
    所述第一信号源包括第二信号产生器和数字移相模块；其中，所述第二信号产生器被配置为生成初始信号；以及所述数字移相模块被配置为采用数字正交调制方式对所述初始信号进行频率搬移和/或移相处理。
  13. 根据权利要求5所述的校准链路，其特征在于，所述射频辅助发射链路还与所述中频单元的输入端相连；其中：
    在所述中频单元完成校准操作后，利用校准后的中频单元对射频辅助发射链路进行校准；利用校准后的射频辅助发射链路对所述射频单元进行校准。
  14. 根据权利要求5或13所述的校准链路，其特征在于，所述射频辅助发射链路包括；
    第二信号源，可被配置为用于输出原始信号；
    第三滤波单元，可被配置为用于对原始信号进行滤波处理，得到滤波信号；
    第三功率放大器，可被配置为用于对滤波信号进行放大处理，得到放大信号；
    第四混频器，可被配置为用于利用本振信号对所述放大信号进行混频处理，得到所需信号。
  15. 根据权利要求14所述的校准链路，其特征在于，所述射频辅助发射链路包括正交补偿单元、第二平方器和第三加法器中的至少一个，其中：
    所述正交补偿单元，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可被配置为用于在所述第二信号源输出的初始信号为正交信号时，对接收的初始信号的正交失衡进行补偿；
    所述第二平方器，与所述中频单元的信号输入端相连，可配置为对所述第四混频器输出的信号进行处理，并输出给校准后的中频单元；
    所述第三加法器，一端与所述第二信号源相连，另一端与所述第三滤波单元相连，可配置为根据第四混频器所使用的本振信号的泄露信号，对第二信号源输出的信号进行补偿。
  16. 一种信号传输链路，包括：
    信号传输主通路，可配置为用于传输电磁波信号；以及
    校准链路，集成于包括有所述信号传输主通路的器件中，以用于对所述信号传输主通路进行校准；
    其中，所述信号传输主通路基于所述校准链路得到的校准信息进行校准操作，其中校准后的信号传输主通路执行信电磁波信号的传输操作。
  17. 如权利要求16所述的信号传输链路，其特征在于，所述校准链路为权利要求1至15中任一项所述的校准链路。
  18. 如权利要求16或17所述的信号传输链路，其特征在于，所述信号传输主通路与所述校准链路集成于同一芯片内或同一PCD板或同一PCB板上。
  19. 一种集成电路，所述集成电路设置有至少两条信号传输主通路以及设置在所述两条相邻发射主通路之间的如权利要求1至15任一项所述的校准链路，其中所述校准链路供所述两条信号传输主通路共有。
  20. 一种电磁波器件，包括：
    承载体；
    如权利要求19所述的集成电路，设置在所处承载体上；
    天线，设置在所述承载体上，或者所述天线与所述集成电路集成为一体器件设置在所述承载体上；所述天线包括发射天线和接收天线；
    其中，所述集成电路与所述天线连接，用于发射电磁波信号和/或接收电磁波信号。
  21. 一种用户终端设备，包括：
    设备本体；以及
    设置于所述设备本体上的如权利要求20所述的电磁波器件；
    其中，所述电磁波器件用于目标检测和/或无线通信，以向所述设备本体的运行提供参考信息。
PCT/CN2024/099420 2023-06-14 2024-06-14 校准链路、信号传输链路、集成电路、电磁波器件和设备 Ceased WO2024255890A1 (zh)

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