WO2024256214A1 - Agencement de branche de pont semi-conducteur de puissance - Google Patents

Agencement de branche de pont semi-conducteur de puissance Download PDF

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Publication number
WO2024256214A1
WO2024256214A1 PCT/EP2024/065305 EP2024065305W WO2024256214A1 WO 2024256214 A1 WO2024256214 A1 WO 2024256214A1 EP 2024065305 W EP2024065305 W EP 2024065305W WO 2024256214 A1 WO2024256214 A1 WO 2024256214A1
Authority
WO
WIPO (PCT)
Prior art keywords
bridge
power semiconductor
individual
leg arrangement
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2024/065305
Other languages
English (en)
Inventor
Stephen Finney
Edward HORSLEY
Paul Judge
Mason PARKER
Philip Perry Waite
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Gamesa Renewable Energy AS
Original Assignee
Siemens Gamesa Renewable Energy AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP24155481.5A external-priority patent/EP4478614A1/fr
Application filed by Siemens Gamesa Renewable Energy AS filed Critical Siemens Gamesa Renewable Energy AS
Priority to CN202480038888.XA priority Critical patent/CN121359381A/zh
Priority to EP24731535.1A priority patent/EP4699221A1/fr
Publication of WO2024256214A1 publication Critical patent/WO2024256214A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0812—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
    • H03K17/08122—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Definitions

  • the present invention relates to a power semiconductor bridge leg arrangement, comprising a switching arrangement having a number of semiconductor switching elements connected between a first connection point and a second connection point, which are connected to a DC-voltage source, and a control circuit for controlling the number of semiconductor switching elements of the switching arrangement.
  • DC-loop inductances and inductances of the switching arrangement are designed such to be as low as possible. Controlling of the semiconductor devices is made such to reduce the rate of change of current (dl/dt) through the semiconductor device during turn-off by using higher value gate resistances at the cost of increased switching losses.
  • snubber circuits are connected in parallel with the semiconductor devices.
  • active gate driving may be used to actively shape the switching trajectory of the semiconductor device which however may result at some cost of increased switching losses, and significant unresolved challenges in implementing a closed-loop system.
  • Active gate driving may be used to facilitate current balancing between power semiconductor switching elements, such as Silicon-Carbide (SiC) -devices .
  • power semiconductor switching elements such as Silicon-Carbide (SiC) -devices .
  • SiC Silicon-Carbide
  • Drive strength based active gate driving adjusts the magnitude of the voltage or current applied to individual gates of switching elements over the switching transient, aiming to balance of the drain source voltage and drain currents.
  • Delay based active gate drivers apply delays to conventional drive signals applied to the individual gates. This compensates for the variants in threshold voltages between devices and allows for dynamic balancing of the drain source voltage and drain current.
  • the switching arrangement comprises at least two individual power semiconductor half-bridge modules connected in parallel between the f irst connection point and the second connection point .
  • Each half-bridge module comprises a controllable high- side semiconductor switch and a controllable low-s ide semiconductor switch being connected to a half-bridge midpoint .
  • Each half-bridge midpoint is connected to the midpoint of the bridge leg arrangement with a dedicated designed inductance .
  • the control circuit is adapted to individually control the switch operations of each semiconductor switch of the at least two individual power semiconductor half -bridge modules .
  • the term "half-bridge module" i s to be understood in the sense that it may compri se a power module with two semiconductor switche s , or it may be formed from two individual dedicated semiconductor switches connected with each other .
  • the power semiconductor bridge leg arrangement according to the invention represents , from an external converter perspective , a composite switch that can be operated a s a single bridge leg .
  • the number of individual power semiconductor half -bridge modules is arbitrary . In particular , the number of half-bridge modules may be even or odd due to the use of individual dedicated de signed inductances .
  • the bridge leg arrangement utilizes a combination of additional inductances and active-gate driving in terms of individually and independently controlling turn-on and turnoff gating signals of the individual semiconductor switches .
  • Current balancing is achieved in parallel half-bridges through a combination of the dedicated de signed inductances for current imbalance control purposes and to limit exces sive current mis-share as well as active gate-driving in terms of individually controlling the semiconductor switche s .
  • the bridge leg arrangement has the advantage that is does not rely upon precise matching of circuit impedance and device characteristic matching in order to achieve current sharing . Nonetheles s , it i s robust against characteri stic variation due to aging and environmental factors .
  • control circuit i s adapted to control the order in which the individual semiconductor switches of the at least two individual power semiconductor half-bridge modules are turned-on/turned-of f to control balancing of the currents flowing through each individual half -bridge module .
  • Thi s is achieved because the difference in halfbridge midpoint voltages result s in a current flowing between the parallel branches , limited in magnitude by the length of the timing s kew and the magnitude of the dedicated des igned inductances .
  • Opportunities to achieve active current balances are therefore present at every switching event ( i . e . , both turn-on and turn-off ) the power semiconductor bridge leg undergoes .
  • control circuit may be adapted to control the order of switching based on phase measurements of currents and/or voltages or based on a given schedule.
  • the timing skew between two individual bridge modules corresponds to the same order of the LC oscillation frequency of the power semiconductor bridge leg arrangement, i.e. , is of the same order of magnitude as the time period of the LC oscillation frequency of the power semiconductor bridge leg arrangement.
  • This preferred embodiment considers the effect of a parasitic inductance of a DC bus which may be a combination of any busbar/connection parasitic inductance, and the parasitic inductance of any DC bus capacitors. As a result of the employed staggered switching, the overall effective dl/dt though the DC bus parasitic inductance can be reduced.
  • the magnitude of this benefit for later switching devices may be maximized by selecting the applied timing skew such that the individual commutation loop current contributions from each individual bridge leg interferes with each other such that the overall dl/dt through the DC bus parasitic inductance is further reduced.
  • the skew required to achieve this is of the order of the time period of the LC oscillations between the output capacitance of the switching elements, and the combined busbar/DC capacitor /switching element package inductance. Reductions in the overshoot in current through the switching elements at turn-on can also be achieved by a similar mechanism of selecting a timing skew such that interference between the commutation loop currents results in a reduction in current overshoot magnitude.
  • the number of dedicated designed inductances corresponds to the number of individual power semiconductor half-bridge modules .
  • each half-bridge module is associated with a dedicated designed inductance.
  • the dedicated designed inductances may be composed of individual wound inductors or parasitic inductances of busbar or cabling used to connect the switching element together at the midpoint.
  • the semiconductor switches may be MOSFETs (Metal-Oxide- Semiconductor Field-Effect Transistor) or IGBTs (Insulated Gate Bipolar Transistor) , in particular based on Silicon- Carbide (SiC) or Silicon (Si) .
  • MOSFETs Metal-Oxide- Semiconductor Field-Effect Transistor
  • IGBTs Insulated Gate Bipolar Transistor
  • Fig. 1 shows a power semiconductor bridge leg arrangement according to the prior art .
  • Fig. 2 shows a power semiconductor bridge leg arrangement according to an embodiment of the invention.
  • Fig. 4 shows timing diagrams during turn-off of low-side semiconductor switches illustrating the current flow through the branches of half-bridges of the bridge leg arrangement .
  • Fig. 5 shows timing diagrams during turn-off of low-side semiconductor switches illustrating a reduced rate of change of voltage increase at the midpoint of the bridge leg arrangement .
  • Fig. 6 shows the bridge leg arrangement according to Fig. 2 together with commutation current loop paths through a DC bus for each of the half-bridges .
  • Fig. 7 illustrates the voltage across the low-side semiconductor switch of a conventional bridge leg arrangement .
  • Fig. 8 shows the voltage across the low-side semiconductor switches of the half-bridges of the bridge leg arrangement when considering skew between gatedriving signals according to the invention.
  • Fig. 1 shows a conventional power semiconductor bridge leg arrangement 1 according to the prior art.
  • the bridge leg arrangement 1 comprises a first connection point 2 of a busbar (DC+) which is connected to a positive terminal of a not shown voltage source.
  • a second connection point 3 of a busbar (DC-) is connected to a negative terminal of the not shown voltage source.
  • a midpoint 5 between the series-connected switching elements 6 represents an output of the semiconductor bridge leg arrangement 1.
  • each gate 6G is connected to a driver 6D.
  • the respective driver 6D receives a triggering signal from a control circuit 7 for controlling the number of semiconductor switching elements 6 in a predetermined way in order to connect the midpoint (output) 5 to the positive first connection point 2 or the negative second connection point 3.
  • the bridge leg arrangement 1 as shown in Fig. 1 may be used in an inverter in order to transform DC-current into AC- current. As known to the people skilled in the art, a bridge leg arrangement 1 as shown in Fig. 1 is provided for each phase of a multi-phase arrangement.
  • Fig. 2 illustrates a power semiconductor bridge leg arrangement according to the invention.
  • the switching arrangement 10 comprises at least two individual power semiconductor half-bridge modules 11, 12, 13 connected in parallel between the first connection point 2 and the second connection point 3.
  • three parallel power semiconductor half-bridge modules 11, 12, 13 are illustrated.
  • the number of half-bridge modules is arbitrary as long as the number of half-bridge modules is 2 or greater.
  • a series connection of one high-side semiconductor switch 11H, 12H, 13H and associated low-side semiconductor switch 11L, 12L, 13L is connected to a halfbridge midpoint 11M, 12M, 13M.
  • each half-bridge midpoint 11M, 12M, 13M is connected to the midpoint 5 of the bridge leg arrangement 1 with a dedicated designed inductance LI, L2, L3.
  • the dedicated designed inductances LI, L2, L3 are composed of individual wound inductors 21, 22, 23.
  • the dedicated designed inductances LI, L2, L3 may be parasitic inductances of busbar or cabling used to connect a respective half-bridge midpoint 11M, 12M, 13M to the midpoint 5 as well.
  • the not shown control circuit is adapted to individually control the switch operations of each semiconductor switch 11H, 11L, 12H, 12L, 13H, 13L of the at least two individual power semiconductor half-bridge modules 11, 12, 13, in particular with respect to the timing.
  • the power semiconductor bridge leg arrangement 1 is formed by the parallel connection of a plurality of individual half-bridges 11, 12, 13, with a dedicated designed inductance LI, L2, L3 connected at the midpoint 11M, 12M, 13M of each individual half-bridge 11, 12, 13 and individual gate-drivers 11DH, 11DL, 12DH, 12DL, 13DH, 13DL. From an external converter perspective, the bridge leg arrangement 1 constitutes and can be operated as a single bridge leg as shown in Fig. 1.
  • the control circuit is adapted to generate an individual dedicated control signal for each semiconductor switch 11H, 11L, 12H, 12L, 13H, 13L of the number of half-bridge modules 11, 12, 13 and provide this signal to its associated driver 11DH, 11DL, 12DH, 12DL, 13DH, 13DL.
  • the control circuit is adapted to skew the switching on/off triggering signals of each semiconductor switch 11H, 11L, 12H, 12L, 13H, 13L of each half-bridge module 11, 12, 13.
  • each individual power semiconductor half-bridge 11, 12, 13 By skewing the switching on/off gate triggering signals of each individual power semiconductor half-bridge 11, 12, 13 within the bridge leg arrangement 1 a mechanism for balancing the currents flowing through each half-bridge 11, 12, 13 that form the overall bridge leg arrangement 1 is achieved.
  • the respective balancing inductors 21, 22, 23 limit the magnitude of change in current during the switching transition.
  • By controlling the order in which the individual semiconductor switches 11H, 11L, 12H, 12L, 13H, 13L are turned-on/turned- off active control over the balancing of the currents In, I12, I13 (see Fig. 3) flowing through each individual halfbridge 11, 12, 13 can be achieved. This is because the difference in half-bridge midpoint voltages results in a current flowing between the parallel half-bridges 11, 12, 13, limited in magnitude by the length of the timing skew and the magnitude of the inductance of the inductors 21, 22, 23.
  • Timing skew between half-bridges is in the region between 5 ns and 100 ns, preferably in a range between 5 ns and 50 ns, and more preferably in a range between 5 ns und 25 ns.
  • the size of the required balancing inductors 21, 22, 23 is far below the size required for implementing converter level current control schemes .
  • Fig. 3 illustrates the bridge-leg arrangement 1 according to Fig. 2, in which in addition to the semiconductor elements and inductors respective voltages UHL, U , Ui 3L over the low- side semiconductor switches 11L, 12L, 13L, half-bridge currents In, In, I and a resulting overall voltage Ui 0 of the midpoint 5 of the bridge leg arrangement 1 are illustrated .
  • Fig. 4 shows timing diagrams during turn-off of the low-side semiconductor switches 11L, 12L, 13L in the respective halfbridges 11, 12, 13 and the midpoint currents In, In, In, InFig. 5 shows the timing diagram in which the resulting voltage U at the midpoint 5 of the bridge leg arrangement 1 is illustrated.
  • the time difference t 2 -ti and t 3 -t 2 , respectively, between the respective two control signals represents the above-mentioned time skew.
  • Fig. 6 illustrates the bridge leg arrangement 1 considering the inclusion of a parasitic inductance LDC of the DC bus. Commutation current loop paths through the DC bus for each of the half-bridges 11, 12, 13 within the semiconductor bridge leg are illustrated in addition. It is to be noted that a combination of any busbar/connection parasitic inductance and the parasitic inductions of any DC bus capacitors may form the parasitic inductance LDC. The following additional benefits arise from the skewing of the gate driving signals.
  • the overall effective dl/dt though the DC bus parasitic inductance LDC can be reduced due to the skewed switching of each switching switch 11H, 11L, 12H, 12L, 13H, 13L. This reduces voltage overshoot experienced by each of the semiconductor switches 11H, 11L, 12H, 12L, 13H, 13L during turn-off, as well as the energy-loss incurred during the switching transition of each individual device 11H, 11L, 12H, 12L, 13H, 13L.
  • the magnitude of this benefit can be increased by ensuring the skew corresponds to the same order of the LC oscillation frequency of the respective semiconductor switch 11H, 11L, 12H, 12L, 13H, 13L, resulting in further reductions in dl/dt across the parasitic inductance LDC due to destructive interference between the different commutation currents.
  • the skew could be selected through either experimental testing or simulation such that this destructive interference effect is maximized.
  • Figs . 7 and 8 show a comparison between device voltage overshoot during turn-off of the bridge leg arrangement 1 where Fig. 7 shows the behavior according to the prior art and Fig. 8 shows the behavior according to the bridge leg arrangement 1 of the invention.
  • the voltage across the low-side devices Un, U , Un when considering skew between gatedriving signals achieves reduced voltage overshoot across each semiconductor switch 11L, 12L, 13L.
  • Voltage overshoot across the low side semiconductor switch of the conventional half-bridge according to Fig. 1 is approximately 600 V. This can be taken from Fig. 7.
  • the voltage overshoot across the first switching device is approximately 350 V with an approximate 270 V overshoot across the second and third device (low side switching elements 11L, 13L) .
  • the simulation performed in Figs. 7 and 8 uses the same circuit parameters.
  • the proposed invention uses sub-microsecond delays to achieve balancing, meaning that the required timing skews are achievable on a FPGA (Field Programmable Gate Array) .
  • the bridge leg arrangement according to the invention does not rely upon precise matching of circuit impedance and device characteristic matching and is robust against characteristic variation due to aging and environmental factors .
  • the bridge leg arrangement according to the invention achieves current balancing in parallel half-bridge s through a combination of additional designed inductance s for limiting the magnitude of change in currents during the switching transition and active gate-driving in terms of introducing intentional timing s kew between .
  • the proposed bridge leg arrangement utilizes a combination of additional inductance s and active gate driving in terms of adding s kew between turn- on/turn-off gating signals of individual devices .
  • the additional inductances consist of dedicated designed inductances which are composed of individual inductors , either wound inductors or paras itic inductances of a busbar or cabling .
  • wound inductors or para sitic inductances allows using an odd or even number of half -bridges to be paralleled .
  • Use of wound inductors contrary to interphase transformers yields a reduced s ize when compared to the use of dedicated interphase transformers .
  • the invention scales down to operation with para sitic inductances and thus needs no dedicated magnetic component s .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne un agencement de branche de pont semi-conducteur de puissance (1), comprenant un premier point de connexion (2) et un deuxième point de connexion (3), qui doivent être connectés à une source de tension continue (4), et un point médian (5) en tant que sortie, un agencement de commutation (10) ayant un certain nombre d'éléments de commutation à semi-conducteur (6) connectés entre le premier point de connexion (2) et le deuxième point de connexion (3), et un circuit de commande (7) pour commander le nombre d'éléments de commutation à semi-conducteur (6) de l'agencement de commutation (10). L'invention est caractérisée en ce que l'agencement de commutation (10) comprend au moins deux modules en demi-pont semi-conducteurs de puissance individuels (11, 12, 13) connectés en parallèle entre le premier point de connexion (2) et le deuxième point de connexion (3), chaque module en demi-pont (11, 12, 13) comprenant un commutateur semi-conducteur côté haut (11H, 12H, 13H) et un commutateur semi-conducteur côté bas (11L, 12L, 13L) étant connecté à un point médian en demi-pont (11M, 12M, 13M), le point médian en demi-pont (11M, 12M, 13M) étant connecté au point médian (5) de l'agencement de branche de pont (1) avec une inductance conçue dédiée (L1, L2, L3). En outre, le circuit de commande (7) est conçu pour commander individuellement les opérations de commutation de chaque commutateur à semi-conducteur (11H, 11L, 12H, 12L, 13H, 13L) desdits au moins deux modules en demi-pont à semi-conducteur de puissance individuels (11, 12, 13).
PCT/EP2024/065305 2023-06-12 2024-06-04 Agencement de branche de pont semi-conducteur de puissance Ceased WO2024256214A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202480038888.XA CN121359381A (zh) 2023-06-12 2024-06-04 功率半导体桥臂布置
EP24731535.1A EP4699221A1 (fr) 2023-06-12 2024-06-04 Agencement de branche de pont semi-conducteur de puissance

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP23178736 2023-06-12
EP23178736.7 2023-06-12
EP24155481.5 2024-02-02
EP24155481.5A EP4478614A1 (fr) 2023-06-12 2024-02-02 Agencement de pied de pont semi-conducteur de puissance

Publications (1)

Publication Number Publication Date
WO2024256214A1 true WO2024256214A1 (fr) 2024-12-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2024/065305 Ceased WO2024256214A1 (fr) 2023-06-12 2024-06-04 Agencement de branche de pont semi-conducteur de puissance

Country Status (3)

Country Link
EP (1) EP4699221A1 (fr)
CN (1) CN121359381A (fr)
WO (1) WO2024256214A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180083617A1 (en) * 2015-03-13 2018-03-22 Transphorm Inc. Paralleling of Switching Devices for High Power Circuits
CN112187020A (zh) * 2020-09-27 2021-01-05 申彦峰 开关半导体器件并联电路及其控制方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180083617A1 (en) * 2015-03-13 2018-03-22 Transphorm Inc. Paralleling of Switching Devices for High Power Circuits
CN112187020A (zh) * 2020-09-27 2021-01-05 申彦峰 开关半导体器件并联电路及其控制方法

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
D. REIFF, S. JOHANNLIEMKEV. STAUDT: "2021 International Aegean Conference on Electrical Machines and Power Electronics (ACEMP) & 2021 International Conference on Optimization of Electrical and Electronic Equipment (OPTIM", ACTIVE CURRENT BALANCING FOR PARALLELED SIC SEMICONDUCTORS IN TIME-STAGGERED SWITCHING MODE, September 2021 (2021-09-01), pages 205 - 211
D. REIFFS. JOHANNLIEMKEV. STAUDT: "Active Current Balancing for Paralleled SiC Semiconductors in Time-Staggered Switching Mode", IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, 2023, pages 1 - 10
FUCHSLUEGER, H. ERTLM. A. VOGELSBERGER: "Reducing dv/dt of Motor Inverters by Staggered-Edge Switching of Multiple Parallel SiC Half-Bridge Cells", PCIM EUROPE
REIFF DAVID ET AL: "Active Current Balancing for Paralleled SiC Semiconductors in Time-Staggered Switching Mode", 2021 INTERNATIONAL AEGEAN CONFERENCE ON ELECTRICAL MACHINES AND POWER ELECTRONICS (ACEMP) & 2021 INTERNATIONAL CONFERENCE ON OPTIMIZATION OF ELECTRICAL AND ELECTRONIC EQUIPMENT (OPTIM), IEEE, 2 September 2021 (2021-09-02), pages 205 - 211, XP034012299, DOI: 10.1109/OPTIM-ACEMP50812.2021.9590062 *
SHEN YANFENG ET AL: "Desynchronizing Paralleled GaN HEMTs to Reduce Light-Load Switching Loss", IEEE TRANSACTIONS ON POWER ELECTRONICS, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, USA, vol. 35, no. 9, 29 January 2020 (2020-01-29), pages 9151 - 9170, XP011786620, ISSN: 0885-8993, [retrieved on 20200505], DOI: 10.1109/TPEL.2020.2970240 *

Also Published As

Publication number Publication date
CN121359381A (zh) 2026-01-16
EP4699221A1 (fr) 2026-02-25

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