WO2025190899A1 - Procédé mis en œuvre par ordinateur pour tester un dispositif de commande électronique avec un simulateur et simulateur correspondant - Google Patents

Procédé mis en œuvre par ordinateur pour tester un dispositif de commande électronique avec un simulateur et simulateur correspondant

Info

Publication number
WO2025190899A1
WO2025190899A1 PCT/EP2025/056532 EP2025056532W WO2025190899A1 WO 2025190899 A1 WO2025190899 A1 WO 2025190899A1 EP 2025056532 W EP2025056532 W EP 2025056532W WO 2025190899 A1 WO2025190899 A1 WO 2025190899A1
Authority
WO
WIPO (PCT)
Prior art keywords
simulation
circuit model
simulator
output variables
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/EP2025/056532
Other languages
German (de)
English (en)
Inventor
Axel Kiffe
Thorben Hoffstadt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dspace GmbH
Original Assignee
Dspace GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102024118150.8A external-priority patent/DE102024118150A1/de
Application filed by Dspace GmbH filed Critical Dspace GmbH
Publication of WO2025190899A1 publication Critical patent/WO2025190899A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/23—Pc programming
    • G05B2219/23446—HIL hardware in the loop, simulates equipment to which a control module is fixed
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2604—Test of external equipment

Definitions

  • the invention relates to a computer-implemented method for testing an electronic control unit using a simulator.
  • the simulator with at least one computing unit, numerically simulates a mathematical circuit model of an electrical circuit.
  • the circuit model is calculated in successive simulation steps with a simulation step duration. Each simulation step comprises several chronologically successive sub-simulation steps.
  • the circuit comprises at least one switching element, which switching element can assume either a conductive or a blocking switching state.
  • the current switching state of the switching element of the circuit is determined and the circuit model is adapted to the switching state of the switching element.
  • input variables of the circuit model are acquired, output variables of the circuit model are calculated, and the output variables are transmitted, at least partially, via a simulator interface to the control unit to be tested.
  • the invention further relates to a corresponding simulator for carrying out the method and also to a computer program that carries out the described method when executed on the computing unit of the simulator.
  • HIL hardware-in-the-loop
  • Typical examples are control units for an electric drive or for an onboard charger, for example from the automotive sector, whose environment—in the case of the control unit for the electric drive, the electric drive and, if applicable, other environmental components (e.g., the vehicle chassis)—is simulated with the simulator.
  • the control unit is connected via its control unit interface to the corresponding simulator interface of the simulator so that corresponding signals (power signals from semiconductor bridges, sensor signals) can be transmitted. nals, etc.) can be exchanged as in real-life use of the control unit.
  • the simulator also includes suitable power electronics modules to simulate corresponding electrical loads (motor, generator, batteries) for the control unit.
  • the control unit can exist in various forms: as a development control unit, which still differs from the final hardware implementation, as a final production control unit, or as a virtual control unit, which is a software simulation. In the latter case, the simulator and the control unit are also connected via corresponding I/O interfaces, even if these are only implemented in data terms.
  • the control unit is tested by operating the control unit together with the simulator, as this allows us to determine whether the control unit and the control system implemented on it realize the expected behavior.
  • This not only requires that the mathematical circuit model is calculated numerically as accurately as possible, but in real-time simulations it must also be calculated in real time: The calculation of the system behavior in a time interval of one second of simulation time must therefore be completed in no more than one second of physical real time so that the simulation result is available in the desired real time.
  • the simulation of electrical circuits with high-frequency switching semiconductors, such as in power electronic systems with controlled half-bridges, is extremely demanding because the systems often have large eigenvalues and thus high rates of change in the state variables over time, especially in comparison to mechanical systems.
  • the overall switching state of the circuit i.e., the total switching states of the existing switching elements
  • the calculation of the sub-simulation steps is based on the assumption of unchanging switching states of the switching elements of the electrical circuit within the simulation step.
  • the determination of the overall switching state is not represented in the state-space equations (Equation 1); it is a separate process that is often performed iteratively until stable switching states are achieved for all switching elements of the circuit.
  • the switching elements can be mathematically represented differently in the circuit model, so that various ways of adapting the circuit model to the switching state of the switching elements are known.
  • closed switching elements are ideally conductive connections, and open switching elements are ideal interruptions in the circuit.
  • the switching of a switching element therefore leads to a structural A change in the circuit and each circuit s variant of the circuit (with N circuit elements, there are 2 N circuit s variants) leads to a different state-space representation of the circuit, so that a multitude of different state-space representations must be used.
  • a simulation step comprises several sequential sub-simulation steps.
  • the chronological order of the sub-simulation steps depends, for example, on whether a later sub-simulation step is dependent on the results of an earlier sub-simulation step.
  • the object of the present invention is to improve the simulation of the electrical circuit so that the output variables better reflect the actual behavior of the electrical circuit and, to this extent, by transmitting the output variables via the simulator interface to the control unit to be tested, a test of the control unit that more precisely reflects the actual physical conditions is possible.
  • the object is achieved in the initially described computer-implemented method for testing an electronic control unit with a simulator having the features of the characterising part of independent patent claim 1 and in the initially described simulator by the features of the germinal part of independent patent claim 10.
  • the method according to the invention is characterized in that the simulator simulates at least some of the sub-simulation steps simultaneously, so that within a simulation step duration, several corresponding time-shifted output variables of the circuit model are calculated based on several time-shifted determined input variables of the circuit model, based on several time-shifted calculated circuit states of the circuit elements of the circuit model.
  • the several time-shifted calculated Output variables are averaged to form averaged output variables and the averaged output variables are at least partially transmitted as output variables via the control unit interface to the control unit to be tested.
  • the method according to the invention significantly increases the accuracy of circuit simulation, so that the determined output variables more accurately reflect the actual physical behavior of the circuit, which also allows the control unit under test to be excited more realistically and precisely by the simulator. This results in more reliable test results.
  • the invention is based on the finding that with the known method, in which only strictly consecutive simulation steps are executed without any temporal overlap, it is only possible to react relatively late to changing switching states, since the switching state of switching elements is checked only once per simulation step. Therefore, reacting to changed switching states of the overall circuit is only possible with a relatively significant delay.
  • the sub-simulation steps are not only performed strictly sequentially, but at least partially simultaneously, i.e., with temporal overlap. This makes it possible to react to changed switching states of switching elements in the circuit at a higher repetition rate. Likewise, current output variables are calculated at a higher rate, and by averaging these, changed switching states are also reflected in the output signal more quickly, thus achieving a lower latency in the reaction to changed switching states.
  • the solution is therefore not to simply run the existing circuit model with a shorter simulation step duration, as this is often not possible at all if the simulation step duration is only slightly longer than the required calculation time (often referred to as the turnaround time) to fully calculate the sub-simulation steps within a simulation step. For example, if 10 ps has been selected as the simulation step duration, but the actual calculation time within a simulation step already requires 8 ps, there is no possibility of achieving a higher temporal resolution by reducing the simulation step duration.
  • the hardware configuration of the simulator often offers the possibility of using parallel hardware structures, so that the method according to the invention can be implemented without any problems.
  • a further development of the method is characterized in that the time offset between the simulation steps of the successively executed instances of the circuit model is the same, in particular with n instances of the circuit model the time offset is the simulation step duration divided by n.
  • An alternative development of the method is characterized in that the time offset between the simulation steps of the successively executed instances of the circuit model. This is intended to prevent adverse effects that may be caused by strictly periodic and temporally symmetric calculations. Particularly preferably, the sum of the time offsets is chosen to be smaller than the simulation step duration. In a particularly preferred embodiment of the method, the time offset between the simulation steps of the successively executed instances of the circuit model is varied during a simulation.
  • a moving arithmetic mean is calculated to average the output variables, in particular, the output variables of all instances of the circuit model are used to calculate the mean.
  • the output variables of the last n calculated instances of the circuit model are averaged.
  • the simulator simulates at least some of the sub-simulation steps simultaneously by implementing these sub-simulation steps of the circuit model on separately executable hardware units, and executing the sub-simulation steps multiple times within a simulation step duration using correspondingly current input variables, so that current averaged output variables are calculated multiple times within a simulation step duration.
  • Different sub-simulation steps are thus executed on different hardware units, i.e., a first sub-simulation step on a first hardware unit, a second sub-simulation step on a second hardware unit (different from the first hardware unit), etc., with a specific hardware unit always executing a specific sub-simulation step.
  • this process variant does not involve multiple instances of the circuit model, but rather only one circuit model that executes several sub-simulation steps, sometimes simultaneously, in one simulation step.
  • the separately executable hardware units can, for example, be several consecutive stages of an FPGA implementation.
  • a preferred embodiment of the method provides for the calculation of the sub-simulation steps to be performed consecutively as quickly as possible in order to obtain the greatest possible number of current averaged output variables within a simulation step duration. This minimizes idle time for the independent hardware units and thus maximizes overlap in the calculations of the sub-simulation steps.
  • the simulation step frequency i.e., the inverse of the simulation step duration
  • the simulation step frequency is selected to be greater than the maximum switching frequency of a switching element in the electrical circuit. This ensures that a change in the switching state of a switching element is actually taken into account in the simulation. Otherwise, it would be possible for the change in a switching state to go unnoticed.
  • the invention also relates to a simulator with a computing unit for the numerical simulation of an electrical circuit with a mathematical circuit model, wherein during operation of the simulator the calculation of the circuit model takes place in successive simulation steps with a simulation step duration, wherein a simulation step comprises several temporally successive sub-simulation steps, wherein the circuit comprises at least one switching element, which switching element can assume either a conductive or a blocking switching state, wherein within a simulation step the current switching state of the switching element of the circuit is detected and the circuit model is adapted to the switching state of the switching element, wherein within a simulation step input variables of the circuit model are detected, output variables of the circuit model are determined, and wherein the simulator has a simulator interface for connecting the device to be tested- the control unit, wherein the simulator, when in operation with a connected control unit to be tested, transmits the output variables at least partially via the simulator interface to the control unit to be tested.
  • the computing unit of the simulator can be a processor-based computing unit with an instruction-oriented programmable arithmetic unit (also multiprocessor and multi-core implementations), but it can also be a programmable gate arrangement, such as a Field Programmable Gate Array (FPGA).
  • FPGA Field Programmable Gate Array
  • the invention further relates to a computer program comprising instructions which, when the program is executed by a computing unit of a simulator, cause the simulator to carry out the method described above.
  • the computer program may be an executable machine code for a processor, insofar as the computing unit is based on the use of processors and/or the computer program may be a hardware description for programmable logic gates, in particular a hardware description for a field programmable gate array (FPGA), insofar as the computing unit is based on the use of programmable logic gates.
  • FPGA field programmable gate array
  • Fig. 1 schematically shows a computer-implemented method for testing an electronic control unit with a simulator and a corresponding simulator
  • Fig. 2 shows schematically an electrical circuit with switching elements
  • Fig. 3 schematically shows a method for calculating a mathematical circuit model of an electrical circuit with successive simulation steps and sub-simulation steps
  • Fig. 5 schematically shows a method according to the invention for the numerical simulation of a mathematical circuit model using the temporally overlapping calculation of several sub-simulation steps of a single circuit model
  • Figs. 1 to 6 schematically show various aspects of a computer-implemented method 1 for testing an electronic control unit 2 with a simulator 3 and a simulator 3.
  • Fig. 1 shows the simulator 3, which is equipped with a computing unit 4 (not shown in detail) based on a programmable gate arrangement in the form of a Field Programmable Gate Array (FPGA).
  • the computer program 10 which is not shown in detail, is a corresponding hardware description for the Field Programmable Gate Array so that it carries out the method 1.
  • the simulator 3 numerically simulates a mathematical circuit model 5 of an electrical circuit 6.
  • the circuit to be tested is
  • the control unit 2 is a production control unit for controlling an electric drive.
  • the electric drive is not real, but is simulated by the simulator 3.
  • the simulator 3 also includes power electronic load simulations, which are controlled during the simulation to simulate a real drive with its electrical connection parameters and dynamic behavior to the control unit 2 as realistically as possible.
  • the setup is a so-called hardware-in-the-loop (HIL) simulation, in which the physical environment of the control unit 2 under test is simulated in real time.
  • HIL hardware-in-the-loop
  • Fig. 2 shows an electrical circuit 6 using the example of a buck converter.
  • the circuit has two switching elements 7, namely an active semiconductor switching element Q1, whose switching state can be influenced by an active control signal g, and a diode Q2, which is a passive switching element 7 whose switching state (conductive, non-conductive) is determined by internal switching conditions (current and connection voltage).
  • the switching elements 7 comprised by the circuit 6 can assume either a conductive or a non-conductive switching state.
  • the circuit 6 is converted into the mathematical circuit model 5 by setting up time-discrete state equations, which forms the basis of the numerical simulation.
  • a simulation step k comprises several temporally successive sub-simulation steps a, b, c, wherein within a simulation step k input variables u, g of the circuit model 5 are recorded, output variables yk, yk+i, yk+2 of the circuit model 5 are calculated, and the output variables yk, yk+i, yk+2 (y is to be understood here as a vector quantity with several vector elements) are at least partially determined via a simulator interface 8 to the control unit 2 to be tested via its control unit interface 9 (Fig. 1).
  • Fig. 3 may be that the result of sub-simulation step a is the input variable of sub-simulation step b, etc., and/or that the computing unit 4 only allows the sub-simulation steps to be executed serially.
  • Fig. 3 also illustrates the course of a real, active switching signal g of a switching element 7, wherein the switching signal g changes from blocking to conducting in the middle of simulation step k-1 and changes again from conducting to blocking in the middle of simulation step k+1.
  • the real switching states g of the switching elements 7 are only determined once per simulation step k. This means that the determined switching state gi only changes from blocking to conducting at the beginning of simulation step k and the determined switching state gi only changes from conducting to blocking in simulation step k+2.
  • the plurality of output variables y n -i, y n , y n +i calculated with a time delay are at least partially averaged with a moving average to form averaged output variables y' n -i, y' n , y'n+i.
  • Fig. 4 shows a first variant of the method 1 generally described above.
  • This variant is characterized in that the simulator 3 simulates at least some of the sub-simulation steps a, b, c simultaneously by simulating several independent instances I, II, III of the mathematical circuit model 5 with corresponding independent instances of the sub-simulation steps a, b, c simultaneously.
  • all sub-simulation steps a, b, c are executed simultaneously at any given time, with the simultaneously executed sub-simulation steps a, b, c belonging to different instances I, II, III of the circuit model 5.
  • the calculations of instances I, II, III of the circuit model 5 are each carried out in simulation steps i, j, k, which simulation steps i, j, k are carried out with a time delay of a fraction of the simulation step duration T.
  • the corresponding start times of the simulation steps i, j, k are denoted by ti, tj, tk.
  • the computing unit 4 of the simulator 3 therefore does not have to calculate a single circuit model 5 faster than was the case in the prior art according to Fig. 3, but the computing unit 4 must have the capacity to calculate the further instances of the circuit model in parallel. calculate, for example by using additional cores of a processor-based computing unit or by parallel implementation of instances I, II, III on an FPGA using additional gates of the FPGA.
  • the averaged output variables y respond more precisely to changed switching states of switching elements 7. Since the averaged output variables y are output as the output variables y to the control unit 2 under test, the simulation is closer to the actual behavior of the simulated circuit 6 in reproducing the timing behavior than was previously possible.
  • the method 1 in Fig. 4 is implemented in such a way that the time offset between the simulation steps i, j, k of the successively executed instances I,
  • the time offset is the simulation step duration T divided by three, i.e. T/3.
  • a moving arithmetic mean is calculated to average the output variables y, y, yk, etc., wherein the output variables y n -i, y n , y n +i of all instances of the circuit model 5 are used to calculate the mean.
  • the output variables y n -i, y n , y n +i of the last N calculated instances of the circuit model 5 are averaged.
  • Equation 2 applies, wherein the output variables y(t) of the instances of the Circuit model 5 is an output variable vector that includes the individual output variables:
  • Fig. 5 shows a second variant of the implementation of method 1.
  • simulator 3 simulates at least some of the sub-simulation steps a, b, c simultaneously by implementing these sub-simulation steps a, b, c of circuit model 5 on separately executable hardware units 4 and executing sub-simulation steps a, b, c multiple times within a simulation step duration T with correspondingly current input variables u, g, so that current averaged output variables y are calculated multiple times within a simulation step duration T.
  • multiple instances of circuit model 5 are not required; rather, a single circuit model (designated I in Fig.
  • Fig. 5 shows the simulation steps i, j, k, and the execution of the sub-simulation steps a, b, c, offset three times in time.
  • the computing unit responsible for calculating sub-simulation step a is practically never idle.
  • Fig. 6 shows the simulation of the buck converter according to Fig. 2 and the temporal characteristics of some electrical variables of the buck converter, namely the capacitor voltage vc, the input current ii n , and the coil current . Furthermore, the input current and the coil current are shown in temporal detail.
  • the curve designated as "reference” shows the actual, error-free curve of the corresponding variables; the dotted curve “EinzehnodeH” shows the simulation result with only a single model, i.e., without overlapping calculation of sub-simulation steps. A significant deviation can be observed between the curves, so that the test of control unit 2 based on the simulation does not correspond well to the actual physical conditions. A significant improvement is achieved with methods 1 according to Figs.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

L'invention concerne un procédé mis en œuvre par ordinateur (1) pour tester un dispositif de commande électronique (2) avec un simulateur (3), le simulateur (3) simulant numériquement un modèle de circuit mathématique (5) d'un circuit électrique (6) en utilisant au moins une unité de calcul (4), le modèle de circuit (5) étant calculé au cours d'étapes de simulation successives (k) avec une durée d'étape de simulation (T), une étape de simulation (k) comprenant une pluralité de sous-étapes de simulation chronologiquement successives (a, b, c), le circuit (6) comprenant au moins un élément de commutation (7), ledit élément de commutation (7) pouvant être dans une état de commutation de conduction ou dans un état de commutation de blocage, dans une étape de simulation (k), l'état de commutation de courant de l'élément de commutation (7) du circuit (6) étant déterminé et le modèle de circuit (5) étant adapté à l'état de commutation de l'élément de commutation (7), des variables d'entrée (u, g) du modèle de circuit (5) étant détectées dans une étape de simulation (k), des variables de sortie (y) du modèle de circuit (5) étant calculées, et les variables de sortie (y) étant transmises au moins partiellement au dispositif de commande (2) à tester par l'intermédiaire d'une interface de simulateur (8). Le test du dispositif de commande (2) qui correspond mieux aux conditions physiques réelles est effectué en simulant simultanément au moins certaines des sous-étapes de simulation (a, b, c) et des variables de sortie correspondantes (yn-1, yn, yn+1) du modèle de circuit (5) étant calculées et moyennées pour produire des variables de sortie moyennées (y- n-1, y- n, y- n+1) et transmises comme variables de sortie (yn-1, yn, yn+1) au dispositif de commande (2) à tester par l'intermédiaire de l'interface de dispositif de commande (8).
PCT/EP2025/056532 2024-03-12 2025-03-11 Procédé mis en œuvre par ordinateur pour tester un dispositif de commande électronique avec un simulateur et simulateur correspondant Pending WO2025190899A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102024106977 2024-03-12
DE102024106977.5 2024-03-12
DE102024118150.8A DE102024118150A1 (de) 2024-03-12 2024-06-27 Computerimplementiertes Verfahren zum Test eines elektronischen Steuergerätes mit einem Simulator und entsprechender Simulator
DE102024118150.8 2024-06-27

Publications (1)

Publication Number Publication Date
WO2025190899A1 true WO2025190899A1 (fr) 2025-09-18

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PCT/EP2025/056532 Pending WO2025190899A1 (fr) 2024-03-12 2025-03-11 Procédé mis en œuvre par ordinateur pour tester un dispositif de commande électronique avec un simulateur et simulateur correspondant

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015108064A1 (de) * 2015-05-21 2016-11-24 in-tech GmbH Testsystem und Verfahren zum automatisierten Testen von wenigstens zwei gleichzeitig an das Testsystem angeschlossenen Steuergeräten sowie Steuergeräte-Anschluss- und Steuergeräte-Umschalteinheit zur Verwendung in einem solchen Testsystem
EP3418924A1 (fr) 2017-06-20 2018-12-26 dSPACE digital signal processing and control engineering GmbH Procédé mise en uvre sur ordinateur destiné à simuler un circuit global électrique
DE102018110020A1 (de) * 2017-09-01 2019-03-07 Dspace Digital Signal Processing And Control Engineering Gmbh Verfahren zum Erzeugen eines auf einem Testgerät ausführbaren Modells eines technischen Systems und Testgerät

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015108064A1 (de) * 2015-05-21 2016-11-24 in-tech GmbH Testsystem und Verfahren zum automatisierten Testen von wenigstens zwei gleichzeitig an das Testsystem angeschlossenen Steuergeräten sowie Steuergeräte-Anschluss- und Steuergeräte-Umschalteinheit zur Verwendung in einem solchen Testsystem
EP3418924A1 (fr) 2017-06-20 2018-12-26 dSPACE digital signal processing and control engineering GmbH Procédé mise en uvre sur ordinateur destiné à simuler un circuit global électrique
DE102018110020A1 (de) * 2017-09-01 2019-03-07 Dspace Digital Signal Processing And Control Engineering Gmbh Verfahren zum Erzeugen eines auf einem Testgerät ausführbaren Modells eines technischen Systems und Testgerät

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