WO2025200802A1 - Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage - Google Patents

Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage

Info

Publication number
WO2025200802A1
WO2025200802A1 PCT/CN2025/076709 CN2025076709W WO2025200802A1 WO 2025200802 A1 WO2025200802 A1 WO 2025200802A1 CN 2025076709 W CN2025076709 W CN 2025076709W WO 2025200802 A1 WO2025200802 A1 WO 2025200802A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
light
signal terminal
emitting
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/076709
Other languages
English (en)
Chinese (zh)
Other versions
WO2025200802A9 (fr
Inventor
杜丽丽
陈家兴
尚庭华
安一
杨中流
牛佐吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025200802A1 publication Critical patent/WO2025200802A1/fr
Publication of WO2025200802A9 publication Critical patent/WO2025200802A9/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • OLED organic light-emitting diode
  • the first light-emitting subcircuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal, and the second node.
  • the first light-emitting subcircuit is configured to control the conduction and cutoff of the first voltage signal terminal and the second node in response to a first light-emitting signal received at the first light-emitting signal terminal.
  • the second light-emitting subcircuit is coupled to the third node, the second light-emitting signal terminal, and an anode of a light-emitting device.
  • the second light-emitting subcircuit is configured to control the conduction and cutoff of the third node and the anode of the light-emitting device in response to a second light-emitting signal received at the second light-emitting signal terminal.
  • the first reset sub-circuit is coupled to a reset signal terminal, the first node, and the first initialization signal terminal; the first reset sub-circuit is configured to control the first initialization signal terminal and the first node to be conductive and cutoff in response to a reset signal received at the reset signal terminal.
  • the compensation sub-circuit is coupled to the first node, the third node, and a first scan signal terminal; the compensation sub-circuit is configured to control the first node and the third node to be conductive and cutoff in response to a first scan signal received at the first scan signal terminal.
  • the first storage sub-circuit is coupled to the first voltage signal terminal and the second node; the first storage sub-circuit is configured to store the potential of the second node.
  • the moment when the first voltage signal terminal and the second node start to conduct is earlier than the moment when the third node and the anode of the light-emitting device start to conduct; the moment when the first voltage signal terminal and the second node start to turn off is earlier than the moment when the third node and the anode of the light-emitting device start to turn off.
  • the first storage sub-circuit includes a first storage capacitor, a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the second node.
  • the pixel circuit further includes a second reset subcircuit and a data write subcircuit.
  • the second reset subcircuit is coupled to a second initialization signal terminal, the anode of the light-emitting device, and a second scan signal terminal; the second reset subcircuit is configured to control the conduction and cutoff of the anode of the light-emitting device and the second initialization signal terminal in response to a second scan signal received at the second scan signal terminal;
  • the data write subcircuit is coupled to the second node, the third scan signal terminal, and the data signal terminal; the data write subcircuit is configured to control the conduction and cutoff of the data signal terminal and the second node in response to a third scan signal received at the third scan signal terminal.
  • the second scanning signal terminal and the third scanning signal terminal receive the same signal.
  • the first light-emitting sub-circuit includes a second transistor
  • the second light-emitting sub-circuit includes a third transistor
  • the first electrode of the second transistor is coupled to the first plate of the first storage capacitor
  • the second electrode is coupled to the second plate of the first storage capacitor
  • the control electrode is coupled to the first light-emitting signal terminal
  • the first electrode of the third transistor is coupled to the third node
  • the second electrode is coupled to the anode of the light-emitting device
  • the control electrode is coupled to the second light-emitting signal terminal EM2.
  • the reset phase includes a first reset phase and a second reset phase; in the first reset phase, the second light-emitting sub-circuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal; the first reset sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal; in the second reset phase, the compensation sub-circuit transmits the potential at the first node to the third node in response to the first scan signal received at the first scan signal terminal; the second light-emitting sub-circuit transmits the potential at the third node to the anode of the light-emitting device in response to the second light-emitting signal received at the second light-emitting signal terminal.
  • the pixel circuit further includes a second reset subcircuit and a write subcircuit; after the reset stage, a display frame cycle further includes a data write compensation stage; in the data write compensation stage, the data write subcircuit transmits the data signal received at the data signal terminal to the second node in response to the second scan number received at the second scan signal terminal; the compensation subcircuit transmits the potential at the second node to the first node in response to the first scan signal received at the first scan signal terminal; the second reset subcircuit transmits the second initialization signal received at the second initialization signal terminal to the anode of the light-emitting device in response to the second scan number received at the second scan signal terminal.
  • a display panel in another aspect, includes a plurality of pixel circuits, each of which includes a second transistor; the second transistor is coupled to a first voltage signal terminal.
  • the display panel includes a substrate, a semiconductor layer, a first conductive layer, and a second conductive layer.
  • the semiconductor layer is disposed on the substrate and includes a second active portion of the second transistor, the second active portion including a second source region, a second drain region, and a second channel region, the second channel region being disposed between the second source region and the second drain region.
  • the first conductive layer is disposed on a side of the semiconductor layer away from the substrate and includes a plurality of first conductive blocks; the orthographic projections of the first conductive blocks on the substrate overlap with the orthographic projections of one of the second source region and the second drain region on the substrate, and the overlapping portion forms a first storage capacitor; the first conductive blocks are connected to the other of the second source region and the second drain region.
  • the second conductive layer is disposed on a side of the first conductive layer away from the substrate and includes a first power signal line, which is connected to the first conductive block and coupled to the first voltage signal terminal.
  • the pixel circuit further includes a first transistor
  • the semiconductor layer further includes a first active portion of the first transistor
  • the first active portion includes a first source region, a first drain region, and a first channel region, the first channel region being disposed between the first source region and the first drain region.
  • the display panel further includes a third conductive layer, the third conductive layer being disposed between the semiconductor layer and the first conductive layer and including a second conductive block, the orthographic projection of the second conductive block on the substrate overlapping the orthographic projection of the first channel region on the substrate.
  • the second conductive layer further includes a third conductive block, the orthographic projection of the third conductive block on the substrate overlapping the orthographic projection of the second conductive block on the substrate, and the overlapping portion of the third conductive block and the second conductive block forming a second storage capacitor.
  • the third conductive layer further includes a fourth conductive block and a fifth conductive block; the orthographic projection of the fourth conductive block on the substrate overlaps with the orthographic projection of the second channel region on the substrate, and the orthographic projection of the fifth conductive block on the substrate overlaps with the orthographic projection of the third channel region on the substrate; the orthographic projection of the fourth conductive block on the substrate and the orthographic projection of the fifth conductive block on the substrate are staggered.
  • the display panel further comprises a fourth conductive layer; the fourth conductive layer is disposed on a side of the first conductive layer away from the third conductive layer, and the fourth conductive layer further comprises a second light-emitting signal line.
  • the second light-emitting signal line is coupled to the second light-emitting signal terminal; the second light-emitting signal line comprises a first straight portion and a second straight portion connected to each other; the first straight portion extends along the first direction, the second straight portion extends along the second direction, and an orthographic projection of the second straight portion on the substrate overlaps with an orthographic projection of the fifth conductive block on the substrate and is connected to the fifth conductive block.
  • a second straight line portion is provided between any two adjacent active layer pattern groups, and the first channel region includes a second straight line segment and a second bending segment; the second straight line segment extends along the first direction, and the second bending segment bends toward one side of the second straight line segment along the second direction.
  • the display device 1000 may be a portable display product, such as the mobile phone shown in FIG1 .
  • a display device 1000 includes a display panel 100 , a driving circuit board 200 , a housing 300 , and a cover plate 400 .
  • the driving circuit board 200 is disposed on the non-luminous side of the display panel 100 and is connected to the display panel 100 to provide a luminous signal to the display panel 100 .
  • the housing 300 may be a box-shaped structure with an opening.
  • the display panel 100 and the driver circuit board 200 may be disposed in the housing 300 .
  • the cover plate 400 is disposed on the light-emitting side of the display panel 100 and located at the opening of the housing 300 .
  • the display panel 100 can be: an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel or a micro light-emitting diode (MLED) display panel, etc., and the embodiments of the present disclosure do not make specific limitations here.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • AMOLED active matrix organic light-emitting diode
  • LCD liquid crystal display
  • MLED micro light-emitting diode
  • the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20 .
  • a plurality of sub-pixels 20 are disposed on a substrate 10.
  • the plurality of sub-pixels 20 may be arranged, for example, in multiple rows and columns.
  • Each row of sub-pixels 20 includes at least two sub-pixels 20 arranged along a first direction X
  • each column of sub-pixels 20 includes at least two sub-pixels 20 arranged along a second direction Y.
  • the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.
  • the plurality of sub-pixels 20 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color.
  • the first, second, and third colors are three primary colors. For example, the first color is red, the second color is blue, and the third color is green. This is not specifically limited in the present embodiment.
  • each sub-pixel 20 includes a pixel circuit 21 and a light-emitting device 22 disposed on a substrate 10.
  • the pixel circuit 21 includes a plurality of transistors 211 and a storage capacitor 212 (Capacitor, C for short).
  • the transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the embodiments of the present disclosure are described using thin film transistors as an example.
  • the transistor 211 is, for example, an oxide thin film transistor.
  • the oxide thin film transistor has a high carrier mobility, which can improve the response speed of the transistor 211 .
  • the transistor 211 includes an active portion 2111, a source 2112, a drain 2113, and a gate 2114.
  • the source 2112 and the drain 2113 are respectively in contact with the active portion 2111.
  • the storage capacitor 212 includes two plates disposed opposite to each other.
  • source 2112 and the drain 2113 can be interchanged, that is, 2112 in FIG. 5 represents the drain, and 2113 represents the source.
  • the pixel circuit 21 may have various structures, which can be selected based on actual needs.
  • the pixel circuit 21 may have a structure such as "2T1C,” “3T1C,” “6T1C,” “7T1C,” “6T2C,” or “7T2C.”
  • T represents the transistor 211
  • the number preceding "T” represents the number of transistors 211.
  • C represents the storage capacitor 212
  • the number preceding "C” represents the number of storage capacitors 212.
  • the light-emitting device 22 includes a first electrode 221, a light-emitting functional layer 222, and a second electrode 223.
  • the first electrode 221 can be electrically connected to, for example, a source electrode 2112 or a drain electrode 2113 of a driving transistor in a plurality of transistors 211.
  • FIG5 illustrates the electrical connection between the first electrode 221 and the drain electrode 2113 of the transistor 211.
  • the material of the first electrode 221 includes indium tin oxide (ITO) or silver (Ag).
  • the material of the second electrode includes aluminum (Al), Ag, or magnesium (Mg).
  • the first electrode 221 is the anode of the light-emitting device 22, and the second electrode 223 is the cathode of the light-emitting device 22; alternatively, the first electrode 221 is the cathode of the light-emitting device 22, and the second electrode 223 is the anode of the light-emitting device 22.
  • the following uses the example of the first electrode 221 being the anode of the light-emitting device 22 and the second electrode 223 being the cathode of the light-emitting device 22 as an example to illustrate the embodiments of the present disclosure.
  • the second electrode 223 (cathode) is a whole-layer structure.
  • the above-mentioned light-emitting functional layer 222 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transport layer (English: Election Transporting Layer, abbreviated as: ETL), an electron injection layer (English: Election Injection Layer, abbreviated as: EIL), a hole transport layer (English: Hole Transporting Layer, abbreviated as: HTL) and a hole injection layer (English: Hole Injection Layer, abbreviated as: HIL).
  • ETL Election Transporting Layer
  • EIL electron injection layer
  • HTL Hole Transporting Layer
  • HIL Hole Injection Layer
  • the encapsulation layer 30 may include a single encapsulation film, or may include two or more stacked encapsulation films.
  • the encapsulation layer 30 includes a first inorganic encapsulation layer 31, a first organic encapsulation layer 32, and a second inorganic encapsulation layer 33 stacked in a direction perpendicular to and away from the substrate 10.
  • the materials of the first inorganic encapsulation layer 31 and the second inorganic encapsulation layer 33 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide.
  • the material of the first organic encapsulation layer 32 includes a polymer resin, such as polyimide.
  • the brightness of the display panel is uneven, resulting in poor display effect of the display panel.
  • the driving subcircuit 201 includes a first transistor (driving transistor) T1 , wherein the first electrode of the first transistor T1 is coupled to the second node N2 , the second electrode is coupled to the third node N3 , and the control electrode (gate) is coupled to the first node N1 .
  • the second light-emitting sub-circuit 203 is coupled to the third node N3, the second light-emitting signal terminal EM2 and the anode of the light-emitting device 22; the second light-emitting sub-circuit 203 is configured to control the conduction and cutoff of the third node N3 and the anode of the light-emitting device 22 in response to the second light-emitting signal received at the second light-emitting signal terminal EM2.
  • the second light-emitting sub-circuit 203 includes a third transistor T3 , a first electrode of the third transistor T3 coupled to the third node N3 , a second electrode coupled to the anode of the light-emitting device 22 , and a control electrode coupled to the second light-emitting signal terminal EM2 .
  • the first reset sub-circuit 204 is coupled to the reset signal terminal RESET, the first node N1, and the first initialization signal terminal VINIT1.
  • the first reset sub-circuit 204 is configured to control the conduction and cutoff of the first initialization signal terminal VINIT1 and the first node N1 in response to the reset signal received at the reset signal terminal RESET.
  • the first reset subcircuit 204 includes a fourth transistor T4 , a first electrode of the fourth transistor T4 coupled to the first initialization signal terminal VINIT1 , a second electrode coupled to the first node N1 , and a control electrode coupled to the reset signal terminal RESET.
  • the first reset sub-circuit 204 includes two fourth transistors T4 connected in series, and the two fourth transistors T4 form a dual-gate transistor to reduce leakage current, but the embodiments of the present disclosure are not limited to this, and it can also be considered that the first reset sub-circuit 204 includes three, four or more fourth transistors T4 connected in series, as long as the same technical concept is applied.
  • the compensation sub-circuit 205 includes a fifth transistor T5 , a first electrode of the fifth transistor T5 coupled to the third node N3 , a second electrode coupled to the first node N1 , and a control electrode coupled to the first scan signal terminal GATE1 .
  • transistors are described using P-type transistors as an example. It should be noted that the embodiments of the present disclosure include but are not limited to this. For example, one or more transistors in the circuits provided in the embodiments of the present disclosure may also be N-type transistors. It is only necessary to connect the respective poles of the selected type of transistor accordingly with reference to the respective poles of the corresponding transistors in the embodiments of the present disclosure, and to provide corresponding high or low potentials at the corresponding potential terminals.
  • the pixel circuit 21 also includes a second reset sub-circuit 207, which is coupled to the second initialization signal terminal VINIT2, the anode of the light-emitting device 22 and the second scan signal terminal GATE2; the second reset sub-circuit 207 is configured to control the conduction and cutoff of the anode of the light-emitting device 22 and the second initialization signal terminal VINIT2 in response to the second scan signal received at the second scan signal terminal GATE2.
  • the second initialization signal received by the second initialization signal terminal VINIT2 can be transmitted to the anode of the light-emitting device 22 through the second reset sub-circuit 207, thereby initializing the anode of the light-emitting device 22, and improving the problem that the potential remaining in the anode of the light-emitting device 22 in the previous image frame affects the displayed image of the next image frame, thereby improving the brightness uniformity of the display panel 100.
  • the data writing sub-circuit 208 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 is connected to the data signal terminal DATA, a second electrode is coupled to the second node N2 , and a control electrode is coupled to the third scan signal terminal GATE3 .
  • the following uses the example of the second scan signal terminal GATE2 and the third scan signal terminal GATE3 receiving the same signal as an example to schematically illustrate some embodiments of the present disclosure.
  • the implementation of the present disclosure is not limited to this, and it can also be considered that the second scan signal terminal GATE2 and the third scan signal terminal GATE3 receive different signals, as long as the same technical concept is applied.
  • the pixel circuit 21 further includes a second storage subcircuit 209 , which is coupled to the first voltage signal terminal VDD and the first node N1 ; the first storage subcircuit 206 is configured to store the potential of the first node N1 .
  • the second storage sub-circuit 209 includes a second storage capacitor C2 , a first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and a second plate is connected to the first node N1 .
  • a display frame period includes a reset phase P1, a data write compensation phase P2, and a light-emitting phase P3.
  • the first reset sub-circuit 204 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the first node N1. That is, the potential of the first node N1 is Vin1.
  • the compensation sub-circuit 205 transmits the potential at the first node N1 to the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1. In this way, the first initialization signal can be transmitted from the first node N1 to the third node N3 to reset the third node N3, that is, the potential of the third node N3 is Vin1.
  • the second light-emitting sub-circuit 203 transmits the potential at the third node N3 to the anode of the light-emitting device 22.
  • the first initialization signal can be transmitted from the third node N3 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22. That is, the potential of the anode of the light-emitting device 22 is Vin1.
  • the difference between the potential Vin1 of the anode of the light-emitting device 22 and the potential Vss of the cathode of the light-emitting device 22 is Vin1-Vss, and is less than the threshold voltage of the light-emitting device 22. In this way, the risk of the light-emitting device 22 emitting light during the reset phase P1 can be reduced.
  • the first storage sub-circuit 206 stores the potential of the second node N2 after the previous frame ends.
  • the potential of the second node N2 can maintain a relatively stable potential corresponding to the first voltage signal terminal VDD, that is, the potential of the second node N2 is Vdd.
  • the reset signal terminal RESET, the second light-emitting signal terminal EM2 and the input low level, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned on, the first scan signal terminal GATE1, the second light-emitting signal terminal EM2 and the second scan signal terminal GATE2 are input high level, and the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are all turned off.
  • each subcircuit in the pixel circuit 21 includes a transistor 211 or a storage capacitor 212.
  • the first light emitting signal is 0, the second light emitting signal is 0, the reset signal is 1, the first scanning signal is 1, and the second scanning signal is 1.
  • the magnitude of the current Ioled input to the light-emitting device 22 is related to the potential Vdata of the written data signal and the first voltage signal, and is not related to the threshold voltage Vth of the first transistor T1. This avoids the problem that the difference in the threshold voltage of the first transistor T1 of each pixel circuit 21 caused by the manufacturing process affects the magnitude of the driving current, thereby affecting the display effect.
  • a display frame period further includes a pre-light emitting phase P4 .
  • the display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first power signal lines VDL, a plurality of first initialization signal lines VL1 and a plurality of second initialization signal lines VL2.
  • the pixel circuit 21 provided in some embodiments of the present disclosure is exemplarily described below in conjunction with the film layer of the display panel 100 .
  • the semiconductor layer 101 is disposed on the substrate 10. As shown in Figures 16A and 16B, the semiconductor layer 101 includes a plurality of active layer patterns 1011. Each active layer pattern 1011 includes an active portion of each transistor 211 in each pixel circuit 21. As shown in Figures 16A and 16B, the active layer pattern 1011 includes a first active portion t1 of a first transistor T1, a first active portion t2 of a second transistor T2, a third active portion t3 of a third transistor T3, a fourth active portion t4 of a fourth transistor T4, a fifth active portion t5 of a fifth transistor T5, a sixth active portion t6 of a sixth transistor T6, and a seventh active portion of a seventh transistor T7.
  • each transistor includes a source region, a drain region, and a channel region, with the channel region being located between the source and drain regions.
  • the first channel region t13 is located between the first source region t11 and the first drain region t12
  • the second channel region t23 is located between the second source region t21 and the second drain region t22
  • the third channel region t33 is located between the third source region t31 and the third drain region t32
  • the fourth channel region t43 is located between the fourth source region t41 and the fourth drain region t42
  • the fifth channel region t53 is located between the fifth source region t51 and the fifth drain region t52
  • the sixth channel region t63 is located between the sixth source region t61 and the sixth drain region t62
  • the seventh channel region t73 is located between the seventh source region t71 and the seventh drain region t72.
  • the active portion of each transistor 211 included in the active layer pattern 1011 is integrally arranged.
  • the semiconductor layer 101 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and drain region can be regions doped with n-type impurities or p-type impurities.
  • the semiconductor layer 101 can be prepared, for example, by depositing a semiconductor material on the surface of the substrate 10 and performing an etching process to form the semiconductor layer 101, so that the semiconductor layer 101 has an active layer pattern 1011.
  • the first conductive block 1021 is connected to the other of the second source region t21 and the second drain region t22 , thereby coupling the first storage capacitor C1 and the second transistor T2 .
  • the first conductive block 1021 is connected to the second drain region t22, and the orthographic projection of the first conductive block 1021 on the substrate overlaps with the orthographic projection of the second source region t21 on the substrate 10.
  • the shape of the orthographic projection of the first conductive block 1021 on the substrate 10 is substantially equal to the orthographic projection of the second drain region t22 on the substrate 10.
  • the display panel 100 further includes a third conductive layer 104.
  • the third conductive layer 104 is a first gate conductive layer.
  • the third conductive layer 104 is disposed between the semiconductor layer 101 and the first conductive layer 102.
  • the third conductive layer 104 includes a second conductive block 1041.
  • the orthographic projection of the second conductive block 1041 on the substrate 10 overlaps with the orthographic projection of the first channel region t13 on the substrate 10. That is, the portion of the second conductive block 1041 that overlaps with the first channel region t13 forms the gate of the first transistor T1.
  • the orthographic projection of the fourth conductive block 1042 on the substrate 10 overlaps with the orthographic projection of the second channel region t23 on the substrate 10. That is, the portion of the fourth conductive block 1042 overlapping with the second channel region t23 forms the gate of the second transistor T2.
  • the orthographic projection of the fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of the third channel region t33 on the substrate 10. That is, the portion of the fifth conductive block 1043 overlapping with the third channel region t33 forms the gate of the third transistor T3.
  • the orthographic projection of the fourth conductive block 1042 on the substrate 10 and the orthographic projection of the fifth conductive block 1043 on the substrate 10 are staggered.
  • the reset signal line RL is configured to be coupled to the reset signal terminal, the orthographic projection of the reset signal line RL on the substrate 10 overlaps with the orthographic projection of the fourth channel region t43 on the substrate 10, and the portion of the reset signal line RL overlapping with the fourth channel region t43 forms the gate of the fourth transistor T4.
  • the display panel 100 further includes a fourth conductive layer 105.
  • the fourth conductive layer 105 is a first source-drain conductive layer.
  • the fourth conductive layer 105 is disposed on a side of the first conductive layer 102 away from the third conductive layer 104.
  • the fourth conductive layer 105 includes a first light-emitting signal line EL1 and a second light-emitting signal line EL2.
  • the first light-emitting signal line EL1 is configured to be coupled to the first light-emitting signal terminal EM1
  • the second light-emitting signal line EL2 is configured to be coupled to the second light-emitting signal terminal EM2.
  • the first light-emitting signal line EL1 includes alternating first straight segments EL11 and first curved segments EL12.
  • the first straight segment EL11 extends along a first direction X, while the first curved segment EL12 bends toward one side of the first straight segment EL11 along a second direction Y.
  • the orthographic projection of the first curved segment EL11 on the substrate 10 overlaps with the orthographic projection of the fourth conductive block 1042 on the substrate 10 and is connected to the fourth conductive block 1042. This arrangement couples the second transistor T2 to the first light-emitting signal terminal EM1.
  • the first straight line segment EL11 is disposed between the third conductive block 1022 and the fourth conductive block 1042 , and the first bending segment EL12 bends toward the side of the third conductive block 1022 close to the fourth conductive block 1042 .
  • the active layer patterns 1011 are arranged in multiple rows and columns. Each row of active layer patterns 1011 includes at least two active layer patterns 1011 spaced apart along the first direction X. The interval between any two adjacent active layer patterns 1011 along the first direction X is substantially equal.
  • the orthographic projection of one fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of one third channel region t33 on the substrate 10.
  • multiple second straight line portions EL22 are arranged at intervals along the first direction X.
  • a second straight line portion EL22 is provided between any two adjacent active layer patterns 1011.
  • the number of second straight line portions EL22 is large, and the area occupied is large, resulting in a shorter channel region extending along the first direction X in the active layer pattern 1011, which in turn reduces the performance (e.g., carrier mobility) of the transistor including the channel region.
  • the first channel region in the active layer pattern 1011 extends along the first direction X.
  • a plurality of first power signal lines VDL and data lines DL are arranged along a first direction X and overlap each other.
  • the second straight line portions EL22 are arranged at intervals along the first direction X.
  • a second straight line portion EL22 is provided between any two adjacent active layer pattern groups. In this manner, the number of second straight line portions EL22 is small, and the area they occupy is small, thereby ensuring that the length of the channel region extending along the first direction X in the active layer pattern 1011 is appropriate, thereby improving the performance of the transistor including this channel region.
  • the sixth block 40 is coupled to one of the second source region and the second drain region in the first active layer pattern 1111 through a via hole, and is coupled to the second drain region t22 through a via hole.
  • the first conductive block 1021 overlapping the first active layer pattern 1111 is directly connected to the first conductive block 1021 overlapping the second active layer pattern 1112 belonging to the same group as the first active layer pattern 1111.
  • the first conductive block 1021 is coupled to the sixth block 40 through a via.
  • first power signal lines VDL As shown in FIG15B , among the plurality of first power signal lines VDL, two first power signal lines VDL respectively connected to two pixel circuits 21 in the same pixel circuit group are grouped together.
  • the two first power signal lines VDL in a first power signal line group are symmetrical about the first axis S1.
  • the third bending segment VDL2 bends away from the other first power signal lines VDL in the same group.
  • two data lines DL connected to two pixel circuits 21 in the same pixel circuit group constitute a data line group.
  • the two data lines DL in a data line group are symmetrical about the first axis S1.
  • a data line group is located between two first power signal lines VDL in a first power signal line group.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

La présente invention concerne un circuit de pixels, un procédé d'excitation, un panneau d'affichage et un appareil d'affichage. Le circuit de pixels comprend un sous-circuit d'attaque, un premier sous-circuit d'émission de lumière, un deuxième sous-circuit d'émission de lumière, un premier sous-circuit de réinitialisation, un sous-circuit de compensation et un premier sous-circuit de stockage. Le sous-circuit d'attaque est couplé à un premier nœud, à un deuxième nœud et à un troisième nœud ; le premier sous-circuit d'émission de lumière est couplé à une première extrémité de signal de tension, à une première extrémité de signal d'émission de lumière et au deuxième nœud ; le deuxième sous-circuit d'émission de lumière est couplé au troisième nœud, à une deuxième extrémité de signal d'émission de lumière et à une anode d'un dispositif électroluminescent ; le premier sous-circuit de réinitialisation est couplé à une extrémité de signal de réinitialisation, au premier nœud et à une première extrémité de signal d'initialisation ; le sous-circuit de compensation est couplé au premier nœud, au troisième nœud et à une première extrémité de signal de balayage ; et le premier sous-circuit de stockage est couplé à la première extrémité de signal de tension et au deuxième nœud. Le circuit de pixels est utilisé pour le panneau d'affichage.
PCT/CN2025/076709 2024-03-28 2025-02-10 Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage Pending WO2025200802A1 (fr)

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CN202410371350.2 2024-03-28

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CN116798360A (zh) * 2022-03-17 2023-09-22 京东方科技集团股份有限公司 显示基板、驱动方法和显示装置

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US20160133191A1 (en) * 2014-11-12 2016-05-12 Samsung Display Co., Ltd. Display apparatus and method of driving the same
CN112397026A (zh) * 2020-12-04 2021-02-23 上海天马有机发光显示技术有限公司 像素驱动电路、显示面板及其驱动方法
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