WO2025200802A9 - Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage - Google Patents

Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage

Info

Publication number
WO2025200802A9
WO2025200802A9 PCT/CN2025/076709 CN2025076709W WO2025200802A9 WO 2025200802 A9 WO2025200802 A9 WO 2025200802A9 CN 2025076709 W CN2025076709 W CN 2025076709W WO 2025200802 A9 WO2025200802 A9 WO 2025200802A9
Authority
WO
WIPO (PCT)
Prior art keywords
node
light
signal terminal
circuit
emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/076709
Other languages
English (en)
Chinese (zh)
Other versions
WO2025200802A1 (fr
Inventor
杜丽丽
陈家兴
尚庭华
安一
杨中流
牛佐吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025200802A1 publication Critical patent/WO2025200802A1/fr
Publication of WO2025200802A9 publication Critical patent/WO2025200802A9/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This disclosure relates to the field of display technology, and in particular to a pixel circuit and driving method, a display panel, and a display device.
  • OLED organic light-emitting diode
  • the first light-emitting sub-circuit is coupled to a first voltage signal terminal, a first light-emitting signal terminal, and the second node; the first light-emitting sub-circuit is configured to control the conduction and cutoff of the first voltage signal terminal and the second node in response to a first light-emitting signal received at the first light-emitting signal terminal.
  • the second light-emitting sub-circuit is coupled to the third node, the second light-emitting signal terminal, and the anode of the light-emitting device; the second light-emitting sub-circuit is configured to control the conduction and cutoff of the third node and the anode of the light-emitting device in response to a second light-emitting signal received at the second light-emitting signal terminal.
  • the first reset sub-circuit is coupled to a reset signal terminal, the first node, and the first initialization signal terminal; the first reset sub-circuit is configured to control the conduction and cutoff of the first initialization signal terminal and the first node in response to a reset signal received at the reset signal terminal.
  • the moment when the first voltage signal terminal and the second node begin to conduct is earlier than the moment when the third node and the anode of the light-emitting device begin to conduct; the moment when the first voltage signal terminal and the second node begin to deactivate is earlier than the moment when the third node and the anode of the light-emitting device begin to deactivate.
  • the first storage sub-circuit includes a first storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate is connected to the second node.
  • the pixel circuit further includes a second reset sub-circuit and a data writing sub-circuit.
  • the second reset sub-circuit is coupled to a second initialization signal terminal, the anode of the light-emitting device, and a second scan signal terminal; the second reset sub-circuit is configured to control the conduction and cutoff of the anode of the light-emitting device and the second initialization signal terminal in response to a second scan number received at the second scan signal terminal;
  • the data writing sub-circuit is coupled to the second node, the third scan signal terminal, and a data signal terminal; the data writing sub-circuit is configured to control the conduction and cutoff of the data signal terminal and the second node in response to a third scan number received at the third scan signal terminal.
  • the second scanning signal terminal and the third scanning signal terminal receive the same signal.
  • the first light-emitting sub-circuit includes a second transistor
  • the second light-emitting sub-circuit includes a third transistor
  • the first electrode of the second transistor is coupled to the first plate of the first storage capacitor
  • the second electrode is coupled to the second plate of the first storage capacitor
  • the control electrode is coupled to the first light-emitting signal terminal
  • the first electrode of the third transistor is coupled to the third node
  • the second electrode is coupled to the anode of the light-emitting device
  • the control electrode is coupled to the second light-emitting signal terminal EM2.
  • a driving method for a pixel circuit is provided, the driving method being used to drive the pixel circuit as described in any of the above embodiments, wherein a display frame cycle includes a reset phase; the driving method includes: in the reset phase, a first reset sub-circuit, in response to a reset signal received at a reset signal terminal, transmitting a first initialization signal received at a first initialization signal terminal to a first node; a compensation sub-circuit, in response to a first scan signal received at a first scan signal terminal, transmitting the potential at the first node to a third node; a second light-emitting sub-circuit, in response to a second light-emitting signal received at a second light-emitting signal terminal, transmitting the potential at the third node to the anode of the light-emitting device; and a first storage sub-circuit storing the potential of the second node after the end of the previous frame.
  • the reset phase includes a first reset phase and a second reset phase; in the first reset phase, the second light-emitting sub-circuit, in response to a second light-emitting signal received at the second light-emitting signal terminal, transmits the potential at the third node to the anode of the light-emitting device; the first reset sub-circuit, in response to a reset signal received at the reset signal terminal, transmits a first initialization signal received at the first initialization signal terminal to the first node; in the second reset phase, the compensation sub-circuit, in response to a first scan signal received at the first scan signal terminal, transmits the potential at the first node to the third node; the second light-emitting sub-circuit, in response to a second light-emitting signal received at the second light-emitting signal terminal, transmits the potential at the third node to the anode of the light-emitting device.
  • the pixel circuit further includes a second reset sub-circuit and a write sub-circuit; after the reset phase, a display frame cycle further includes a data write compensation phase; in the data write compensation phase, the data write sub-circuit, in response to a second scan number received at the second scan signal terminal, transmits the data signal received at the data signal terminal to the second node; the compensation sub-circuit, in response to a first scan signal received at the first scan signal terminal, transmits the potential at the second node to the first node; the second reset sub-circuit, in response to a second scan number received at the second scan signal terminal, transmits a second initialization signal received at the second initialization signal terminal to the anode of the light-emitting device.
  • a display panel in another aspect, includes a plurality of pixel circuits, each pixel circuit including a second transistor; the second transistor is coupled to a first voltage signal terminal.
  • the display panel includes a substrate, a semiconductor layer, a first conductive layer, and a second conductive layer.
  • the semiconductor layer is disposed on the substrate and includes a second active portion of the second transistor, the second active portion including a second source region, a second drain region, and a second channel region, the second channel region being disposed between the second source region and the second drain region.
  • the first conductive layer is disposed on the side of the semiconductor layer away from the substrate and includes a plurality of first conductive blocks; the orthographic projection of the first conductive blocks on the substrate overlaps with the orthographic projection of one of the second source region and the second drain region on the substrate, the overlapping portion forming a first storage capacitor; the first conductive blocks are connected to the other of the second source region and the second drain region.
  • the second conductive layer is disposed on the side of the first conductive layer away from the substrate and includes a first power signal line, the first power signal line being connected to the first conductive blocks and coupled to the first voltage signal terminal.
  • the pixel circuit further includes a first transistor
  • the semiconductor layer further includes a first active portion of the first transistor.
  • the first active portion includes a first source region, a first drain region, and a first channel region, with the first channel region disposed between the first source region and the first drain region.
  • the display panel further includes a third conductive layer disposed between the semiconductor layer and the first conductive layer, and includes a second conductive block.
  • the orthographic projection of the second conductive block on the substrate overlaps with the orthographic projection of the first channel region on the substrate.
  • the second conductive layer further includes a third conductive block, the orthographic projection of the third conductive block on the substrate overlapping with the orthographic projection of the second conductive block on the substrate, with the overlapping portion forming a second storage capacitor.
  • the first conductive block and the third conductive block are integrally disposed.
  • the pixel circuit further includes a third transistor connected to the anode of the light-emitting device.
  • the semiconductor layer further includes a third active portion of the third transistor, the third active portion including a third source region, a third drain region, and a third channel region, the third channel region being disposed between the third source region and the third drain region.
  • the third conductive layer further includes a fourth conductive block and a fifth conductive block; the orthographic projection of the fourth conductive block on the substrate overlaps with the orthographic projection of the second channel region on the substrate, and the orthographic projection of the fifth conductive block on the substrate overlaps with the orthographic projection of the third channel region on the substrate; wherein the orthographic projections of the fourth and fifth conductive blocks on the substrate are staggered.
  • the display panel further includes a fourth conductive layer; the fourth conductive layer is disposed on the side of the first conductive layer away from the third conductive layer, and the fourth conductive layer includes a first light-emitting signal line.
  • the first light-emitting signal line is coupled to a first light-emitting terminal; the first light-emitting signal line includes alternating first straight segments and first bent segments; the first straight segments extend along a first direction, the first bent segments bend toward the side of the first straight segments along a second direction, and the orthographic projection of the first bent segments on the substrate overlaps with the orthographic projection of the fourth conductive block on the substrate, and is connected to the fourth conductive block.
  • the display panel further includes a fourth conductive layer; the fourth conductive layer is disposed on the side of the first conductive layer away from the third conductive layer, and the fourth conductive layer further includes a second light-emitting signal line.
  • the second light-emitting signal line is coupled to a second light-emitting terminal; the second light-emitting signal line includes a first straight portion and a second straight portion connected together; the first straight portion extends along a first direction, the second straight portion extends along a second direction, and the orthographic projection of the second straight portion on the substrate overlaps with the orthographic projection of the fifth conductive block on the substrate, and is connected to the fifth conductive block.
  • the active layer patterns are arranged in multiple rows and columns, each row of active layer patterns includes at least two active layer patterns spaced apart along a first direction, and the spacing between any two adjacent active layer patterns is approximately equal along the first direction; each column of active layer patterns includes at least two active layer patterns spaced apart along a second direction; the orthographic projection of a fifth conductive block on the substrate overlaps with the orthographic projection of a third channel region on the substrate.
  • a second straight section is provided between any two adjacent active layer pattern groups, and the first channel region includes a second straight segment and a second bent segment; the second straight segment extends along the first direction, and the second bent segment bends toward the side of the second straight segment along the second direction.
  • the plurality of active layer patterns include a plurality of first active layer patterns and a plurality of second active layer patterns; the plurality of active layer patterns are arranged in multiple rows and columns, a row of active layer patterns is divided into multiple active layer pattern groups, and an active layer pattern group includes an adjacent first active layer pattern and a second active layer pattern; in the same active layer pattern group, the first active layer pattern and the second active layer pattern are approximately symmetrical about a first axis, the first axis extends along a second direction, and the second direction intersects the first direction; in the orthographic projection onto the substrate, the orthographic projection of one of the fifth conductive blocks on the substrate overlaps with the third channel region in the adjacent first active layer pattern and the third channel region in the second active layer pattern in two adjacent active layer pattern groups.
  • a second straight section is provided between any two adjacent active layer pattern groups; the extension direction of the first channel region is parallel to the first direction.
  • the display device includes a display panel as described in any of the above embodiments.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is another structural diagram of a display device according to some embodiments.
  • Figure 3 is a structural diagram of a display device including a display panel according to some embodiments.
  • Figure 4 is a structural diagram of a display panel including a substrate and pixel circuitry according to some embodiments
  • Figure 5 is a cross-sectional view along section line A-A in Figure 4.
  • Figure 6A is a structural diagram of a pixel circuit according to some embodiments.
  • Figure 6B is another structural diagram of a pixel circuit according to some embodiments.
  • Figure 7 is a structural diagram of a pixel circuit including transistors and capacitors according to some embodiments.
  • Figure 8 is a timing diagram of a pixel circuit according to some embodiments.
  • Figure 9 is another timing diagram of a pixel circuit according to some embodiments.
  • Figure 10 is a structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 11 is another structural diagram of the pixel circuit according to some embodiments, showing the transistors being turned on or off;
  • Figure 12 is another structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 13 is another structural diagram of a pixel circuit according to some embodiments, showing the transistors being turned on or off.
  • Figure 15A is a structural diagram of a display panel including a film layer structure according to some embodiments.
  • one display frame cycle includes a reset phase P1, a data write compensation phase P2, and a light emission phase P3.
  • the second light-emitting circuit 203 in response to the second light-emitting signal received at the second light-emitting signal terminal EM2, transmits the potential at the third node N3 to the anode of the light-emitting device 22.
  • the first initialization signal can be transmitted from the third node N3 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22, i.e., the potential of the anode of the light-emitting device 22 is Vin1.
  • Vin1-Vss the difference between the potential Vin1 of the anode of the light-emitting device 22 and the potential Vss of the cathode of the light-emitting device 22 is Vin1-Vss, which is less than the threshold voltage of the light-emitting device 22. This reduces the risk of the light-emitting device 22 emitting light at P1 during the reset phase.
  • the reset phase P1 includes a first reset phase P11 and a second reset phase P12.
  • the second light-emitting circuit 203 in response to the second light-emitting signal received at the second light-emitting signal terminal EM2, transmits the potential at the third node N3 to the anode of the light-emitting device 22.
  • the first reset sub-circuit 204 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the first node N1.
  • the first reset sub-circuit 204 maintains its state, and the compensation sub-circuit 205 responds to the first scan signal received at the first scan signal terminal GATE1 and transmits the potential at the first node N1 to the third node N3. In this way, the first initialization signal can be transmitted from the first node N1 to the third node N3 to reset the third node N3.
  • the second light-emitting circuit 203 is maintained in a state such that the first initialization signal can be transmitted from the third node N3 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22.
  • each sub-circuit in pixel circuit 21 includes a transistor 211 or a storage capacitor 212.
  • the reset signal is 0, the second light emission signal is 0, the first scan signal is 1, the second light emission signal is 1, and the second scan signal is 1.
  • "0" represents a low level and "1" represents a high level.
  • the reset signal terminal RESET and the second light-emitting signal terminal EM2 are input at a low level
  • the third transistor T3 and the fourth transistor T4 are turned on
  • the first scan signal terminal GATE1 the second light-emitting signal terminal EM2 and the second scan signal terminal GATE2 are input at a high level
  • the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned off.
  • the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the first node N1 through the fourth transistor T4, and the potential of the first node N1 is Vin1.
  • the potential of the third node N3 is transmitted to the anode of the light-emitting device 22 through the fourth transistor T4.
  • the first storage capacitor C1 can maintain a relatively stable potential corresponding to the first voltage signal terminal VDD, that is, the potential of the second node N2 is Vdd.
  • the potential difference between the first node N1 and the second node N2 is Vin1-Vdd, thereby keeping the first transistor T1 in a fixed on state.
  • the reset signal is 0, the second light-emitting signal is 0, the first scan signal is 0, the second light-emitting signal is 1, and the second scan signal is 1.
  • "0" represents a low level and "1" represents a high level.
  • the reset signal terminal RESET, the second light-emitting signal terminal EM2, and the input are all at low levels.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the first scan signal terminal GATE1, the second light-emitting signal terminal EM2, and the second scan signal terminal GATE2 are all at high levels.
  • the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are all turned off.
  • the potential at the first node N1 is transferred to the third node N3 through the fifth transistor T5, so that the potential at the third node N3 is also Vin1, i.e., the third node N3 is reset.
  • the potential at the third node N3 is transferred to the anode of the light-emitting device 22 through the third transistor T3, so that the potential of the anode of the light-emitting device 22 is Vin1, i.e., the anode of the light-emitting device 22 is reset.
  • the potential difference between the first node N1 and the second node N2 is also Vin1-VDD, so that the first transistor T1 is kept in a fixed on state.
  • the potential difference between the first node N1 and the second node N2 remains VINIT - VDD, thus keeping the first transistor T1 in a fixed on state. Therefore, regardless of whether the data signal in the previous image display frame was a high-grayscale signal or a low-grayscale signal, the first transistor T1 enters the data write compensation phase in a fixed on state during this display frame. This effectively mitigates the short-term image retention problem caused by hysteresis.
  • each sub-circuit in pixel circuit 21 includes a transistor 211 or a capacitor 212.
  • the reset signal is 0, the second light-emitting signal is 0, the first scan signal is 0, the second light-emitting signal is 1, and the second scan signal is 1.
  • "0" represents a low level and "1" represents a high level.
  • the reset signal terminal RESET, the second light-emitting signal terminal EM2, and the input are all at low levels.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on.
  • the first scan signal terminal GATE1, the second light-emitting signal terminal EM2, and the second scan signal terminal GATE2 are all at high levels.
  • the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are all turned off.
  • the first initialization signal received at the first initialization signal terminal VINIT1 is transmitted to the first node N1 through the fourth transistor T4, so that the potential of the first node N1 is Vin1.
  • the potential at the first node N1 is transmitted to the third node N3 through the fifth transistor T5, so that the potential at the third node N3 is also Vin1, that is, the third node N3 is reset.
  • the potential at the third node N3 is transmitted to the anode of the light-emitting device 22 through the third transistor T3, so that the potential of the anode of the light-emitting device 22 is Vin1, that is, the anode of the light-emitting device 22 is reset.
  • the potential difference between the first node N1 and the second node N2 is also Vin1-VDD, so that the first transistor T1 is in a fixed on state.
  • the first transistor T1 regardless of whether the data signal in the previous image display frame is a high grayscale signal or a low grayscale signal, in this display frame, the first transistor T1 enters the data writing compensation stage in a fixed on state. This can improve the problem of short-term afterimage caused by hysteresis.
  • the data writing sub-circuit 208 responds to the second scan number received at the second scan signal terminal GATE2 and transmits the data signal received at the data signal terminal DATA to the second node N2.
  • the compensation sub-circuit 205 responds to the first scan signal received at the first scan signal terminal GATE1 and transmits the potential at the second node N2 to the first node N1.
  • the second storage sub-circuit 209 is used to maintain the potential of the first node N1.
  • the second reset sub-circuit 207 responds to the second scan number received at the second scan signal terminal GATE2 and transmits the second initialization signal received at the second initialization signal terminal VINIT2 to the anode of the light-emitting device 22 to reset the anode of the light-emitting device 22.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first scan signal is 0, the second scan signal is 0, the reset signal is 1, the second light emission signal is 1, and the first light emission signal is 1.
  • “0" represents a low level and "1" represents a high level.
  • the first scan signal terminal GATE1 and the second scan signal terminal GATE2 are at low input level
  • the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all turned on
  • the reset signal terminal RESET the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are at high input level
  • the second transistor T2, the third transistor T3 and the fourth transistor T4 are all turned off.
  • the second initialization signal at the second initialization signal terminal VINIT2 is transmitted to the anode of the light-emitting device 22 through the sixth transistor T6 to reset the anode of the light-emitting device 22.
  • the difference between the potential Vin2 of the anode of the light-emitting device 22 and the potential Vss of the cathode of the light-emitting device 22 is Vin1-Vss, which is less than the threshold voltage of the light-emitting device 22. In this way, the risk of the light-emitting device 22 emitting light at P2 during the data write compensation stage can be reduced.
  • the data signal received at the DATA terminal is transmitted to the second node N2 via the seventh transistor T7, meaning the potential of the second node N2 is Vdata.
  • the potential of the first node N1 is Vint1.
  • the potential difference between the gate (first node N1) and source (second node N2) of the first transistor T1 is Vint1 - Vdata.
  • the first transistor T1 is turned on, and the data signal is transmitted from the third node N3 to the second node N2.
  • the data signal at the second node N2 is transmitted to the first node N1 via the fifth transistor T5.
  • the potential of the first node N1 gradually increases from Vin1.
  • the potential of the first node N1 rises to Vdata + Vth
  • the first transistor T1 is turned off, and the data write compensation stage P2 ends.
  • the data signal Vdata and the threshold voltage Vth are written to the second storage capacitor C2.
  • the first light-emitting circuit 202 responds to the first light-emitting signal received at the first light-emitting signal terminal EM1 and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2, that is, the potential of the second node is Vdd.
  • the driving sub-circuit 201 generates a driving current under the control of the potentials of the first node N1 and the second node N2, and outputs the driving current to the third node N3.
  • the second light-emitting sub-circuit 203 transmits the driving current received at the third node N3 to the anode of the light-emitting device 22, thereby causing the light-emitting device 22 to emit light under the control of the driving current.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first light emission signal is 0, the second light emission signal is 0, the reset signal is 1, the first scan signal is 1, and the second scan signal is 1.
  • the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are input with a low level, and the second transistor T2 and the third transistor T3 are turned on.
  • the reset signal terminal RESET, the first scan signal terminal GATE1, and the second scan signal terminal GATE2 are input with a high level, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off.
  • the first voltage signal at the first voltage signal terminal VDD is transmitted to the second node N2 through the second transistor T2, that is, the potential of the second node is Vdd.
  • the potential of the first node N1 is Vdata + Vth.
  • the first transistor T1 generates a driving current under the control of the potentials of the first node N1 and the third node N3, and the first transistor T1 operates in the saturation region. According to the saturation current formula, the driving current generated by the first transistor T1 (the current input to the light-emitting device 22) is:
  • W/L is the channel width-to-length ratio of the first transistor T1; ⁇ is the carrier mobility; Cox is the channel capacitance per unit area of the first transistor T1; Vgs is the gate-source voltage difference of the first transistor T1; and Vth is the threshold voltage of the first transistor T1.
  • the magnitude of the current Ioled of the input light-emitting device 22 is related to the potential Vdata of the written data signal and the first voltage signal, but is not related to the threshold voltage Vth of the first transistor T1. This avoids the problem that the different threshold voltages of the first transistor T1 of each pixel circuit 21 caused by the manufacturing process affect the magnitude of the driving current and thus affect the display effect.
  • a display frame cycle also includes a pre-light emission phase P4.
  • the first light-emitting sub-circuit 202 transmits the first voltage signal received at the first voltage signal terminal VDD to the first node N1, so that the potential of the first node N1 is Vdd.
  • each sub-circuit in pixel circuit 21 includes transistor 211 or storage capacitor 212.
  • the first light emission signal is 0, the second light emission signal is 1, the first scan signal is 1, the second scan signal is 1, and the reset signal is 1.
  • the first light-emitting signal terminal EM1 is input with a low level, and the second transistor T2 is turned on.
  • the second light-emitting signal terminal EM2, the first scan signal terminal GATE1, the second scan signal terminal GATE2, and the fifth signal terminal are input with a high level, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off.
  • the first voltage signal received at the first voltage signal terminal VDD is transmitted to the second node N2 through the second transistor T2, thereby charging the second node N2, and the potential of the second node N2 changes from Vdata to Vdd. Since the fifth transistor T5 is turned off in this stage, the light-emitting device 22 does not emit light in this pre-light emission stage P4, and prepares for the light emission in the next stage.
  • the following description exemplifies some embodiments of the present disclosure by assuming that all pixel circuits 21 are arranged in multiple rows and columns.
  • the implementation of the present disclosure is not limited thereto.
  • a plurality of pixel circuits 21 arranged along the first direction X are referred to as a row of pixel circuits 21, and a plurality of pixel circuits 21 arranged along the second direction Y are referred to as a column of pixel circuits 21.
  • the display panel 100 also includes multiple gate lines GL, multiple data lines DL, multiple first power signal lines VDL, multiple first initialization signal lines VL1, and multiple second initialization signal lines VL2.
  • each gate line GL extends approximately along the first direction X and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, a first light emission signal, and a second light emission signal.
  • a gate line GL can be connected to any one of the first scan signal terminal GATE1, the second scan signal terminal GATE2, the reset signal terminal RESET, the first light emission signal terminal EM1, and the second light emission signal terminal EM2 of a row pixel circuit 21.
  • the data line DL extends approximately along the second direction Y and is configured to transmit data signals.
  • a data line DL can be connected to the data signal terminal DATA of a column of pixel circuits 21.
  • the first power signal line VDL extends approximately along the second direction Y and is configured to transmit a first power potential signal.
  • a first power signal line VDL can be connected to the first voltage signal terminal VDD of a column of pixel circuits 21.
  • the first initialization signal line VL1 extends approximately along the first direction X and is configured to transmit a first initialization signal.
  • a first initialization signal line VL1 can be connected to the first initialization signal terminal VINIT1 of a row pixel circuit 21.
  • the second initialization signal line VL2 extends approximately along the first direction X and is configured to transmit a second initialization signal.
  • a second initialization signal line VL2 can be connected to the second initialization signal terminal VINIT2 of a row pixel circuit 21.
  • the pixel circuit 21 provided in some embodiments of this disclosure will be described below with reference to the film layer of the display panel 100.
  • the display panel 100 further includes a semiconductor layer 101, a first conductive layer 102, and a second conductive layer 103.
  • the first conductive layer 102 is a second gate conductive layer
  • the second conductive layer 103 is a second source/drain conductive layer.
  • a semiconductor layer 101 is disposed on the substrate 10.
  • the semiconductor layer 101 includes a plurality of active layer patterns 1011, each active layer pattern 1011 including the active portion of each transistor 211 in each pixel circuit 21.
  • the active layer pattern 1011 includes a first active portion t1 of a first transistor T1, a first active portion t2 of a second transistor T2, a third active portion t3 of a third transistor T3, a fourth active portion t4 of a fourth transistor T4, a fifth active portion t5 of a fifth transistor T5, a sixth active portion t6 of a sixth transistor T6, and a seventh active portion of a seventh transistor T7.
  • each transistor includes a source region, a drain region, and a channel region, with the channel region located between the source region and the drain region.
  • the first channel region t13 is located between the first source region t11 and the first drain region t12
  • the second channel region t23 is located between the second source region t21 and the second drain region t22
  • the third channel region t33 is located between the third source region t31 and the third drain region t32
  • the fourth channel region t43 is located between the fourth source region t41 and the fourth drain region t42
  • the fifth channel region t53 is located between the fifth source region t51 and the fifth drain region t52
  • the sixth channel region t63 is located between the sixth source region t61 and the sixth drain region t62
  • the seventh channel region t73 is located between the seventh source region t71 and the seventh drain region t72.
  • each transistor 211 included in the active layer pattern 1011 are integrally disposed.
  • the semiconductor layer 101 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.
  • the semiconductor layer 101 is fabricated, for example, by depositing a semiconductor material on the surface of the substrate 10, followed by an etching process to form the semiconductor layer 101, thereby giving the semiconductor layer 101 an active layer pattern 1011.
  • the first conductive layer 102 is disposed on the side of the semiconductor layer 101 away from the substrate 10, and includes a plurality of first conductive blocks 1021.
  • the orthogonal projection of the first conductive block 1021 onto the substrate 10 overlaps with the orthogonal projection of one of the second source region t21 and the second drain region t22 onto the substrate 10, and the overlapping portion forms the first storage capacitor C1. This simplifies the film structure and reduces the fabrication cost.
  • the first conductive block 1021 is connected to the other of the second source region t21 and the second drain region t22, thereby enabling the first storage capacitor C1 and the second transistor T2 to be coupled.
  • the first conductive block 1021 is connected to the second drain region t22, and the orthographic projection of the first conductive block 1021 on the substrate overlaps with the orthographic projection of the second source region t21 on the substrate 10.
  • the shape of the orthographic projection of the first conductive block 1021 on the substrate 10 is approximately equal to the orthographic projection of the second drain region t22 on the substrate 10.
  • the display panel 100 further includes a sixth block 40, which is connected to one of the second source region t21 and the second drain region t22 via a via, and is also connected to the first conductive block 1021 via a via.
  • a second conductive layer 103 is disposed on the side of the first conductive layer 102 away from the substrate 10.
  • the second conductive layer 103 includes a first power signal line VDL, which is connected to the first conductive block 1021 and configured to be coupled to a first voltage signal terminal VDD. This allows the first storage capacitor C1 and the second transistor T2 to be coupled to the first voltage signal terminal VDD.
  • the first power signal line VDL includes an alternately connected third straight segment VDL1 and a third bent segment VDL2.
  • the third straight segment VDL1 extends along a second direction, and the third bent segment VDL2 bends away from the third straight segment VDL1 along a first direction X.
  • the second conductive layer 103 also includes a data line DL, configured to be coupled to a data signal terminal DATA.
  • the data line DL is coupled to a fourth source region t41 so that the fourth transistor T4 is coupled to the data signal terminal DATA.
  • the display panel 100 further includes a third conductive layer 104.
  • the third conductive layer 104 is a first gate conductive layer.
  • the third conductive layer 104 is disposed between the semiconductor layer 101 and the first conductive layer 102.
  • the third conductive layer 104 includes a second conductive block 1041, the orthographic projection of the second conductive block 1041 on the substrate 10 overlaps with the orthographic projection of the first channel region t13 on the substrate 10, that is, the portion of the second conductive block 1041 that overlaps with the first channel region t13 forms the gate of the first transistor T1.
  • the first conductive layer 102 also includes a third conductive block 1022.
  • the orthographic projection of the third conductive block 1022 onto the substrate 10 overlaps with the orthographic projection of the second conductive block 1041 onto the substrate 10, and the overlapping portion forms the second storage capacitor C2.
  • the first conductive layer 102 also includes a first conductive block 1021. That is, the first conductive block 1021 and the third conductive block 1022 are made of the same material and are disposed in the same layer. In this case, the first conductive block 1021 and the third conductive block 1022 can be formed in a single patterning process, thereby reducing the manufacturing cost.
  • the first conductive block 1021 and the third conductive block 1022 are directly connected.
  • directly connected means that the first conductive block 1021 and the third conductive block 1022 are not connected through other connection structures (e.g., connecting wires and connecting holes).
  • one of the first conductive block 1021 and the third conductive block 1022 is coupled to the first power signal line through a via, so that both the first conductive block 1021 and the third conductive block 1022 are coupled to the first power signal line, thereby reducing the number of vias and simplifying the film layer structure of the display panel 100.
  • the third conductive layer 104 further includes a fourth conductive block 1042 and a fifth conductive block 1043.
  • the orthographic projection of the fourth conductive block 1042 on the substrate 10 overlaps with the orthographic projection of the second channel region t23 on the substrate 10, that is, the portion of the fourth conductive block 1042 that overlaps with the second channel region t23 forms the gate of the second transistor T2.
  • the orthographic projection of the fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of the third channel region t33 on the substrate 10, that is, the portion of the fifth conductive block 1043 that overlaps with the third channel region t33 forms the gate of the third transistor T3.
  • the orthographic projections of the fourth conductive block 1042 and the fifth conductive block 1043 on the substrate 10 are staggered.
  • the third conductive layer 104 also includes a first scan signal line GL1, a second scan signal line GL2, and a reset signal line RL.
  • the first scan signal line GL1 is configured to be coupled to the first scan signal terminal GATE1.
  • the orthogonal projection of the first scan signal line GL1 on the substrate 10 overlaps with the fifth channel region t53.
  • the portion of the first scan signal line GL1 that overlaps with the fifth channel region t53 forms the gate of the fifth transistor T5.
  • the second scan signal line GL2 is configured to be coupled to the second scan signal terminal GATE2.
  • the orthographic projection of the second scan signal line GL2 on the substrate 10 overlaps with the orthographic projection of the sixth channel region t63 on the substrate 10, and also overlaps with the orthographic projection of the seventh channel region t73 on the substrate 10.
  • the portion of the second scan signal line GL2 that overlaps with the sixth channel region t63 forms the gate of the sixth transistor T6, and the portion that overlaps with the seventh channel region t73 forms the gate of the seventh transistor T7.
  • the reset signal line RL is configured to be coupled to the reset signal terminal.
  • the orthographic projection of the reset signal line RL on the substrate 10 overlaps with the orthographic projection of the fourth channel region t43 on the substrate 10.
  • the portion of the reset signal line RL that overlaps with the fourth channel region t43 forms the gate of the fourth transistor T4.
  • the display panel 100 further includes a fourth conductive layer 105, for example, the fourth conductive layer 105 is a first source/drain conductive layer.
  • the fourth conductive layer 105 is disposed on the side of the first conductive layer 102 away from the third conductive layer 104, and the fourth conductive layer 105 includes a first light-emitting signal line EL1 and a second light-emitting signal line EL2.
  • the first light-emitting signal line EL1 is configured to be coupled to a first light-emitting signal terminal EM1
  • the second light-emitting signal line EL2 is configured to be coupled to a second light-emitting signal terminal EM2.
  • the first light-emitting signal line EL1 includes an alternately connected first straight segment EL11 and a first bent segment EL12.
  • the first straight segment EL11 extends along a first direction X
  • the first bent segment EL12 bends towards the side of the first straight segment EL11 along a second direction Y.
  • the orthographic projection of the first bent segment EL11 on the substrate 10 overlaps with the orthographic projection of the fourth conductive block 1042 on the substrate 10, and is connected to the fourth conductive block 1042. This arrangement allows the second transistor T2 to be coupled to the first light-emitting signal terminal EM1.
  • the first straight segment EL11 is disposed between the third conductive block 1022 and the fourth conductive block 1042, and the first bent segment EL12 bends toward the side of the third conductive block 1022 closer to the fourth conductive block 1042.
  • the second light-emitting signal line EL2 includes a first straight section EL21 and a second straight section EL22 connected to each other.
  • the first straight section EL21 extends along a first direction X
  • the second straight section EL22 extends along a second direction Y.
  • the orthographic projection of the second straight section EL22 on the substrate 10 overlaps with the orthographic projection of the fifth conductive block 1043 on the substrate 10, and is connected to the fifth conductive block 1043. This arrangement allows the third transistor T3 to be coupled to the second light-emitting signal terminal EM2.
  • the active layer patterns 1011 are arranged in multiple rows and columns. Each row of active layer patterns 1011 includes at least two active layer patterns 1011 spaced apart along a first direction X. The spacing between any two adjacent active layer patterns 1011 along the first direction X is approximately equal.
  • the orthographic projection of a fifth conductive block 1043 on the substrate 10 overlaps with the orthographic projection of a third channel region t33 on the substrate 10.
  • a plurality of second straight sections EL22 are arranged at intervals along the first direction X.
  • a second straight section EL22 is disposed between any two adjacent active layer patterns 1011.
  • the number of second straight sections EL22 is large, occupying a large area, which results in a shorter length of the channel region extending along the first direction X in the active layer pattern 1011, thereby causing a decrease in the performance (e.g., carrier mobility) of the transistor including this channel region.
  • the first channel region in the active layer pattern 1011 extends along the first direction X.
  • the first channel region t13 includes a second straight segment t131 and a second bent segment t132; the second straight segment t131 extends along the first direction X, and the second bent segment t132 bends toward the side of the second straight segment t131 along the second direction Y. In this way, the length of the first channel region t13 can be increased, thereby improving the performance of the first transistor T1.
  • first power signal lines VDL and data lines DL are arranged in an overlapping manner along the first direction X.
  • the plurality of active layer patterns 1011 include a plurality of first active layer patterns 1111 and a plurality of second active layer patterns 1112.
  • the plurality of active layer patterns 1011 are arranged in multiple rows and columns, and a row of active layer patterns 1011 is divided into a plurality of active layer pattern groups 1011.
  • An active layer pattern group 1011 includes an adjacent first active layer pattern 1111 and a second active layer pattern 1112.
  • the first active layer pattern 1111 and the second active layer pattern 1112 are approximately symmetrical about a first axis S1, and the first axis S1 extends along a second direction Y.
  • the orthographic projection of a fifth conductive block 1043 onto the substrate 10 overlaps with the third channel region t33 in the first active layer pattern 1111 and the third channel region t33 in the second active layer pattern 1112 of the two adjacent active layer pattern groups.
  • the fifth conductive block 1043 is coupled to the second light-emitting signal line EL2 via vias, the number of vias can be reduced, simplifying the film structure.
  • the second straight sections EL22 are arranged at intervals along the first direction X.
  • a second straight section EL22 is disposed between any two adjacent active layer pattern groups.
  • the number of second straight sections EL22 is small, and the area they occupy is small, so that the length of the channel region extending along the first direction X in the active layer pattern 1011 is appropriate, thereby improving the performance of the transistors including the channel region.
  • the extension direction of the first channel region t13 is parallel to the first direction X. In this case, the performance of the first transistor T1 is better.
  • the sixth block 40 is coupled to one of the second source region and the second drain region in the first active layer pattern 1111 through a via, and is also coupled to the second drain region t22 through a via.
  • the first conductive block 1021 overlapping with the first active layer pattern 1111 and the first conductive block 1021 overlapping with the second active layer pattern 1112 belonging to the same group as the first active layer pattern 1111 are directly connected.
  • the first conductive block 1021 is coupled to the sixth block 40 through a via.
  • the two first power signal lines VDL connected to the two pixel circuits 21 in the same pixel circuit group form a group, and the two first power signal lines VDL in a group are symmetrical about the first axis S1.
  • the third bending segment VDL2 bends away from the other first power signal line VDL in the same group.
  • two data lines DL connected to two pixel circuits 21 in the same pixel circuit group respectively constitute a data line group.
  • the two data lines DL of a data line group are symmetrical about the first axis S1.
  • a data line group is located between two first power signal lines VDL in a first power signal line group.

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Abstract

La présente invention concerne un circuit de pixels, un procédé d'excitation, un panneau d'affichage et un appareil d'affichage. Le circuit de pixels comprend un sous-circuit d'attaque, un premier sous-circuit d'émission de lumière, un deuxième sous-circuit d'émission de lumière, un premier sous-circuit de réinitialisation, un sous-circuit de compensation et un premier sous-circuit de stockage. Le sous-circuit d'attaque est couplé à un premier nœud, à un deuxième nœud et à un troisième nœud ; le premier sous-circuit d'émission de lumière est couplé à une première extrémité de signal de tension, à une première extrémité de signal d'émission de lumière et au deuxième nœud ; le deuxième sous-circuit d'émission de lumière est couplé au troisième nœud, à une deuxième extrémité de signal d'émission de lumière et à une anode d'un dispositif électroluminescent ; le premier sous-circuit de réinitialisation est couplé à une extrémité de signal de réinitialisation, au premier nœud et à une première extrémité de signal d'initialisation ; le sous-circuit de compensation est couplé au premier nœud, au troisième nœud et à une première extrémité de signal de balayage ; et le premier sous-circuit de stockage est couplé à la première extrémité de signal de tension et au deuxième nœud. Le circuit de pixels est utilisé pour le panneau d'affichage.
PCT/CN2025/076709 2024-03-28 2025-02-10 Circuit de pixels, procédé d'excitation, panneau d'affichage et appareil d'affichage Pending WO2025200802A1 (fr)

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CN202410371350.2A CN120726945A (zh) 2024-03-28 2024-03-28 像素电路及驱动方法、显示面板和显示装置
CN202410371350.2 2024-03-28

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KR102343143B1 (ko) * 2014-11-12 2021-12-27 삼성디스플레이 주식회사 표시 장치 및 그의 구동 방법
CN112397026B (zh) * 2020-12-04 2022-06-28 武汉天马微电子有限公司 像素驱动电路、显示面板及其驱动方法
CN113436583B (zh) * 2021-06-30 2022-10-14 昆山国显光电有限公司 显示面板及其驱动方法
CN116798360A (zh) * 2022-03-17 2023-09-22 京东方科技集团股份有限公司 显示基板、驱动方法和显示装置
CN115376461B (zh) * 2022-08-29 2025-09-26 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN115331609B (zh) * 2022-10-12 2023-01-10 昆山国显光电有限公司 像素电路及其驱动方法
CN116229899B (zh) * 2022-12-27 2026-03-03 云谷（固安）科技有限公司 像素电路及其驱动方法、显示面板和显示装置
CN116343648B (zh) * 2023-03-22 2025-10-31 合肥维信诺科技有限公司 像素驱动电路及其驱动方法、显示装置

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