WO2025211009A1 - Circuit électronique et appareil électronique - Google Patents

Circuit électronique et appareil électronique

Info

Publication number
WO2025211009A1
WO2025211009A1 PCT/JP2025/003924 JP2025003924W WO2025211009A1 WO 2025211009 A1 WO2025211009 A1 WO 2025211009A1 JP 2025003924 W JP2025003924 W JP 2025003924W WO 2025211009 A1 WO2025211009 A1 WO 2025211009A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
semiconductor chip
current
digital
current flowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2025/003924
Other languages
English (en)
Japanese (ja)
Inventor
保博 落合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2025211009A1 publication Critical patent/WO2025211009A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters

Definitions

  • This technology relates to electronic circuits and electronic devices. More specifically, this technology relates to electronic circuits and electronic devices that can control operation timing based on current monitoring.
  • the switching current of the electronic circuit may be monitored.
  • technology has been disclosed for dynamically probing power supply fluctuations within electronic circuits (see, for example, Non-Patent Document 1).
  • This technology was developed in light of these circumstances, and aims to suppress malfunctions caused by interference within electronic circuits.
  • the analog circuit may include an AD (Analog to Digital) conversion circuit. This has the effect of suppressing a decrease in AD conversion accuracy caused by switching noise generated in the digital circuit, based on the current flowing through the semiconductor chip monitored on the semiconductor chip.
  • AD Analog to Digital
  • the timing adjustment circuit may adjust the operation timing of at least one of the analog circuit and the digital circuit so that the operation period of the analog circuit is set during the flat portion of the waveform of the current flowing through the semiconductor chip. This has the effect of reducing the influence of switching noise generated in the digital circuit during the operation period of the analog circuit.
  • the timing adjustment circuit may include a register that stores an adjustment value for the operation timing of at least one of the analog circuit and the digital circuit, and the adjustment value may be set in the register externally. This has the effect of making it possible to manually set the operation period of the analog circuit so as to reduce the effects of switching noise generated in the digital circuit.
  • an output interface may be provided that digitizes the monitoring results of the current flowing through the semiconductor chip and outputs the results to the outside. This has the effect of suppressing a decrease in the monitoring accuracy of the current flowing through the semiconductor chip that is monitored on the semiconductor chip, while making it possible to display the waveform of that current.
  • the current consumption circuit may consume the current flowing through the semiconductor chip so that the waveform of the current flowing through the semiconductor chip is flattened during the operation period of the analog circuit. This has the effect of flattening the waveform of the current flowing through the semiconductor chip, which cannot be achieved by adjusting the timing of the operation periods of the analog circuit and the digital circuit.
  • the timing adjustment circuit after the timing adjustment circuit adjusts the operation timing, the timing adjustment circuit, the current monitor circuit, and the current consumption circuit may be turned off. This has the effect of adjusting the timing of the interference period within the electronic circuit while suppressing an increase in power consumption.
  • the device may further include a voltage monitor circuit that monitors a voltage corresponding to the frequency component of the current based on the current monitored by the current monitor circuit. This provides the effect of realizing voltage monitoring based on current monitoring.
  • a second aspect is an electronic device comprising a sensor that performs sensing and an electronic circuit that processes the output from the sensor, the electronic circuit being formed on a semiconductor chip and comprising an AD conversion circuit that AD converts the output from the sensor, a digital circuit embedded in the semiconductor chip, a current monitoring circuit that monitors the current flowing through the semiconductor chip on the semiconductor chip, and a timing adjustment circuit that adjusts the operation timing of at least one of the AD conversion circuit or the digital circuit based on the waveform of the current flowing through the semiconductor chip.
  • This has the effect of suppressing a decrease in the accuracy of AD conversion of sensor data caused by switching noise generated in the digital circuit based on the current flowing through the semiconductor chip monitored on the semiconductor chip.
  • 1 is a block diagram showing an example of the configuration of a semiconductor chip on which an electronic circuit according to a first embodiment is formed; 10A and 10B are diagrams illustrating an example of a modification of the AD conversion timing according to the first embodiment; 1 is a block diagram illustrating a configuration example of a digital circuit according to a first embodiment.
  • 5A and 5B are diagrams illustrating current waveforms before and after a change in the start-up timing of the digital circuit according to the first embodiment.
  • 4A and 4B are diagrams illustrating examples of monitoring positions of a current flowing in a semiconductor chip according to the first embodiment;
  • FIG. 10 is a diagram showing a change in monitor current due to differences in monitor position according to the first embodiment.
  • FIG. 4 is a block diagram showing a first example of current monitor data output according to the first embodiment.
  • FIG. 10 is a block diagram illustrating a second example of current monitor data output according to the first embodiment.
  • FIG. 2 is a block diagram illustrating a first example of data output from the AD conversion circuit according to the first embodiment.
  • FIG. 10 is a block diagram illustrating a second example of data output from the AD conversion circuit according to the first embodiment.
  • FIG. 10 is a block diagram illustrating a third example of data output from the AD conversion circuit according to the first embodiment.
  • FIG. 10 is a block diagram showing a configuration example of a semiconductor chip on which an electronic circuit according to a second embodiment is formed.
  • FIG. 10 is a diagram illustrating a method for setting AD conversion timing according to a second embodiment.
  • FIG. 11 is a block diagram showing a configuration example of a semiconductor chip on which an electronic circuit according to a third embodiment is formed.
  • FIG. 10 is a diagram illustrating a first configuration example of a current consumption circuit according to a third embodiment.
  • FIG. 10 is a diagram illustrating a second configuration example of a current consumption circuit according to a third embodiment.
  • FIG. 11 is a diagram illustrating a method for setting AD conversion timing according to a third embodiment.
  • FIG. 11 is a diagram illustrating a method for setting current consumption timing according to a third embodiment.
  • 10 is a flowchart showing a method for changing the activation timing of a digital circuit according to a third embodiment.
  • FIG. 10 is a diagram illustrating a method for setting AD conversion timing according to a fourth embodiment.
  • FIG. 10 is a diagram illustrating a method for setting AD conversion timing according to a fourth embodiment.
  • FIG. 13 is a diagram illustrating a method for setting current consumption timing according to a fourth embodiment.
  • 10 is a flowchart showing a method for changing the activation timing of a digital circuit according to a fourth embodiment
  • 10A and 10B are diagrams illustrating a method for monitoring a voltage of a semiconductor chip on which an electronic circuit is formed according to a fifth embodiment.
  • FIG. 11 is a diagram illustrating the relationship between frequency and impedance of an electronic circuit according to a fifth embodiment.
  • 1 is a block diagram illustrating a schematic configuration example of a vehicle control system.
  • FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • the activation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 can be stored in register 123A so that the operating period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100.
  • Checking the flat portion of the waveform of the current flowing through the semiconductor chip 100 and storing the activation timing of the digital circuit 120 and the sub-circuits included in the digital circuit 120 in register 123A can be done manually.
  • the activation timing of the AD conversion circuit 112 can be stored in register 124A so that the operating period of the AD conversion circuit 112 is set to the flat portion of the waveform of the current flowing through the semiconductor chip 100. Checking the flat portion of the waveform of the current flowing through the semiconductor chip 100 and storing the activation timing of the AD conversion circuit 112 in register 124A can be done manually.
  • the digital circuit 120 may turn off the current monitor circuit 121, the digital timing adjustment circuit 123, and the AD conversion timing adjustment circuit 124 after the operation timing has been adjusted by the digital timing adjustment circuit 123 or the AD conversion timing adjustment circuit 124.
  • the AD conversion period of the AD conversion circuit 112 is set based on the AD conversion start signal. For example, when the AD conversion start signal is at a low level, the AD conversion of the AD conversion circuit 112 can be set to inactive, and when the AD conversion start signal is at a high level, the AD conversion of the AD conversion circuit 112 can be set to active.
  • the AD conversion period of the AD conversion circuit 112 can also be displayed on a display device.
  • the current waveform MA monitored by the current monitor circuit 121 and the AD conversion period T1 of the AD conversion circuit 112 can be displayed on a display device with the time axis aligned.
  • the AD conversion period T1 of the AD conversion circuit 112 overlaps with. If the AD conversion period T1 of the AD conversion circuit 112 does not overlap with the period T2 of the flat portion of the current waveform MA, the rising timing of the AD conversion start signal is manually stored in register 124A so that the operation period of the AD conversion circuit 112 is set to the period T2 of the flat portion of the current waveform MA. Note that the operation period of the AD conversion circuit 112 may also be set to the periods T1 and T3 of the flat portions of the current waveform MA.
  • the AD conversion of the AD conversion circuit 112 is performed during period T2, which is the flat portion of the current waveform MA. This makes the AD conversion of the AD conversion circuit 112 less susceptible to the switching noise of the digital circuit 120, and prevents a decrease in AD conversion accuracy in the semiconductor chip 100 on which the digital circuit 120 is embedded.
  • FIG. 3 is a block diagram showing an example configuration of a digital circuit according to the first embodiment. While the diagram shows an example in which the digital circuit 120 has three sub-circuits 120A to 120C, the number of sub-circuits is not limited to three, and the digital circuit 120 may have any number of sub-circuits other than three.
  • digital circuit 120 comprises multiple sub-circuits 120A to 120C. These sub-circuits 120A to 120C can be connected in parallel between power supply potential VDD and ground potential GND. The operation period of each of sub-circuits 120A to 120C can be set individually. In this case, digital timing adjustment circuit 123 can individually set the activation timing of each of sub-circuits 120A to 120C based on the data stored in register 123A.
  • Figure 4 shows current waveforms before and after changing the startup timing of the digital circuit according to the first embodiment.
  • the activation timing of each of the sub-circuits 120A to 120C can be stored in register 123A so that a flat portion TP is generated in the current waveform monitored by the current monitor circuit 121, as shown in the figure, b.
  • the digital timing adjustment circuit 123 adjusts the activation timing of each of the sub-circuits 120A to 120C based on the data stored in register 123A, thereby changing the current waveforms of each of the sub-circuits 120A to 120C during operation from WA2 to WC2, respectively, and generating a flat portion TP.
  • the AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 so that the operation period of the AD conversion circuit 112 is set to this flat portion TP. This allows a flat portion to be generated in the waveform of the current monitored by the current monitor circuit 121 when there is no flat portion in the waveform of the current monitored by the current monitor circuit 121, and allows the AD conversion circuit 112 to operate on that flat portion.
  • FIG. 5 shows an example of the monitoring position of the current flowing through the semiconductor chip according to the first embodiment
  • FIG. 6 shows the change in the monitored current due to differences in the monitoring position according to the first embodiment. Note that FIG. 5 shows the power supply systems of the digital circuit 120, package 130, and PCB board 140 equivalently.
  • semiconductor chip 100 is packaged in package 130, which is mounted on PCB (Printed Circuit Board) substrate 140.
  • a current source G is connected between the power supply potential VDD and ground potential GND of digital circuit 120, and a capacitance C1 is connected in parallel to current source G.
  • the power supply potential VDD and ground potential GND of digital circuit 120 are connected to package 130 via resistors R1 and R2, respectively.
  • Inductor L1 is connected in series to the power supply potential VDD of package 130, and inductor L2 is connected in series to the ground potential GND of package 130.
  • a capacitor C2 is connected between the power supply potential VDD and ground potential GND of package 130.
  • a capacitor C3 is connected between the power supply potential VDD and ground potential GND of package 130.
  • Inductor L3 is connected in series to the power supply potential VDD of PCB board 140, and inductor L4 is connected in series to the ground potential GND of PCB board 140.
  • a capacitor C4 is connected between the power supply potential VDD and ground potential GND of PCB board 140.
  • a capacitor C5 is connected between the power supply potential VDD and ground potential GND of PCB board 140.
  • a bypass capacitor C6 is connected in parallel to capacitor C5.
  • a current In flows through the digital circuit 120.
  • a current Io flows through the PCB board 140.
  • the current Io has a waveform in which the high-frequency components of the current In are attenuated.
  • the current monitor circuit 121 monitors the current In flowing through the digital circuit 120. This allows the current monitor circuit 121 to capture a waveform in which the high-frequency components of the current In are not attenuated.
  • Figure 7 is a block diagram showing a first example of current monitor data output according to the first embodiment.
  • the output interface 126 includes an AD conversion circuit 127.
  • the AD conversion circuit 127 digitizes the current IA monitored by the current monitor circuit 121 and outputs a digital value ID of the current IA. At this time, the AD conversion circuit 127 can output multiple bits of the digital value ID in parallel.
  • by digitizing and outputting the current IA monitored by the current monitor circuit 121 it is possible to observe the waveform of the current IA monitored by the current monitor circuit 121 externally while suppressing distortion of the waveform.
  • Figure 8 is a block diagram showing a second example of current monitor data output according to the first embodiment.
  • the output interface 126 includes an AD conversion circuit 127 and a parallel-serial conversion circuit 128.
  • the parallel-serial conversion circuit 128 serializes the multiple bits of the digital value ID output in parallel from the AD conversion circuit 127 and outputs serial data SD.
  • serializing and outputting the digital value ID output in parallel from the AD conversion circuit 127 the number of data output terminals can be reduced.
  • the digital timing adjustment circuit 123 can adjust the operation timing of the digital circuit 120 based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122.
  • the AD conversion timing adjustment circuit 124 can adjust the operation timing of the AD conversion circuit 112 based on the waveform of the current flowing through the semiconductor chip 100 recognized by the current waveform recognition circuit 122.
  • this semiconductor chip 300 has a digital circuit 320 instead of the digital circuit 220 of the second embodiment described above.
  • the other configuration of the semiconductor chip 300 of the third embodiment is the same as the configuration of the semiconductor chip 200 of the second embodiment described above.
  • the current consumption circuit 302 supplies a consumption current to the digital circuit 320.
  • This consumption current does not have to contribute to the operation of the digital circuit 320.
  • this consumption current may be consumed by a resistor or stored in a capacitor. This consumption current is reflected in the current monitored by the current monitor circuit 121.
  • the digital timing adjustment circuit 123 determines whether there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112 (S103). If there is no change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the processing ends. On the other hand, if there is a change in the current flowing through the semiconductor chip 300 during AD conversion by the AD conversion circuit 112, the digital timing adjustment circuit 123 changes the activation timing of the digital circuit 320 (S104).
  • the operation timing and current consumption timing of the analog circuit 110 or digital circuit 320 are automatically adjusted based on the waveform of the current flowing through the semiconductor chip 300.
  • the operation timing and current consumption timing of the analog circuit 110 or digital circuit 320 are automatically adjusted based on the waveform of the current flowing through the semiconductor chip 300.
  • the AD conversion period of the AD conversion circuit 112 during CDS operation is set based on the AD conversion start signal. For example, when the AD conversion start signal is low level, the AD conversion of the P phase and D phase of the AD conversion circuit 112 can be set to inactive, and when the AD conversion start signal is high level, the AD conversion of the P phase and D phase of the AD conversion circuit 112 can be set to active.
  • the current monitor circuit 121 monitors the current flowing through the semiconductor chip 300 on the semiconductor chip 300.
  • the current monitored by the current monitor circuit 121 is input to the current waveform recognition circuit 122.
  • the current waveform recognition circuit 122 can detect the flat portion of the current waveform ME.
  • FIG. 21 shows a method for setting current consumption timing according to the fourth embodiment.
  • the current consumption control circuit 301 detects the slope of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period.
  • the current consumption control circuit 301 controls the current consumption circuit 302 so that a current FI is consumed during the P-phase AD conversion period and the D-phase AD conversion period.
  • the current consumption control circuit 301 recognizes whether the slopes of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period match, based on the waveform MF of the current flowing through the semiconductor chip 300 recognized by the current waveform recognition circuit 122.
  • the current consumption control circuit 301 can then adjust the current FI during the D-phase AD conversion period so that the slopes of the waveform MF during the P-phase AD conversion period and the D-phase AD conversion period match.
  • the slopes of the waveforms MF during the P-phase AD conversion period and the D-phase AD conversion period are the same, the same switching noise will be superimposed on the P-phase analog signal and the D-phase analog signal generated by the analog signal generating source 111. Therefore, by digitizing the difference between the P-phase analog signal and the D-phase analog signal, the switching noise superimposed on the P-phase analog signal and the D-phase analog signal can be canceled out.
  • the digital circuit 320 performs processing similar to that of the third embodiment described above (S101 to S105).
  • the current consumption control circuit 301 determines whether the change in current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation is the same (S201). If the change in current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation is the same, processing ends. On the other hand, if the change in current flowing through the semiconductor chip 300 during the P-phase AD conversion period and the D-phase AD conversion period during CDS operation is not the same, the current consumption control circuit 301 controls the current consumption supplied from the current consumption circuit 302 (S202) and returns processing to S101.
  • the operation timing and current consumption timing of the analog circuit 110 or the digital circuit 320 during CDS operation are adjusted based on the waveform of the current flowing through the semiconductor chip 300. This makes it possible to reduce the effects of switching noise generated in the digital circuit when the CDS circuit is operating, even when it is difficult to flatten the waveform of the current flowing through the semiconductor chip 300.
  • the operation timing of the analog circuit 110 or the digital circuit 220 is automatically adjusted based on the waveform of the current flowing through the semiconductor chip 200.
  • a voltage corresponding to the frequency component of the current is monitored.
  • a current source G is connected between the power supply potential VDD and ground potential GND of the digital circuit 220, and a series circuit of a capacitor C11 and a resistor R11 is connected in parallel to the current source G.
  • the power supply potential VDD is connected to the ground potential GND via a series circuit of a resistor R12 and an inductor L11.
  • V(t) R ⁇ I(t)
  • V(t) L ⁇ d/dtI(t)
  • V(t) 1/C ⁇ I(t)dt
  • R is the resistance component of the loop impedance of the digital circuit 220
  • L is the inductance component of the loop impedance of the digital circuit 220
  • C is the capacitance component of the loop impedance of the digital circuit 220.
  • the voltage V(t) is determined by the frequency of the current I(t), the resistance component R, the inductance component L, and the capacitance component C.
  • the resistance component R and the inductance component L are parasitic resistance and parasitic inductance components generated by the power supply wiring and ground wiring of the package or substrate outside the semiconductor chip 200, and are the sum of the power supply and ground components.
  • the capacitance component C is a stabilizing capacitance connected between the power supply and ground of the digital circuit 220.
  • Figure 26 shows an example of the installation position of the imaging unit 12031.
  • At least one of the image capturing units 12101 to 12104 may have a function for acquiring distance information.
  • at least one of the image capturing units 12101 to 12104 may be a stereo camera consisting of multiple image capturing elements, or an image capturing element having pixels for phase difference detection.
  • the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or higher). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian.
  • the audio/video output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis.
  • the audio/video output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian in a desired position.
  • the technology disclosed herein can be applied to the drive system control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031.
  • the semiconductor chips of the first to fifth embodiments described above can be applied to the drive system control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

La présente technologie supprime des dysfonctionnements provoqués par une interférence à l'intérieur d'un circuit électronique.　Le circuit électronique comprend : un circuit analogique formé sur une puce semi-conductrice ; un circuit numérique également formé sur la puce semi-conductrice ; un circuit de surveillance de courant pour surveiller, sur la puce semi-conductrice, un courant circulant à travers la puce semi-conductrice ; et un circuit de réglage de synchronisation pour ajuster la synchronisation de fonctionnement du circuit analogique et/ou du circuit numérique sur la base de la forme d'onde du courant circulant à travers la puce semi-conductrice. Le circuit analogique peut comprendre un circuit de conversion analogique-numérique (AD).
PCT/JP2025/003924 2024-04-03 2025-02-06 Circuit électronique et appareil électronique Pending WO2025211009A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2024059939 2024-04-03
JP2024-059939 2024-04-03

Publications (1)

Publication Number Publication Date
WO2025211009A1 true WO2025211009A1 (fr) 2025-10-09

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444180A (ja) * 1990-06-11 1992-02-13 Oki Electric Ind Co Ltd コンバータ内蔵マイクロコンピュータ
JPH06104383A (ja) * 1992-09-21 1994-04-15 Fujitsu Ltd 半導体集積回路
JPH08329035A (ja) * 1995-06-02 1996-12-13 Hitachi Ltd 半導体装置
JP2002231813A (ja) * 2001-02-02 2002-08-16 Handotai Rikougaku Kenkyu Center:Kk 半導体集積回路における電源電流波形の解析方法及び解析装置
JP2004015206A (ja) * 2002-06-04 2004-01-15 Matsushita Electric Ind Co Ltd Ａ／ｄ内蔵型マイクロコンピュータ
JP2005190195A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp マイクロコントローラ
US20080094266A1 (en) * 2006-10-23 2008-04-24 Agere Systems Inc. Reducing noise associated with local reference-potential fluctuations in mixed-signal integrated circuits
JP2017077020A (ja) * 2016-12-20 2017-04-20 ルネサスエレクトロニクス株式会社 集積回路
JP2023003171A (ja) * 2021-06-23 2023-01-11 株式会社デンソー 車両用電子制御装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0444180A (ja) * 1990-06-11 1992-02-13 Oki Electric Ind Co Ltd コンバータ内蔵マイクロコンピュータ
JPH06104383A (ja) * 1992-09-21 1994-04-15 Fujitsu Ltd 半導体集積回路
JPH08329035A (ja) * 1995-06-02 1996-12-13 Hitachi Ltd 半導体装置
JP2002231813A (ja) * 2001-02-02 2002-08-16 Handotai Rikougaku Kenkyu Center:Kk 半導体集積回路における電源電流波形の解析方法及び解析装置
JP2004015206A (ja) * 2002-06-04 2004-01-15 Matsushita Electric Ind Co Ltd Ａ／ｄ内蔵型マイクロコンピュータ
JP2005190195A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp マイクロコントローラ
US20080094266A1 (en) * 2006-10-23 2008-04-24 Agere Systems Inc. Reducing noise associated with local reference-potential fluctuations in mixed-signal integrated circuits
JP2017077020A (ja) * 2016-12-20 2017-04-20 ルネサスエレクトロニクス株式会社 集積回路
JP2023003171A (ja) * 2021-06-23 2023-01-11 株式会社デンソー 車両用電子制御装置

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