AT521083A3 - Verfahren zum Lokalisieren von Vorrichtungen - Google Patents

Verfahren zum Lokalisieren von Vorrichtungen Download PDF

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Publication number
AT521083A3
AT521083A3 ATA9279/2014A AT92792014A AT521083A3 AT 521083 A3 AT521083 A3 AT 521083A3 AT 92792014 A AT92792014 A AT 92792014A AT 521083 A3 AT521083 A3 AT 521083A3
Authority
AT
Austria
Prior art keywords
donor substrate
device layer
layer
weak zone
localization method
Prior art date
Application number
ATA9279/2014A
Other languages
English (en)
Other versions
AT521083A2 (de
AT521083B1 (de
Inventor
Broekaart Marcel
Radu Ionut
Lagahe Blanchard Chrystelle
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of AT521083A2 publication Critical patent/AT521083A2/de
Publication of AT521083A3 publication Critical patent/AT521083A3/de
Application granted granted Critical
Publication of AT521083B1 publication Critical patent/AT521083B1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Micromachines (AREA)
  • Machine Tool Sensing Apparatuses (AREA)

Abstract

Verfahren zum Lokalisieren von Vorrichtungen nach dem Übertragen einer Nutzschicht (80), wobei das Verfahren die folgenden Schritte umfasst: a) das Vorsehen eines Trägersubstrats (10) umfassend: -eine Vorrichtungsschicht (40), die eine freie Oberfläche aufweist; und -Ausrichtmarkierungen (50); b) das Vorsehen eines Donatorsubstrats (60); c) das Bilden einer schwachen Zone (70) im Donatorsubstrat (60), wobei die schwache Zone (70) eine Nutzschicht (80) begrenzt; d) das Verbinden des Donatorsubstrats (60) und des Trägersubstrats (10); und e) das Brechen des Donatorsubstrats (60) in der schwachen Zone (70), um die Nutzschicht (80) auf die Vorrichtungsschicht (40) zu übertragen; wobei das Verfahren dadurch gekennzeichnet ist, dass die Ausrichtmarkierungen (50) in Hohlräumen (90) angeordnet werden, die in der Vorrichtungsschicht (40) gebildet sind, wobei die Hohlräume (90) eine Öffnung aufweisen, die mit der freien Oberfläche der Vorrichtungsschicht (40) bündig ist.
ATA9279/2014A 2013-07-15 2014-06-24 Verfahren zum Lokalisieren von Vorrichtungen AT521083B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1301697A FR3008543B1 (fr) 2013-07-15 2013-07-15 Procede de localisation de dispositifs
PCT/FR2014/051568 WO2015007971A1 (fr) 2013-07-15 2014-06-24 Procede de localisation de dispositifs

Publications (3)

Publication Number Publication Date
AT521083A2 AT521083A2 (de) 2019-10-15
AT521083A3 true AT521083A3 (de) 2019-12-15
AT521083B1 AT521083B1 (de) 2020-04-15

Family

ID=49546458

Family Applications (1)

Application Number Title Priority Date Filing Date
ATA9279/2014A AT521083B1 (de) 2013-07-15 2014-06-24 Verfahren zum Lokalisieren von Vorrichtungen

Country Status (8)

Country Link
US (2) US20160197006A1 (de)
JP (1) JP6463751B2 (de)
KR (1) KR102218891B1 (de)
AT (1) AT521083B1 (de)
DE (1) DE112014003280B4 (de)
FR (1) FR3008543B1 (de)
SG (1) SG11201510638XA (de)
WO (1) WO2015007971A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3076292B1 (fr) * 2017-12-28 2020-01-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile sur un substrat support
FR3079659B1 (fr) 2018-03-29 2020-03-13 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005142252A (ja) * 2003-11-05 2005-06-02 Sony Corp アライメントマークの形成方法および半導体装置の製造方法および半導体装置
KR100543393B1 (ko) * 2000-03-09 2006-01-20 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US20130069190A1 (en) * 2011-09-21 2013-03-21 United Microelectronics Corporation Image sensor and method for fabricating the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2628555B2 (ja) 1988-03-22 1997-07-09 富士通株式会社 半導体装置の製造方法
KR0155835B1 (ko) * 1995-06-23 1998-12-01 김광호 반도체 장치의 얼라인 키 패턴 형성방법
EP1571705A3 (de) 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat
KR101233105B1 (ko) * 2008-08-27 2013-02-15 소이텍 선택되거나 제어된 격자 파라미터들을 갖는 반도체 물질층들을 이용하여 반도체 구조물들 또는 소자들을 제조하는 방법
JP5196160B2 (ja) 2008-10-17 2013-05-15 日亜化学工業株式会社 半導体発光素子
US8536629B2 (en) 2009-02-24 2013-09-17 Nec Corporation Semiconductor device and method for manufacturing the same
WO2011132654A1 (ja) 2010-04-20 2011-10-27 住友電気工業株式会社 複合基板の製造方法
JP5440442B2 (ja) 2010-08-18 2014-03-12 株式会社リコー 光走査装置及び画像形成装置
JP5664656B2 (ja) * 2010-09-30 2015-02-04 富士電機株式会社 半導体装置の製造方法
US8502389B2 (en) * 2011-08-08 2013-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS image sensor and method for forming the same
FR3005648B1 (fr) * 2013-05-15 2016-02-12 Commissariat Energie Atomique Procede d'encapsulation d'un dispositif microelectronique comprenant une injection de gaz noble a travers un materiau permeable a ce gaz noble

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543393B1 (ko) * 2000-03-09 2006-01-20 후지쯔 가부시끼가이샤 반도체 장치 및 그 제조 방법
JP2005142252A (ja) * 2003-11-05 2005-06-02 Sony Corp アライメントマークの形成方法および半導体装置の製造方法および半導体装置
US8058137B1 (en) * 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US20130069190A1 (en) * 2011-09-21 2013-03-21 United Microelectronics Corporation Image sensor and method for fabricating the same

Also Published As

Publication number Publication date
FR3008543B1 (fr) 2015-07-17
DE112014003280B4 (de) 2026-04-30
US20160197006A1 (en) 2016-07-07
DE112014003280T5 (de) 2016-04-14
US11088016B2 (en) 2021-08-10
KR20160031489A (ko) 2016-03-22
AT521083A2 (de) 2019-10-15
FR3008543A1 (fr) 2015-01-16
WO2015007971A1 (fr) 2015-01-22
JP2016527717A (ja) 2016-09-08
SG11201510638XA (en) 2016-01-28
US20200161172A1 (en) 2020-05-21
KR102218891B1 (ko) 2021-02-24
AT521083B1 (de) 2020-04-15
JP6463751B2 (ja) 2019-02-06

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