US20160197006A1 - Method for locating devices - Google Patents

Method for locating devices Download PDF

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Publication number
US20160197006A1
US20160197006A1 US14/903,961 US201414903961A US2016197006A1 US 20160197006 A1 US20160197006 A1 US 20160197006A1 US 201414903961 A US201414903961 A US 201414903961A US 2016197006 A1 US2016197006 A1 US 2016197006A1
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US
United States
Prior art keywords
process according
layer
cavities
device layer
useful
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/903,961
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English (en)
Inventor
Marcel Broekaart
Ionut Radu
Chrystelle Lagahe Blanchard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
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Soitec SA
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Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of US20160197006A1 publication Critical patent/US20160197006A1/en
Assigned to SOITEC reassignment SOITEC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BROEKAART, MARCEL, BLANCHARD, CHRYSTELLE LAGAHE, RADU, IONUT
Abandoned legal-status Critical Current

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Classifications

    • H01L21/76254—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L23/544—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H01L2223/54426—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment

Definitions

  • This disclosure relates to a process for locating devices after transfer of a useful layer to a carrier substrate.
  • a prior-art process for locating devices after transfer of a useful layer 8 to a carrier substrate 1 comprises the following steps:
  • the device layer 4 comprises devices such as transistors, (npn or pnp) junctions, interconnections and any other structure.
  • the useful layer 8 generally comprises an opaque semiconductor layer.
  • the useful layer 8 masks the devices of the device layer 4 and the alignment marks 5 .
  • the main drawback of this process is that the alignment marks 5 are no longer accessible or observable.
  • apertures 9 must be produced in the useful layer 8 in order to expose the alignment marks 5 .
  • the process for forming the apertures 9 generally comprises a photolithography step, followed by an etching step.
  • the photolithography step is intended to define the shape and position of the apertures 9 in the useful layer 8 .
  • this step carried out with no reference point other than the edge of the carrier substrate 1 , has a precision of +/ ⁇ 100 ⁇ m. Therefore, the alignment marks 5 can be localized only to within +/ ⁇ 100 ⁇ m.
  • the apertures 9 must thus have a side length (i.e., a width) of about 250 ⁇ m. Such a side length consumes too much space, and is unacceptable.
  • One aim of the disclosure is, therefore, to provide a simpler process for locating devices after transfer of a useful layer 8 , allowing smaller apertures to be formed than with prior-art techniques.
  • This disclosure aims to remedy the aforementioned drawbacks, and relates to a process for locating devices after transfer of a useful layer, the process comprising the following steps:
  • the alignment marks are placed in cavities formed in the device layer, the cavities having an aperture flush with the free surface of the device layer.
  • the alignment marks are placed so as to make it possible to locate the devices.
  • the useful layer may be formed from a set of sublayers.
  • the useful layer is generally opaque and, therefore, masks the device layer after step e).
  • the cavities have walls, and the volume delimited by the walls of a cavity and its aperture makes up the volume of the cavity.
  • alignment marks placed in cavities is meant that the alignment marks are placed in the volume of the cavities.
  • the devices of the device layer may be located from the free surface of the useful layer.
  • the holes are automatically formed in the positions of the cavities at the moment of the transfer of the useful layer.
  • the through-holes in the useful layer have a shape that corresponds to the aperture of the cavities. Therefore, the through-holes in the useful layer do not encroach beyond the aperture of the cavities.
  • the cavities extend as far as into the carrier substrate.
  • the alignment marks are placed at the bottom of the cavities.
  • the device layer comprises devices regularly distributed over the entire extent of the device layer.
  • an opaque layer is present on the useful layer before the assembly step d).
  • the opaque layer comprises at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • step c) of forming the weak zone is executed by implanting at least one of the species selected from the following group: hydrogen and helium.
  • the fracturing step e) comprises a heat treatment executed at a temperature between 200° C. and 500° C.
  • the thickness of the useful layer is smaller than 8000 ⁇ and preferably smaller than 5000 ⁇ .
  • the useful layer comprises sublayers of different doping.
  • FIGS. 1A and 1B are schematic representations of a structure obtained with a process for locating devices according to prior-art techniques
  • FIG. 2 is a schematic representation of a process for locating devices according to one embodiment of the disclosure
  • FIG. 3 is a schematic representation of the structure obtained with the process for locating devices according to a second embodiment of the disclosure.
  • FIG. 4 is a schematic representation of the process for locating devices according to one embodiment of the disclosure.
  • FIGS. 2 and 3 schematically illustrate a process for locating devices.
  • Step a) of the process for locating devices comprises providing a carrier substrate 10 comprising a front side 20 and a back side 30 parallel to the front side 20 .
  • the carrier substrate 10 may comprise a bulk substrate on which a device layer 40 is formed on the front side 20 of the carrier substrate 10 .
  • the bulk substrate may consist of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • the bulk substrate may comprise at least one material selected from the following group: silicon, silicon carbide, silicon germanium, glass, a ceramic and a metal alloy.
  • the device layer 40 comprises devices, such as electronic devices (for example transistors, junctions, etc.), interconnections and/or metalized zones.
  • electronic devices for example transistors, junctions, etc.
  • the devices are formed using techniques well known to those skilled in the art.
  • the devices may be regularly distributed over the entire extent of the device layer 40 .
  • Cavities 90 are formed in the device layer 40 .
  • the cavities 90 are open and comprise an aperture flush with the free surface of the device layer 40 .
  • the cavities 90 comprise walls.
  • the walls of the cavity 90 and the aperture of the cavity 90 delimit the volume of the cavity 90 .
  • the cavities 90 may extend as far as into the carrier substrate 10 .
  • Alignment marks 50 are placed in the volume of the cavities 90 , and the alignment marks 50 are away from the aperture of the cavities 90 .
  • the alignment marks 50 are placed so as to make it possible to precisely locate the devices of the device layer 40 .
  • Alignment marks 50 are conventionally used to align photolithography masks.
  • the alignment marks 50 may take the form of crosses, chevrons or interference patterns, or any other form liable to allow the precise location of the devices to be determined.
  • the alignment marks 50 are placed at the bottom of the cavities 90 .
  • Step b) of the process for locating devices comprises providing a donor substrate 60 .
  • the donor substrate 60 may be made of any material conventionally used in the microelectronics, optics, optoelectronics and photovoltaic industries.
  • the donor substrate 60 may comprise at least one material selected from the following group: silicon, silicon carbide and silicon germanium.
  • the donor substrate 60 may comprise a semiconductor material.
  • Step c) of the process for locating devices may comprise forming a weak zone 70 in the donor substrate 60 .
  • the donor substrate 60 comprises a first surface.
  • the weak zone 70 and the first surface of the donor substrate 60 delimit a useful layer 80 intended to be transferred to the device layer 40 .
  • the weak zone 70 may be obtained by implanting atomic species.
  • the weakening implantation may be carried out with a single species (for example, hydrogen or helium), but may also be carried out with a plurality of sequentially implanted species (for example, hydrogen and helium).
  • the hydrogen is implanted with an energy of between 20 and 70 keV, and a dose of between 4 ⁇ 10 16 and 6 ⁇ 10 16 atoms/cm 2 .
  • the helium may be implanted with an energy of between 20 and 70 keV, and a dose of between 0.5 ⁇ 10 16 and 3 ⁇ 10 16 atoms/cm 2 .
  • the useful layer 80 may have a thickness smaller than 8000 ⁇ and preferably smaller than 5000 ⁇ .
  • Step d) of the process for locating devices may comprise assembling the donor substrate 60 and the carrier substrate 10 .
  • the assembly step d) may be executed by direct bonding.
  • the assembly may be executed by bringing the useful layer 80 into direct contact with the device layer 40 .
  • the assembly is executed so as to preserve, at least in part, the volume of the cavities 90 . Therefore, the presence of cavities 90 generates unbonded zones.
  • the assembly step d) may comprise a direct bonding step executed in an environment at a pressure below 20 mbar (2000 Pa).
  • an intermediate layer 100 may be placed on the useful layer 80 before the assembly step d).
  • the intermediate layer 100 may be an opaque layer placed on the useful layer 80 .
  • the opaque layer may comprise at least one material selected from the following group: tungsten, titanium, tungsten silicide, titanium silicide, nickel silicide, nickel silicide and platinum.
  • Step e) of the method for locating devices comprises fracturing the donor substrate 60 in the weak zone 70 so as to transfer the useful layer 80 to the device layer 40 .
  • the useful layer 80 masks the devices.
  • the opaque layer is then located intermediate between the useful layer 80 and the device layer 40 after the fracturing step.
  • the fracturing step e) may comprise a heat treatment executed at a temperature between 200° C. and 500° C.
  • the through-holes in the useful layer 80 are in positional correspondence with the cavities 90 , so that the through-holes extend the cavities 90 into the useful layer 80 .
  • each cavity 90 is inscribed in the aperture of a hole of the useful layer 80 .
  • each through-hole in the useful layer 80 may have an aperture that corresponds to the aperture in the cavity 90 into which it extends, such as illustrated in FIG. 3 .

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Micromachines (AREA)
  • Machine Tool Sensing Apparatuses (AREA)
US14/903,961 2013-07-15 2014-06-24 Method for locating devices Abandoned US20160197006A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1301697A FR3008543B1 (fr) 2013-07-15 2013-07-15 Procede de localisation de dispositifs
FR1301697 2013-07-15
PCT/FR2014/051568 WO2015007971A1 (fr) 2013-07-15 2014-06-24 Procede de localisation de dispositifs

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2014/051568 A-371-Of-International WO2015007971A1 (fr) 2013-07-15 2014-06-24 Procede de localisation de dispositifs

Related Child Applications (1)

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US16/685,938 Continuation US11088016B2 (en) 2013-07-15 2019-11-15 Method for locating devices

Publications (1)

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US20160197006A1 true US20160197006A1 (en) 2016-07-07

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US14/903,961 Abandoned US20160197006A1 (en) 2013-07-15 2014-06-24 Method for locating devices
US16/685,938 Active US11088016B2 (en) 2013-07-15 2019-11-15 Method for locating devices

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US16/685,938 Active US11088016B2 (en) 2013-07-15 2019-11-15 Method for locating devices

Country Status (8)

Country Link
US (2) US20160197006A1 (de)
JP (1) JP6463751B2 (de)
KR (1) KR102218891B1 (de)
AT (1) AT521083B1 (de)
DE (1) DE112014003280B4 (de)
FR (1) FR3008543B1 (de)
SG (1) SG11201510638XA (de)
WO (1) WO2015007971A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019186035A1 (fr) * 2018-03-29 2019-10-03 Soitec Procédé de fabrication d'un substrat donneur pour la réalisation d'une structure intégrée en trois dimensions et procédé de fabrication d'une telle structure intégrée
US11401162B2 (en) * 2017-12-28 2022-08-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for transferring a useful layer into a supporting substrate

Citations (2)

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US20130037958A1 (en) * 2011-08-08 2013-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS Image Sensor and Method for Forming the Same
US20140342487A1 (en) * 2013-05-15 2014-11-20 Commissariat A L'energie Atomique Et Aux Ene Alt Process for encapsulating a microelectronic device comprising injection of noble gas through a material permeable to this noble gas

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JP4260396B2 (ja) * 2000-03-09 2009-04-30 富士通マイクロエレクトロニクス株式会社 半導体装置およびその製造方法
JP2005142252A (ja) * 2003-11-05 2005-06-02 Sony Corp アライメントマークの形成方法および半導体装置の製造方法および半導体装置
EP1571705A3 (de) 2004-03-01 2006-01-04 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung einer Hableiterstruktur auf einem Substrat
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US20140342487A1 (en) * 2013-05-15 2014-11-20 Commissariat A L'energie Atomique Et Aux Ene Alt Process for encapsulating a microelectronic device comprising injection of noble gas through a material permeable to this noble gas

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11401162B2 (en) * 2017-12-28 2022-08-02 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for transferring a useful layer into a supporting substrate
WO2019186035A1 (fr) * 2018-03-29 2019-10-03 Soitec Procédé de fabrication d'un substrat donneur pour la réalisation d'une structure intégrée en trois dimensions et procédé de fabrication d'une telle structure intégrée
FR3079659A1 (fr) * 2018-03-29 2019-10-04 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree
CN111868915A (zh) * 2018-03-29 2020-10-30 Soitec公司 制造用于生产三维集成结构的供体衬底的工艺及用于制造这种集成结构的工艺
US11239108B2 (en) 2018-03-29 2022-02-01 Soitec Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure

Also Published As

Publication number Publication date
FR3008543B1 (fr) 2015-07-17
DE112014003280B4 (de) 2026-04-30
DE112014003280T5 (de) 2016-04-14
US11088016B2 (en) 2021-08-10
KR20160031489A (ko) 2016-03-22
AT521083A3 (de) 2019-12-15
AT521083A2 (de) 2019-10-15
FR3008543A1 (fr) 2015-01-16
WO2015007971A1 (fr) 2015-01-22
JP2016527717A (ja) 2016-09-08
SG11201510638XA (en) 2016-01-28
US20200161172A1 (en) 2020-05-21
KR102218891B1 (ko) 2021-02-24
AT521083B1 (de) 2020-04-15
JP6463751B2 (ja) 2019-02-06

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