ATE126615T1 - Leistungsfähiges protokoll für die übertragung zwischen asynchronen vorrichtungen. - Google Patents

Leistungsfähiges protokoll für die übertragung zwischen asynchronen vorrichtungen.

Info

Publication number
ATE126615T1
ATE126615T1 AT89307289T AT89307289T ATE126615T1 AT E126615 T1 ATE126615 T1 AT E126615T1 AT 89307289 T AT89307289 T AT 89307289T AT 89307289 T AT89307289 T AT 89307289T AT E126615 T1 ATE126615 T1 AT E126615T1
Authority
AT
Austria
Prior art keywords
transmission
asynchronous devices
powerful protocol
powerful
protocol
Prior art date
Application number
AT89307289T
Other languages
English (en)
Inventor
William J Bowhill
Robert Dickson
Hugh W Durdan
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of ATE126615T1 publication Critical patent/ATE126615T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Complex Calculations (AREA)
AT89307289T 1988-07-20 1989-07-19 Leistungsfähiges protokoll für die übertragung zwischen asynchronen vorrichtungen. ATE126615T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/221,920 US5040109A (en) 1988-07-20 1988-07-20 Efficient protocol for communicating between asychronous devices

Publications (1)

Publication Number Publication Date
ATE126615T1 true ATE126615T1 (de) 1995-09-15

Family

ID=22829981

Family Applications (1)

Application Number Title Priority Date Filing Date
AT89307289T ATE126615T1 (de) 1988-07-20 1989-07-19 Leistungsfähiges protokoll für die übertragung zwischen asynchronen vorrichtungen.

Country Status (6)

Country Link
US (1) US5040109A (de)
EP (1) EP0352081B1 (de)
JP (1) JPH0619756B2 (de)
AT (1) ATE126615T1 (de)
CA (1) CA1324683C (de)
DE (1) DE68923834T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US5388216A (en) * 1989-08-17 1995-02-07 Samsung Electronics Co., Ltd. Circuit for controlling generation of an acknowledge signal and a busy signal in a centronics compatible parallel interface
CA2023998A1 (en) * 1989-11-13 1991-05-14 Thomas F. Lewis Apparatus and method for guaranteeing strobe separation timing
WO1992021088A1 (en) * 1991-05-17 1992-11-26 Eastman Kodak Company Novel electrical bus structure
US5416918A (en) * 1991-07-10 1995-05-16 Hewlett-Packard Company Low skew system for interfacing asics by routing internal clock off-chip to external delay element then feeding back to on-chip drivers
US5481675A (en) * 1992-05-12 1996-01-02 International Business Machines Corporation Asynchronous serial communication system for delaying with software dwell time a receiving computer's acknowledgement in order for the transmitting computer to see the acknowledgement
GB9210414D0 (en) * 1992-05-15 1992-07-01 Texas Instruments Ltd Method and apparatus for interfacing a serial data signal
US5434975A (en) * 1992-09-24 1995-07-18 At&T Corp. System for interconnecting a synchronous path having semaphores and an asynchronous path having message queuing for interprocess communications
EP0590212A1 (de) * 1992-09-30 1994-04-06 International Business Machines Corporation Synchronisationseinrichtung für ein synchrones Datenkommunikationssystem
US5442658A (en) * 1993-09-07 1995-08-15 International Business Machines Corporation Synchronization apparatus for a synchronous data processing system
US5625805A (en) * 1994-06-30 1997-04-29 Digital Equipment Corporation Clock architecture for synchronous system bus which regulates and adjusts clock skew
US5761516A (en) * 1996-05-03 1998-06-02 Lsi Logic Corporation Single chip multiprocessor architecture with internal task switching synchronization bus
US6192073B1 (en) * 1996-08-19 2001-02-20 Samsung Electronics Co., Ltd. Methods and apparatus for processing video data
KR100280285B1 (ko) 1996-08-19 2001-02-01 윤종용 멀티미디어 신호에 적합한 멀티미디어 프로세서
US6119190A (en) * 1996-11-06 2000-09-12 Intel Corporation Method to reduce system bus load due to USB bandwidth reclamation
US6067629A (en) * 1998-08-10 2000-05-23 Intel Corporation Apparatus and method for pseudo-synchronous communication between clocks of different frequencies
US7507429B2 (en) * 2004-01-09 2009-03-24 Ecolab Inc. Methods for washing carcasses, meat, or meat products with medium chain peroxycarboxylic acid compositions
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US8624906B2 (en) * 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8683184B1 (en) * 2004-11-15 2014-03-25 Nvidia Corporation Multi context execution on a video processor
EP1812928A4 (de) * 2004-11-15 2010-03-31 Nvidia Corp Videoverarbeitung
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US9064333B2 (en) * 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
GB2464703A (en) * 2008-10-22 2010-04-28 Advanced Risc Mach Ltd An array of interconnected processors executing a cycle-based program
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
CN113110124B (zh) * 2021-03-11 2022-08-19 上海新时达电气股份有限公司 双mcu控制方法及控制系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541046A (en) * 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
US4729094A (en) * 1983-04-18 1988-03-01 Motorola, Inc. Method and apparatus for coordinating execution of an instruction by a coprocessor
US4648034A (en) * 1984-08-27 1987-03-03 Zilog, Inc. Busy signal interface between master and slave processors in a computer system
JPS6224366A (ja) * 1985-07-03 1987-02-02 Hitachi Ltd ベクトル処理装置
JP2564805B2 (ja) * 1985-08-08 1996-12-18 日本電気株式会社 情報処理装置
JPS62151971A (ja) * 1985-12-25 1987-07-06 Nec Corp マイクロ・プロセツサ装置
JPH0665550B2 (ja) * 1986-01-08 1994-08-24 株式会社日立製作所 パワ−ステアリング制御装置
JPS62214464A (ja) * 1986-03-17 1987-09-21 Hitachi Ltd データ処理システム
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor

Also Published As

Publication number Publication date
JPH02176846A (ja) 1990-07-10
EP0352081A3 (de) 1991-07-03
DE68923834D1 (de) 1995-09-21
EP0352081A2 (de) 1990-01-24
EP0352081B1 (de) 1995-08-16
DE68923834T2 (de) 1996-04-18
JPH0619756B2 (ja) 1994-03-16
CA1324683C (en) 1993-11-23
US5040109A (en) 1991-08-13

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