ATE137358T1 - Planarisationsmethode für ic-struktur - Google Patents

Planarisationsmethode für ic-struktur

Info

Publication number
ATE137358T1
ATE137358T1 AT90203417T AT90203417T ATE137358T1 AT E137358 T1 ATE137358 T1 AT E137358T1 AT 90203417 T AT90203417 T AT 90203417T AT 90203417 T AT90203417 T AT 90203417T AT E137358 T1 ATE137358 T1 AT E137358T1
Authority
AT
Austria
Prior art keywords
planarizing
layer
low melting
carried out
melting inorganic
Prior art date
Application number
AT90203417T
Other languages
English (en)
Inventor
Jeffrey Marks
Kam Shing Law
David Nin-Kou Wang
Dan Maydan
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of ATE137358T1 publication Critical patent/ATE137358T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06Planarisation of inorganic insulating materials
    • H10P95/062Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/092Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69Inorganic materials
    • H10P14/692Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
AT90203417T 1988-11-10 1989-10-24 Planarisationsmethode für ic-struktur ATE137358T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26950888A 1988-11-10 1988-11-10

Publications (1)

Publication Number Publication Date
ATE137358T1 true ATE137358T1 (de) 1996-05-15

Family

ID=23027564

Family Applications (2)

Application Number Title Priority Date Filing Date
AT90203417T ATE137358T1 (de) 1988-11-10 1989-10-24 Planarisationsmethode für ic-struktur
AT90203418T ATE137608T1 (de) 1988-11-10 1989-10-24 Planarisationsmethode für ic-struktur

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT90203418T ATE137608T1 (de) 1988-11-10 1989-10-24 Planarisationsmethode für ic-struktur

Country Status (5)

Country Link
EP (1) EP0368504A3 (de)
JP (1) JPH02199831A (de)
AT (2) ATE137358T1 (de)
DE (2) DE68926392T2 (de)
ES (2) ES2088958T3 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990010307A1 (en) * 1989-02-21 1990-09-07 Lam Research Corporation Novel glass deposition viscoelastic flow process
JPH0774146A (ja) * 1990-02-09 1995-03-17 Applied Materials Inc 低融点無機材料を使用する集積回路構造の改良された平坦化方法
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
KR0182006B1 (ko) * 1995-11-10 1999-04-15 김광호 반도체 패키지 장치 및 몰딩물질에 의해 발생하는 기생용량의 산출방법
KR102391994B1 (ko) * 2017-08-14 2022-04-28 삼성디스플레이 주식회사 멀티 스택 접합체, 멀티 스택 접합체의 제조 방법 및 멀티 스택 접합체를 포함하는 표시 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2961350A (en) * 1958-04-28 1960-11-22 Bell Telephone Labor Inc Glass coating of circuit elements
US3755720A (en) * 1972-09-25 1973-08-28 Rca Corp Glass encapsulated semiconductor device
DE2713647C2 (de) * 1977-03-28 1984-11-29 Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa Halbleitervorrichtung, bestehend aus einem Halbleitersubstrat und aus einem Oberflächenschutzfilm
EP0023146B1 (de) * 1979-07-23 1987-09-30 Fujitsu Limited Verfahren zur Herstellung einer Halbleiteranordnung, in der erste und zweite Schichten geformt sind
US4407851A (en) * 1981-04-13 1983-10-04 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JPS5834945A (ja) * 1981-08-26 1983-03-01 Nippon Telegr & Teleph Corp <Ntt> 多層配線構造体
JPS58190043A (ja) * 1982-04-30 1983-11-05 Seiko Epson Corp 多層配線法
JPS58210634A (ja) * 1982-05-31 1983-12-07 Toshiba Corp 半導体装置の製造方法
JPS62169442A (ja) * 1986-01-22 1987-07-25 Nec Corp 素子分離領域の形成方法

Also Published As

Publication number Publication date
DE68926392T2 (de) 1996-08-14
ES2088957T3 (es) 1996-10-01
DE68926392D1 (de) 1996-06-05
EP0368504A3 (de) 1990-09-12
DE68926344T2 (de) 1996-09-05
JPH02199831A (ja) 1990-08-08
ATE137608T1 (de) 1996-05-15
ES2088958T3 (es) 1996-10-01
DE68926344D1 (de) 1996-05-30
EP0368504A2 (de) 1990-05-16

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
REN Ceased due to non-payment of the annual fee