ATE141714T1 - Verfahren zur planarizierung einer oberfläche von bauelementen mit integrierter schaltung - Google Patents

Verfahren zur planarizierung einer oberfläche von bauelementen mit integrierter schaltung

Info

Publication number
ATE141714T1
ATE141714T1 AT92300020T AT92300020T ATE141714T1 AT E141714 T1 ATE141714 T1 AT E141714T1 AT 92300020 T AT92300020 T AT 92300020T AT 92300020 T AT92300020 T AT 92300020T AT E141714 T1 ATE141714 T1 AT E141714T1
Authority
AT
Austria
Prior art keywords
portions
coating
oxygen plasma
planarizing
integrated circuit
Prior art date
Application number
AT92300020T
Other languages
English (en)
Inventor
Karen Reinhardt
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE141714T1 publication Critical patent/ATE141714T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
AT92300020T 1991-02-05 1992-01-02 Verfahren zur planarizierung einer oberfläche von bauelementen mit integrierter schaltung ATE141714T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/650,625 US5290399A (en) 1991-02-05 1991-02-05 Surface planarizing methods for integrated circuit devices

Publications (1)

Publication Number Publication Date
ATE141714T1 true ATE141714T1 (de) 1996-09-15

Family

ID=24609643

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92300020T ATE141714T1 (de) 1991-02-05 1992-01-02 Verfahren zur planarizierung einer oberfläche von bauelementen mit integrierter schaltung

Country Status (5)

Country Link
US (1) US5290399A (de)
EP (1) EP0498521B1 (de)
JP (1) JPH04335517A (de)
AT (1) ATE141714T1 (de)
DE (1) DE69212853T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0817174B2 (ja) * 1993-11-10 1996-02-21 キヤノン販売株式会社 絶縁膜の改質方法
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5438022A (en) 1993-12-14 1995-08-01 At&T Global Information Solutions Company Method for using low dielectric constant material in integrated circuit fabrication
US5395785A (en) * 1993-12-17 1995-03-07 Sgs-Thomson Microelectronics, Inc. SRAM cell fabrication with interlevel dielectric planarization
US6591634B1 (en) * 1994-02-25 2003-07-15 Toshinori Morizane Method for production of metal oxide glass film at a low temperature
US5413963A (en) * 1994-08-12 1995-05-09 United Microelectronics Corporation Method for depositing an insulating interlayer in a semiconductor metallurgy system
US5567658A (en) * 1994-09-01 1996-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for minimizing peeling at the surface of spin-on glasses
US5679211A (en) * 1995-09-18 1997-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue
KR100255659B1 (ko) * 1996-03-30 2000-05-01 윤종용 반도체 장치의 sog층 처리 방법
DE19634845C1 (de) * 1996-08-28 1998-02-26 Siemens Ag Verfahren zur Optimierung der Adhäsion zwischen Preßmasse und Passivierungsschicht in einem Kunststoffchipgehäuse
EP0851470A1 (de) * 1996-12-24 1998-07-01 STMicroelectronics S.r.l. Verfahren zur Abscheidung eines geschichteten Dielektrikums zur Verbesserung der Planarität von elektronischen Halbleiterschaltungen
KR100230405B1 (ko) 1997-01-30 1999-11-15 윤종용 반도체장치의 다층 배선 형성방법
US20070015373A1 (en) * 2005-07-13 2007-01-18 General Electric Company Semiconductor device and method of processing a semiconductor substrate
MY146156A (en) * 2007-12-05 2012-06-29 Mimos Berhad Packaging method for micromechanical device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
JPH0697660B2 (ja) * 1985-03-23 1994-11-30 日本電信電話株式会社 薄膜形成方法
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
US4775550A (en) * 1986-06-03 1988-10-04 Intel Corporation Surface planarization method for VLSI technology
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
JPS6318673A (ja) * 1986-07-11 1988-01-26 Yamaha Corp 半導体装置の製法
US4721548A (en) * 1987-05-13 1988-01-26 Intel Corporation Semiconductor planarization process
GB2214709A (en) * 1988-01-20 1989-09-06 Philips Nv A method of enabling connection to a substructure forming part of an electronic device
US4894351A (en) * 1988-02-16 1990-01-16 Sprague Electric Company Method for making a silicon IC with planar double layer metal conductors system
US4826709A (en) * 1988-02-29 1989-05-02 American Telephone And Telegraph Company At&T Bell Laboratories Devices involving silicon glasses
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
US4962063A (en) * 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
KR910008980B1 (ko) * 1988-12-20 1991-10-26 현대전자산업 주식회사 자외선을 이용한 s.o.g 박막 경화 방법
US5003062A (en) * 1990-04-19 1991-03-26 Taiwan Semiconductor Manufacturing Co. Semiconductor planarization process for submicron devices
US5059448A (en) * 1990-06-18 1991-10-22 Dow Corning Corporation Rapid thermal process for obtaining silica coatings

Also Published As

Publication number Publication date
EP0498521A1 (de) 1992-08-12
JPH04335517A (ja) 1992-11-24
US5290399A (en) 1994-03-01
DE69212853D1 (de) 1996-09-26
EP0498521B1 (de) 1996-08-21
DE69212853T2 (de) 1997-02-27

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