ATE166492T1 - Verfahren zum herstellen von mos-anordnungen in vlsi-strukturen - Google Patents

Verfahren zum herstellen von mos-anordnungen in vlsi-strukturen

Info

Publication number
ATE166492T1
ATE166492T1 AT91306491T AT91306491T ATE166492T1 AT E166492 T1 ATE166492 T1 AT E166492T1 AT 91306491 T AT91306491 T AT 91306491T AT 91306491 T AT91306491 T AT 91306491T AT E166492 T1 ATE166492 T1 AT E166492T1
Authority
AT
Austria
Prior art keywords
devices
wafer
regions
nmos
constructed
Prior art date
Application number
AT91306491T
Other languages
English (en)
Inventor
James Juen Hsu
Yow Juang W Liu
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE166492T1 publication Critical patent/ATE166492T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
AT91306491T 1990-08-10 1991-07-17 Verfahren zum herstellen von mos-anordnungen in vlsi-strukturen ATE166492T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/565,384 US5091324A (en) 1990-08-10 1990-08-10 Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures

Publications (1)

Publication Number Publication Date
ATE166492T1 true ATE166492T1 (de) 1998-06-15

Family

ID=24258370

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91306491T ATE166492T1 (de) 1990-08-10 1991-07-17 Verfahren zum herstellen von mos-anordnungen in vlsi-strukturen

Country Status (5)

Country Link
US (1) US5091324A (de)
EP (1) EP0470716B1 (de)
JP (1) JP3194596B2 (de)
AT (1) ATE166492T1 (de)
DE (1) DE69129430T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2697392B2 (ja) * 1991-07-30 1998-01-14 ソニー株式会社 相補型半導体装置の製造方法
US5407849A (en) * 1992-06-23 1995-04-18 Imp, Inc. CMOS process and circuit including zero threshold transistors
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US5405788A (en) * 1993-05-24 1995-04-11 Micron Technology, Inc. Method for forming and tailoring the electrical characteristics of semiconductor devices
EP0637073A1 (de) * 1993-07-29 1995-02-01 STMicroelectronics S.r.l. Verfahren zur herstellung von P-Kanal MOS-Transistoren für komplementäre Bauteille (CMOS)
EP0653843A3 (de) * 1993-11-17 1996-05-01 Hewlett Packard Co CMOS Schaltungen mit adaptiver Spannungsschwelle.
JP2682425B2 (ja) * 1993-12-24 1997-11-26 日本電気株式会社 半導体装置の製造方法
JP2837821B2 (ja) * 1994-04-15 1998-12-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイス
US5416038A (en) * 1994-05-25 1995-05-16 United Microelectronics Corporation Method for producing semiconductor device with two different threshold voltages
KR0126789B1 (ko) * 1994-06-08 1998-04-02 김광호 매몰형 트랜지스터 제조방법
US6271093B1 (en) * 1994-06-30 2001-08-07 Siemens Aktiengesellschaft Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETs
US5698458A (en) * 1994-09-30 1997-12-16 United Microelectronics Corporation Multiple well device and process of manufacture
US5661059A (en) * 1995-04-18 1997-08-26 Advanced Micro Devices Boron penetration to suppress short channel effect in P-channel device
US5545580A (en) * 1995-09-19 1996-08-13 United Microelectronics Corporation Multi-state read-only memory using multiple polysilicon selective depositions
US5739058A (en) * 1995-12-14 1998-04-14 Micron Technology, Inc. Method to control threshold voltage by modifying implant dosage using variable aperture dopant implants
JPH104182A (ja) * 1996-06-14 1998-01-06 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
TW434834B (en) * 1996-06-29 2001-05-16 Hyundai Electronics Ind Method of manufacturing a complementary metal-oxide semiconductor device
US6096611A (en) * 1998-03-13 2000-08-01 Texas Instruments - Acer Incorporated Method to fabricate dual threshold CMOS circuits
US6271563B1 (en) 1998-07-27 2001-08-07 Advanced Micro Devices, Inc. MOS transistor with high-K spacer designed for ultra-large-scale integration
US6143612A (en) * 1998-10-14 2000-11-07 Advanced Micro Devices, Inc. High voltage transistor with high gated diode breakdown, low body effect and low leakage
WO2002019396A1 (en) * 2000-08-29 2002-03-07 Boise State University Damascene double gated transistors and related manufacturing methods
US6432777B1 (en) 2001-06-06 2002-08-13 International Business Machines Corporation Method for increasing the effective well doping in a MOSFET as the gate length decreases
US7274076B2 (en) * 2003-10-20 2007-09-25 Micron Technology, Inc. Threshold voltage adjustment for long channel transistors
JP5141028B2 (ja) * 2007-02-07 2013-02-13 富士通セミコンダクター株式会社 マスクレイアウトデータ作成方法、マスクレイアウトデータ作成装置及び半導体装置の製造方法
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8736013B2 (en) * 2012-04-19 2014-05-27 Fairchild Semiconductor Corporation Schottky diode with opposite-polarity schottky diode field guard ring
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US10811528B2 (en) 2018-03-21 2020-10-20 International Business Machines Corporation Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs
CN121054477B (zh) * 2025-10-24 2026-03-24 荣芯半导体(宁波)有限公司 一种半导体器件及其制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
JPS5952849A (ja) * 1982-09-20 1984-03-27 Fujitsu Ltd 半導体装置の製造方法
JPS61144841A (ja) * 1984-12-19 1986-07-02 Toshiba Corp 半導体装置の製造方法
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4845047A (en) * 1987-06-25 1989-07-04 Texas Instruments Incorporated Threshold adjustment method for an IGFET
JPH0760809B2 (ja) * 1987-09-08 1995-06-28 日本電気株式会社 半導体装置の製造方法
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5024961A (en) * 1990-07-09 1991-06-18 Micron Technology, Inc. Blanket punchthrough and field-isolation implant for sub-micron N-channel CMOS devices

Also Published As

Publication number Publication date
JP3194596B2 (ja) 2001-07-30
EP0470716A2 (de) 1992-02-12
US5091324A (en) 1992-02-25
DE69129430D1 (de) 1998-06-25
DE69129430T2 (de) 1999-01-28
JPH04255266A (ja) 1992-09-10
EP0470716B1 (de) 1998-05-20
EP0470716A3 (de) 1995-02-08

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