ATE171011T1 - Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate - Google Patents

Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate

Info

Publication number
ATE171011T1
ATE171011T1 AT92900715T AT92900715T ATE171011T1 AT E171011 T1 ATE171011 T1 AT E171011T1 AT 92900715 T AT92900715 T AT 92900715T AT 92900715 T AT92900715 T AT 92900715T AT E171011 T1 ATE171011 T1 AT E171011T1
Authority
AT
Austria
Prior art keywords
field oxide
floating gate
drain
walls
design
Prior art date
Application number
AT92900715T
Other languages
English (en)
Inventor
Steven J Schumann
James Cheng Hu
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Application granted granted Critical
Publication of ATE171011T1 publication Critical patent/ATE171011T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
AT92900715T 1990-11-21 1991-11-13 Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate ATE171011T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/616,460 US5086325A (en) 1990-11-21 1990-11-21 Narrow width EEPROM with single diffusion electrode formation

Publications (1)

Publication Number Publication Date
ATE171011T1 true ATE171011T1 (de) 1998-09-15

Family

ID=24469563

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92900715T ATE171011T1 (de) 1990-11-21 1991-11-13 Verfahren zur herstellung einer mos-eeprom- transistorzelle mit schwebendem gate

Country Status (7)

Country Link
US (1) US5086325A (de)
EP (1) EP0511370B1 (de)
JP (1) JP3129438B2 (de)
KR (1) KR100193551B1 (de)
AT (1) ATE171011T1 (de)
DE (1) DE69130163T2 (de)
WO (1) WO1992010002A1 (de)

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JP3344598B2 (ja) * 1993-11-25 2002-11-11 株式会社デンソー 半導体不揮発メモリ装置
JPH09512658A (ja) * 1994-04-29 1997-12-16 アトメル・コーポレイション 高速で、不揮発性の電気的にプログラム可能で、かつ消去可能なセルおよび方法
DE19526012C2 (de) * 1995-07-17 1997-09-11 Siemens Ag Elektrisch lösch- und programmierbare nicht-flüchtige Speicherzelle
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6369422B1 (en) 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6583007B1 (en) * 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6700818B2 (en) * 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7178004B2 (en) * 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) * 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7484329B2 (en) 2003-11-20 2009-02-03 Seaweed Bio-Technology Inc. Technology for cultivation of Porphyra and other seaweeds in land-based sea water ponds
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) * 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US20060068551A1 (en) * 2004-09-27 2006-03-30 Saifun Semiconductors, Ltd. Method for embedding NROM
US7638850B2 (en) * 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US20060146624A1 (en) * 2004-12-02 2006-07-06 Saifun Semiconductors, Ltd. Current folding sense amplifier
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (de) * 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Teil-Löschüberprüfung
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US20070141788A1 (en) * 2005-05-25 2007-06-21 Ilan Bloom Method for embedding non-volatile memory with logic circuitry
JP2007027760A (ja) * 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US20070096199A1 (en) * 2005-09-08 2007-05-03 Eli Lusky Method of manufacturing symmetric arrays
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US20070087503A1 (en) * 2005-10-17 2007-04-19 Saifun Semiconductors, Ltd. Improving NROM device characteristics using adjusted gate work function
US20070120180A1 (en) * 2005-11-25 2007-05-31 Boaz Eitan Transition areas for dense memory arrays
US7352627B2 (en) * 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) * 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US20070173017A1 (en) * 2006-01-20 2007-07-26 Saifun Semiconductors, Ltd. Advanced non-volatile memory array and method of fabrication thereof
US7692961B2 (en) * 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) * 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) * 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) * 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
JP5773539B2 (ja) 2010-06-04 2015-09-02 株式会社シンク・ラボラトリー レーザ製版用レーザ露光方法
JP6002160B2 (ja) 2012-02-07 2016-10-05 株式会社シンク・ラボラトリー グラビア製版ロールのペーパー研磨方法及びペーパー研磨装置

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US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit
US4203158A (en) * 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
US4377818A (en) * 1978-11-02 1983-03-22 Texas Instruments Incorporated High density electrically programmable ROM
US4375087C1 (en) * 1980-04-09 2002-01-01 Hughes Aircraft Co Electrically erasable programmable read-only memory
US4477825A (en) * 1981-12-28 1984-10-16 National Semiconductor Corporation Electrically programmable and erasable memory cell
DE3481667D1 (de) * 1983-08-29 1990-04-19 Seeq Technology Inc Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung.
US4822750A (en) * 1983-08-29 1989-04-18 Seeq Technology, Inc. MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide
JPS60161673A (ja) * 1984-02-02 1985-08-23 Toshiba Corp 不揮発性半導体メモリ
DE3576245D1 (de) * 1984-05-17 1990-04-05 Toshiba Kawasaki Kk Verfahren zur herstellung eines nichtfluechtigen halbleiter-eeprom-elementes.
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US5008721A (en) * 1988-07-15 1991-04-16 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel
FR2638285B1 (fr) * 1988-10-25 1992-06-19 Commissariat Energie Atomique Circuit integre a haute densite d'integration tel que memoire eprom et procede d'obtention correspondant
JPH081933B2 (ja) * 1989-12-11 1996-01-10 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
JPH05508262A (ja) 1993-11-18
WO1992010002A1 (en) 1992-06-11
EP0511370B1 (de) 1998-09-09
EP0511370A4 (en) 1993-04-21
KR920704358A (ko) 1992-12-19
JP3129438B2 (ja) 2001-01-29
KR100193551B1 (ko) 1999-07-01
DE69130163T2 (de) 1999-05-20
DE69130163D1 (de) 1998-10-15
US5086325A (en) 1992-02-04
EP0511370A1 (de) 1992-11-04

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Legal Events

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