ATE173100T1 - Verfahren und system um einen unabhängige zugriff auf zwischenspeicherpuffern in einem superskalaren prozessorsystem zu gewährleisten. - Google Patents

Verfahren und system um einen unabhängige zugriff auf zwischenspeicherpuffern in einem superskalaren prozessorsystem zu gewährleisten.

Info

Publication number
ATE173100T1
ATE173100T1 AT93120933T AT93120933T ATE173100T1 AT E173100 T1 ATE173100 T1 AT E173100T1 AT 93120933 T AT93120933 T AT 93120933T AT 93120933 T AT93120933 T AT 93120933T AT E173100 T1 ATE173100 T1 AT E173100T1
Authority
AT
Austria
Prior art keywords
storage buffer
instruction
general purpose
superscalar processor
purpose register
Prior art date
Application number
AT93120933T
Other languages
English (en)
Inventor
Chin-Cheng Kau
Aubrey D Ogden
Donald E Waldecker
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE173100T1 publication Critical patent/ATE173100T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
AT93120933T 1993-01-08 1993-12-27 Verfahren und system um einen unabhängige zugriff auf zwischenspeicherpuffern in einem superskalaren prozessorsystem zu gewährleisten. ATE173100T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US187293A 1993-01-08 1993-01-08

Publications (1)

Publication Number Publication Date
ATE173100T1 true ATE173100T1 (de) 1998-11-15

Family

ID=21698213

Family Applications (1)

Application Number Title Priority Date Filing Date
AT93120933T ATE173100T1 (de) 1993-01-08 1993-12-27 Verfahren und system um einen unabhängige zugriff auf zwischenspeicherpuffern in einem superskalaren prozessorsystem zu gewährleisten.

Country Status (9)

Country Link
US (1) US5491829A (de)
EP (1) EP0605868B1 (de)
JP (1) JP2777535B2 (de)
KR (1) KR0122528B1 (de)
CN (1) CN1042863C (de)
AT (1) ATE173100T1 (de)
CA (1) CA2112995A1 (de)
DE (1) DE69321929T2 (de)
TW (1) TW230807B (de)

Families Citing this family (25)

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TW242673B (de) * 1993-08-18 1995-03-11 Ibm
US6378062B1 (en) * 1994-01-04 2002-04-23 Intel Corporation Method and apparatus for performing a store operation
CN1094610C (zh) 1994-12-02 2002-11-20 英特尔公司 可以对复合操作数进行压缩操作和拆开操作的微处理器
FR2731094B1 (fr) * 1995-02-23 1997-04-30 Dufal Frederic Procede et dispositif de commande simultanee des etats de controle des unites d'execution d'un processeur programmable
JP2636789B2 (ja) * 1995-03-31 1997-07-30 日本電気株式会社 マイクロプロセッサ
US5974240A (en) * 1995-06-07 1999-10-26 International Business Machines Corporation Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution
US5875294A (en) 1995-06-30 1999-02-23 International Business Machines Corporation Method and system for halting processor execution in response to an enumerated occurrence of a selected combination of internal states
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5764970A (en) * 1995-11-20 1998-06-09 International Business Machines Corporation Method and apparatus for supporting speculative branch and link/branch on count instructions
US6792523B1 (en) 1995-12-19 2004-09-14 Intel Corporation Processor with instructions that operate on different data types stored in the same single logical register file
US5940859A (en) 1995-12-19 1999-08-17 Intel Corporation Emptying packed data state during execution of packed data instructions
US5852726A (en) * 1995-12-19 1998-12-22 Intel Corporation Method and apparatus for executing two types of instructions that specify registers of a shared logical register file in a stack and a non-stack referenced manner
US5701508A (en) 1995-12-19 1997-12-23 Intel Corporation Executing different instructions that cause different data type operations to be performed on single logical register file
US5845149A (en) * 1996-04-10 1998-12-01 Allen Bradley Company, Llc Industrial controller with I/O mapping table for linking software addresses to physical network addresses
US6298435B1 (en) * 1996-04-16 2001-10-02 International Business Machines Corporation Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor
US5870616A (en) * 1996-10-04 1999-02-09 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5805907A (en) * 1996-10-04 1998-09-08 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US5765017A (en) * 1997-01-13 1998-06-09 International Business Machines Corporation Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers
US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US5875326A (en) * 1997-04-25 1999-02-23 International Business Machines Corporation Data processing system and method for completing out-of-order instructions
JP2001092657A (ja) * 1999-09-22 2001-04-06 Toshiba Corp 中央演算装置、コンパイル方法、及びコンパイルプログラムを記録した記録媒体
US7039060B2 (en) * 2001-03-07 2006-05-02 Mips Tech Inc System and method for extracting fields from packets having fields spread over more than one register
US6826704B1 (en) * 2001-03-08 2004-11-30 Advanced Micro Devices, Inc. Microprocessor employing a performance throttling mechanism for power management
US7330988B2 (en) * 2004-06-30 2008-02-12 Sun Microsystems, Inc. Method and apparatus for power throttling in a multi-thread processor
CN100576169C (zh) * 2007-07-11 2009-12-30 凌阳科技股份有限公司 一种执行指令的方法及系统

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JPS581246A (ja) * 1981-06-26 1983-01-06 Fujitsu Ltd 命令処理順序制御方式
JPS58178464A (ja) * 1982-04-14 1983-10-19 Hitachi Ltd 並列演算処理装置
US4594660A (en) * 1982-10-13 1986-06-10 Honeywell Information Systems Inc. Collector
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
WO1990010267A1 (en) * 1989-02-24 1990-09-07 Nexgen Microsystems Distributed pipeline control for a computer
JP2825906B2 (ja) * 1990-02-01 1998-11-18 株式会社日立製作所 計算機システム
US5237694A (en) * 1991-05-30 1993-08-17 Advanced Micro Devices, Inc. Processing system and method including lock buffer for controlling exclusive critical problem accesses by each processor
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
US5416913A (en) * 1992-07-27 1995-05-16 Intel Corporation Method and apparatus for dependency checking in a multi-pipelined microprocessor
US5367650A (en) * 1992-07-31 1994-11-22 Intel Corporation Method and apparauts for parallel exchange operation in a pipelined processor

Also Published As

Publication number Publication date
DE69321929T2 (de) 1999-07-01
DE69321929D1 (de) 1998-12-10
US5491829A (en) 1996-02-13
EP0605868B1 (de) 1998-11-04
CA2112995A1 (en) 1994-07-09
JP2777535B2 (ja) 1998-07-16
KR940018757A (ko) 1994-08-18
CN1092189A (zh) 1994-09-14
TW230807B (de) 1994-09-21
KR0122528B1 (ko) 1997-11-20
CN1042863C (zh) 1999-04-07
EP0605868A1 (de) 1994-07-13
JPH06242955A (ja) 1994-09-02

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