ATE176534T1 - Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem - Google Patents

Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem

Info

Publication number
ATE176534T1
ATE176534T1 AT92910069T AT92910069T ATE176534T1 AT E176534 T1 ATE176534 T1 AT E176534T1 AT 92910069 T AT92910069 T AT 92910069T AT 92910069 T AT92910069 T AT 92910069T AT E176534 T1 ATE176534 T1 AT E176534T1
Authority
AT
Austria
Prior art keywords
cache
processor
addresses
stream
pct
Prior art date
Application number
AT92910069T
Other languages
English (en)
Inventor
Erik Hagersten
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE176534T1 publication Critical patent/ATE176534T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Communication Control (AREA)
AT92910069T 1991-05-02 1992-04-29 Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem ATE176534T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9101325A SE469402B (sv) 1991-05-02 1991-05-02 Foerfarande foer att haemta data till ett cache-minne

Publications (1)

Publication Number Publication Date
ATE176534T1 true ATE176534T1 (de) 1999-02-15

Family

ID=20382624

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92910069T ATE176534T1 (de) 1991-05-02 1992-04-29 Verfahren zur erhöhung der datenverarbeitungsgeschwindigkeit in einem rechnersystem

Country Status (8)

Country Link
US (2) US5802566A (de)
EP (1) EP0582635B1 (de)
JP (1) JPH06510611A (de)
KR (1) KR100277818B1 (de)
AT (1) ATE176534T1 (de)
DE (1) DE69228380T2 (de)
SE (1) SE469402B (de)
WO (1) WO1992020027A1 (de)

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US5809529A (en) * 1995-08-23 1998-09-15 International Business Machines Corporation Prefetching of committed instructions from a memory to an instruction cache
US5664147A (en) * 1995-08-24 1997-09-02 International Business Machines Corp. System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated
US5737565A (en) * 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US6029226A (en) * 1996-09-30 2000-02-22 Lsi Logic Corporation Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command
DE19747275A1 (de) * 1997-10-25 1999-04-29 Philips Patentverwaltung Mobilfunkgerät mit einem Steuersignalgenerator
JP3071752B2 (ja) 1998-03-24 2000-07-31 三菱電機株式会社 ブリッジ方法、バスブリッジ及びマルチプロセッサシステム
US6430680B1 (en) * 1998-03-31 2002-08-06 International Business Machines Corporation Processor and method of prefetching data based upon a detected stride
TW501011B (en) * 1998-05-08 2002-09-01 Koninkl Philips Electronics Nv Data processing circuit with cache memory
JP3439350B2 (ja) * 1998-10-02 2003-08-25 Ｎｅｃエレクトロニクス株式会社 キャッシュ・メモリ制御方法及びキャッシュ・メモリ制御装置
US6463509B1 (en) * 1999-01-26 2002-10-08 Motive Power, Inc. Preloading data in a cache memory according to user-specified preload criteria
US6370614B1 (en) 1999-01-26 2002-04-09 Motive Power, Inc. I/O cache with user configurable preload
US6449697B1 (en) 1999-04-23 2002-09-10 International Business Machines Corporation Prestaging data into cache in preparation for data transfer operations
US6622212B1 (en) * 1999-05-24 2003-09-16 Intel Corp. Adaptive prefetch of I/O data blocks
US6470427B1 (en) 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
US6567894B1 (en) 1999-12-08 2003-05-20 International Business Machines Corporation Method and apparatus to prefetch sequential pages in a multi-stream environment
US6628294B1 (en) 1999-12-31 2003-09-30 Intel Corporation Prefetching of virtual-to-physical address translation for display data
JP4341186B2 (ja) 2001-01-22 2009-10-07 株式会社日立製作所 メモリシステム
US6571318B1 (en) * 2001-03-02 2003-05-27 Advanced Micro Devices, Inc. Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism
JP3969009B2 (ja) * 2001-03-29 2007-08-29 株式会社日立製作所 ハードウェアプリフェッチシステム
WO2003025755A2 (en) * 2001-09-14 2003-03-27 Seagate Technology Llc sETHOD AND SYSTEM FOR CACHE MANAGEMENT ALGORITHM SELECTION
US6760818B2 (en) 2002-05-01 2004-07-06 Koninklijke Philips Electronics N.V. Memory region based data pre-fetching
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP4532931B2 (ja) * 2004-02-25 2010-08-25 株式会社日立製作所 プロセッサ、および、プリフェッチ制御方法
EP1610323A1 (de) * 2004-06-22 2005-12-28 Koninklijke Philips Electronics N.V. Defektmanagement auf Dateiebene
US7418531B2 (en) * 2005-05-04 2008-08-26 Pillar Data Systems, Inc. Quality of service for data storage volumes
US7457923B1 (en) * 2005-05-11 2008-11-25 Sun Microsystems, Inc. Method and structure for correlation-based prefetching
US20060294315A1 (en) * 2005-06-27 2006-12-28 Seagate Technology Llc Object-based pre-fetching Mechanism for disc drives
US8612956B2 (en) * 2007-12-05 2013-12-17 International Business Machines Corporation Efficient object profiling for optimizing object locality
US8918588B2 (en) * 2009-04-07 2014-12-23 International Business Machines Corporation Maintaining a cache of blocks from a plurality of data streams
US8566496B2 (en) * 2010-12-03 2013-10-22 Lsi Corporation Data prefetch in SAS expanders
US10642502B2 (en) 2018-06-29 2020-05-05 Western Digital Technologies, Inc. System and method for prediction of read commands to non-sequential data
US10649776B2 (en) 2018-06-29 2020-05-12 Western Digital Technologies, Inc. System and method for prediction of multiple read commands directed to non-sequential data
US10489305B1 (en) 2018-08-14 2019-11-26 Texas Instruments Incorporated Prefetch kill and revival in an instruction cache
US10642742B2 (en) 2018-08-14 2020-05-05 Texas Instruments Incorporated Prefetch management in a hierarchical cache system
US10896131B2 (en) 2019-01-28 2021-01-19 Western Digital Technologies, Inc. System and method for configuring a storage device based on prediction of host source
US10846226B2 (en) 2019-01-28 2020-11-24 Western Digital Technologies, Inc. System and method for prediction of random read commands in virtualized multi-queue memory systems
US10725781B1 (en) 2019-02-28 2020-07-28 Western Digital Technologies, Inc. System and method for chain prediction of multiple read commands
US10719445B1 (en) 2019-02-28 2020-07-21 Western Digital Technologies, Inc. System and method for scaling a historical pattern matching data structure in a memory device
US11055022B2 (en) 2019-03-25 2021-07-06 Western Digital Technologies, Inc. Storage system and method for early host command fetching in a low queue depth environment
US11010299B2 (en) 2019-05-20 2021-05-18 Western Digital Technologies, Inc. System and method for performing discriminative predictive read
US11416263B1 (en) 2021-02-12 2022-08-16 Western Digital Technologies, Inc. Boosted boot procedure by background re-arrangement of read patterns

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US4262332A (en) * 1978-12-28 1981-04-14 International Business Machines Corporation Command pair to improve performance and device independence
US4468730A (en) * 1981-11-27 1984-08-28 Storage Technology Corporation Detection of sequential data stream for improvements in cache data storage
US5093777A (en) * 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
US5233702A (en) * 1989-08-07 1993-08-03 International Business Machines Corporation Cache miss facility with stored sequences for data fetching
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5357618A (en) * 1991-04-15 1994-10-18 International Business Machines Corporation Cache prefetch and bypass using stride registers
US5305389A (en) * 1991-08-30 1994-04-19 Digital Equipment Corporation Predictive cache system
US5367656A (en) * 1992-03-13 1994-11-22 Bull Hn Information Systems Inc. Controlling cache predictive prefetching based on cache hit ratio trend
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor

Also Published As

Publication number Publication date
EP0582635B1 (de) 1999-02-03
SE469402B (sv) 1993-06-28
SE9101325L (sv) 1992-11-03
SE9101325D0 (sv) 1991-05-02
WO1992020027A1 (en) 1992-11-12
DE69228380T2 (de) 1999-08-26
EP0582635A1 (de) 1994-02-16
US6078996A (en) 2000-06-20
KR100277818B1 (ko) 2001-01-15
DE69228380D1 (de) 1999-03-18
JPH06510611A (ja) 1994-11-24
US5802566A (en) 1998-09-01

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