ATE187015T1 - Niedrige dielektrizitätskonstanten- schichtentechnik - Google Patents

Niedrige dielektrizitätskonstanten- schichtentechnik

Info

Publication number
ATE187015T1
ATE187015T1 AT95935248T AT95935248T ATE187015T1 AT E187015 T1 ATE187015 T1 AT E187015T1 AT 95935248 T AT95935248 T AT 95935248T AT 95935248 T AT95935248 T AT 95935248T AT E187015 T1 ATE187015 T1 AT E187015T1
Authority
AT
Austria
Prior art keywords
layer
metal interconnects
spin
dielectric structure
glass
Prior art date
Application number
AT95935248T
Other languages
English (en)
Inventor
Robin W Cheung
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE187015T1 publication Critical patent/ATE187015T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Inorganic Insulating Materials (AREA)
  • Organic Insulating Materials (AREA)
  • Local Oxidation Of Silicon (AREA)
AT95935248T 1994-10-28 1995-09-29 Niedrige dielektrizitätskonstanten- schichtentechnik ATE187015T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/330,871 US5534731A (en) 1994-10-28 1994-10-28 Layered low dielectric constant technology

Publications (1)

Publication Number Publication Date
ATE187015T1 true ATE187015T1 (de) 1999-12-15

Family

ID=23291661

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95935248T ATE187015T1 (de) 1994-10-28 1995-09-29 Niedrige dielektrizitätskonstanten- schichtentechnik

Country Status (8)

Country Link
US (2) US5534731A (de)
EP (1) EP0737362B1 (de)
JP (1) JPH09507617A (de)
KR (1) KR100392900B1 (de)
AT (1) ATE187015T1 (de)
DE (1) DE69513501T2 (de)
TW (1) TW260824B (de)
WO (1) WO1996013856A1 (de)

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TWI579916B (zh) * 2009-12-09 2017-04-21 諾菲勒斯系統公司 整合可流動氧化物及頂蓋氧化物之新穎間隙填充
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Also Published As

Publication number Publication date
US5534731A (en) 1996-07-09
EP0737362B1 (de) 1999-11-24
EP0737362A1 (de) 1996-10-16
DE69513501T2 (de) 2000-06-29
KR100392900B1 (ko) 2003-11-17
TW260824B (en) 1995-10-21
JPH09507617A (ja) 1997-07-29
KR970700375A (ko) 1997-01-08
WO1996013856A1 (en) 1996-05-09
DE69513501D1 (de) 1999-12-30
US5693566A (en) 1997-12-02

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