ATE193387T1 - Multiplexer und integrierter prozessor mit einem solchen multiplexer - Google Patents

Multiplexer und integrierter prozessor mit einem solchen multiplexer

Info

Publication number
ATE193387T1
ATE193387T1 AT95306666T AT95306666T ATE193387T1 AT E193387 T1 ATE193387 T1 AT E193387T1 AT 95306666 T AT95306666 T AT 95306666T AT 95306666 T AT95306666 T AT 95306666T AT E193387 T1 ATE193387 T1 AT E193387T1
Authority
AT
Austria
Prior art keywords
integrated processor
clock
intensive
various subsystems
clock signals
Prior art date
Application number
AT95306666T
Other languages
English (en)
Inventor
Gary Baum
Michael S Quimby
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE193387T1 publication Critical patent/ATE193387T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Microcomputers (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
AT95306666T 1994-10-19 1995-09-21 Multiplexer und integrierter prozessor mit einem solchen multiplexer ATE193387T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/325,906 US5596765A (en) 1994-10-19 1994-10-19 Integrated processor including a device for multiplexing external pin signals

Publications (1)

Publication Number Publication Date
ATE193387T1 true ATE193387T1 (de) 2000-06-15

Family

ID=23269972

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95306666T ATE193387T1 (de) 1994-10-19 1995-09-21 Multiplexer und integrierter prozessor mit einem solchen multiplexer

Country Status (6)

Country Link
US (1) US5596765A (de)
EP (1) EP0708405B1 (de)
JP (1) JP3919246B2 (de)
KR (1) KR100385155B1 (de)
AT (1) ATE193387T1 (de)
DE (1) DE69517123T2 (de)

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EP0562151B1 (de) * 1992-03-27 1998-12-23 Siemens Aktiengesellschaft Integrierter Mikroprozessor
JP3904244B2 (ja) * 1993-09-17 2007-04-11 株式会社ルネサステクノロジ シングル・チップ・データ処理装置
US5752077A (en) * 1995-05-15 1998-05-12 Motorola, Inc. Data processing system having a multi-function input/output port with individual pull-up and pull-down control
US5805923A (en) * 1995-05-26 1998-09-08 Sony Corporation Configurable power management system having a clock stabilization filter that can be enabled or bypassed depending upon whether a crystal or can oscillator is used
US5838995A (en) * 1995-12-18 1998-11-17 International Business Machines Corporation System and method for high frequency operation of I/O bus
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
JPH10301661A (ja) * 1997-04-23 1998-11-13 Matsushita Electric Ind Co Ltd クロック供給装置
US6073225A (en) * 1997-06-24 2000-06-06 Intel Corporation Method and apparatus for monitoring bus transactions based on cycle type and memory address range
US6134675A (en) * 1998-01-14 2000-10-17 Motorola Inc. Method of testing multi-core processors and multi-core processor testing device
US6052746A (en) * 1998-04-14 2000-04-18 Motorola, Inc. Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset
WO2000028406A2 (en) 1998-11-08 2000-05-18 Cirrus Logic, Inc. Mixed-signal single-chip integrated system electronics for magnetic hard disk drives
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6310570B1 (en) * 1999-06-04 2001-10-30 Thomson Licensing S.A. System with adjustable ADC clock phase
US6457100B1 (en) 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
DE60034581T2 (de) 1999-09-15 2008-01-31 Thomson Licensing Multi-takt ic mit taktgenerator mit bidirektionneller taktanschlussanordnung
US6567866B1 (en) * 1999-12-30 2003-05-20 Intel Corporation Selecting multiple functions using configuration mechanism
US7395447B2 (en) * 2002-09-16 2008-07-01 Silicon Labs Cp, Inc. Precision oscillator for an asynchronous transmission system
US6917658B2 (en) * 2002-09-16 2005-07-12 Silicon Labs Cp, Inc. Clock recovery method for bursty communications
KR100596605B1 (ko) * 2003-11-12 2006-07-03 (주)세솔 아이오 확장 기술
US7368958B2 (en) * 2006-01-27 2008-05-06 International Business Machines Corporation Methods and systems for locally generating non-integral divided clocks with centralized state machines
US7319348B2 (en) * 2006-01-27 2008-01-15 International Business Machines Corporation Circuits for locally generating non-integral divided clocks with centralized state machines
US7355460B2 (en) * 2006-01-27 2008-04-08 International Business Machines Corporation Method for locally generating non-integral divided clocks with centralized state machines
US8127275B1 (en) * 2007-04-18 2012-02-28 Parasoft Corporation System and method for recording the state of variables and objects when running unit tests
US10817043B2 (en) * 2011-07-26 2020-10-27 Nvidia Corporation System and method for entering and exiting sleep mode in a graphics subsystem
CN111581150B (zh) * 2020-04-27 2022-12-27 希翼微电子(嘉兴)有限公司 Mcu中gpio功能可重构方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6039237A (ja) * 1983-08-12 1985-03-01 Hitachi Ltd 半導体集積回路装置
US5175841A (en) * 1987-03-13 1992-12-29 Texas Instruments Incorporated Data processing device with multiple on-chip memory buses
JPH0290382A (ja) * 1988-09-28 1990-03-29 Hitachi Ltd 半導体集積回路
US5070449A (en) * 1988-12-19 1991-12-03 Honeywell Inc. Bus interface controller for computer graphics
US5450557A (en) * 1989-11-07 1995-09-12 Loral Aerospace Corp. Single-chip self-configurable parallel processor
US5276833A (en) * 1990-07-02 1994-01-04 Chips And Technologies, Inc. Data cache management system with test mode using index registers and CAS disable and posted write disable
US5241631A (en) * 1991-08-23 1993-08-31 Nec Technologies, Inc. Personal computer having a local bus interface to a video circuit
US5309568A (en) * 1992-03-16 1994-05-03 Opti, Inc. Local bus design
JPH05324860A (ja) * 1992-05-27 1993-12-10 Nec Corp シングルチップマイクロコンピュータ
US5448703A (en) * 1993-05-28 1995-09-05 International Business Machines Corporation Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
US5495422A (en) * 1993-10-12 1996-02-27 Wang Laboratories, Inc. Method for combining a plurality of independently operating circuits within a single package

Also Published As

Publication number Publication date
EP0708405B1 (de) 2000-05-24
JPH08292936A (ja) 1996-11-05
KR960015205A (ko) 1996-05-22
DE69517123D1 (de) 2000-06-29
US5596765A (en) 1997-01-21
KR100385155B1 (ko) 2004-02-25
JP3919246B2 (ja) 2007-05-23
EP0708405A1 (de) 1996-04-24
DE69517123T2 (de) 2001-01-25

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