ATE196215T1 - Verfahren zur herstellung integrierter schaltungen unter verwendung einer schicht gegen der diffusion von sauerstoff - Google Patents

Verfahren zur herstellung integrierter schaltungen unter verwendung einer schicht gegen der diffusion von sauerstoff

Info

Publication number
ATE196215T1
ATE196215T1 AT86310234T AT86310234T ATE196215T1 AT E196215 T1 ATE196215 T1 AT E196215T1 AT 86310234 T AT86310234 T AT 86310234T AT 86310234 T AT86310234 T AT 86310234T AT E196215 T1 ATE196215 T1 AT E196215T1
Authority
AT
Austria
Prior art keywords
oxidation
poly
layer
nitride
substrate
Prior art date
Application number
AT86310234T
Other languages
English (en)
Inventor
Yung-Chau Yen
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE196215T1 publication Critical patent/ATE196215T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6316—Formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0142—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations the dielectric materials being chemical transformed from non-dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments

Landscapes

  • Formation Of Insulating Films (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Solid-Phase Diffusion Into Metallic Material Surfaces (AREA)
  • Chemical Vapour Deposition (AREA)
AT86310234T 1986-01-08 1986-12-31 Verfahren zur herstellung integrierter schaltungen unter verwendung einer schicht gegen der diffusion von sauerstoff ATE196215T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/817,233 US4789560A (en) 1986-01-08 1986-01-08 Diffusion stop method for forming silicon oxide during the fabrication of IC devices

Publications (1)

Publication Number Publication Date
ATE196215T1 true ATE196215T1 (de) 2000-09-15

Family

ID=25222635

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86310234T ATE196215T1 (de) 1986-01-08 1986-12-31 Verfahren zur herstellung integrierter schaltungen unter verwendung einer schicht gegen der diffusion von sauerstoff

Country Status (5)

Country Link
US (1) US4789560A (de)
EP (1) EP0237684B1 (de)
JP (1) JP2673183B2 (de)
AT (1) ATE196215T1 (de)
DE (1) DE3650747T2 (de)

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US4666556A (en) * 1986-05-12 1987-05-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JP2672537B2 (ja) * 1987-12-21 1997-11-05 株式会社東芝 不揮発性半導体装置の製造方法
US5123994A (en) * 1989-05-30 1992-06-23 Motorola, Inc. Ramped oxide formation method
US5213670A (en) * 1989-06-30 1993-05-25 Siemens Aktiengesellschaft Method for manufacturing a polycrystalline layer on a substrate
JP2722873B2 (ja) * 1991-07-29 1998-03-09 日本電気株式会社 半導体装置およびその製造方法
US5169491A (en) * 1991-07-29 1992-12-08 Micron Technology, Inc. Method of etching SiO2 dielectric layers using chemical mechanical polishing techniques
JPH06502026A (ja) * 1991-08-19 1994-03-03 イーストマン コダック カンパニー 低酸素透過率を有する写真用紙
US5880036A (en) * 1992-06-15 1999-03-09 Micron Technology, Inc. Method for enhancing oxide to nitride selectivity through the use of independent heat control
US5286344A (en) * 1992-06-15 1994-02-15 Micron Technology, Inc. Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride
JP3396553B2 (ja) * 1994-02-04 2003-04-14 三菱電機株式会社 半導体装置の製造方法及び半導体装置
JP3045946B2 (ja) * 1994-05-09 2000-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスの製造方法
US6306727B1 (en) * 1997-08-18 2001-10-23 Micron Technology, Inc. Advanced isolation process for large memory arrays
US7192829B2 (en) 1998-07-17 2007-03-20 Micron Technology, Inc. Methods of forming floating gate transistors
JP2001093996A (ja) * 1999-09-27 2001-04-06 Toshiba Corp 半導体装置の製造方法
EP1150350A3 (de) * 2000-02-25 2002-04-24 Infineon Technologies North America Corp. Herstellung eines Grabenkondensators
DE10056261A1 (de) * 2000-11-14 2002-05-29 Infineon Technologies Ag Verfahren zur Herstellung eines integrierten Halbleiter-Bauelements
US20030107111A1 (en) * 2001-12-10 2003-06-12 International Business Machines Corporation A 3-d microelectronic structure including a vertical thermal nitride mask
JPWO2006006369A1 (ja) * 2004-07-12 2008-04-24 パイオニア株式会社 半導体装置
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7285812B2 (en) * 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
US7229895B2 (en) * 2005-01-14 2007-06-12 Micron Technology, Inc Memory array buried digit line
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
JP5032056B2 (ja) * 2005-07-25 2012-09-26 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US9401363B2 (en) 2011-08-23 2016-07-26 Micron Technology, Inc. Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
JP5829196B2 (ja) 2011-10-28 2015-12-09 東京エレクトロン株式会社 シリコン酸化物膜の成膜方法
KR101452091B1 (ko) 2013-02-26 2014-10-16 삼성전기주식회사 전력 반도체 소자 및 그 제조 방법
KR101452098B1 (ko) * 2013-03-29 2014-10-16 삼성전기주식회사 전력 반도체 소자 및 그 제조 방법
TWI769797B (zh) * 2021-04-27 2022-07-01 華邦電子股份有限公司 動態隨機存取記憶體及其製造法方法

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Also Published As

Publication number Publication date
EP0237684B1 (de) 2000-09-06
EP0237684A3 (de) 1991-01-09
JP2673183B2 (ja) 1997-11-05
EP0237684A2 (de) 1987-09-23
DE3650747D1 (de) 2000-11-16
DE3650747T2 (de) 2001-04-26
JPS62177931A (ja) 1987-08-04
US4789560A (en) 1988-12-06

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