ATE198381T1 - Verfahren zu grosser logischer adressierung - Google Patents

Verfahren zu grosser logischer adressierung

Info

Publication number
ATE198381T1
ATE198381T1 AT92118610T AT92118610T ATE198381T1 AT E198381 T1 ATE198381 T1 AT E198381T1 AT 92118610 T AT92118610 T AT 92118610T AT 92118610 T AT92118610 T AT 92118610T AT E198381 T1 ATE198381 T1 AT E198381T1
Authority
AT
Austria
Prior art keywords
lvas
address
dat
lva
ales
Prior art date
Application number
AT92118610T
Other languages
English (en)
Inventor
Richard Irwin Baum
Kenneth Ernest Plambeck
Casper Anthony Scalzi
Richard John Schmalz
Bhaskar Sinha
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE198381T1 publication Critical patent/ATE198381T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Logic Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
AT92118610T 1991-12-06 1992-10-30 Verfahren zu grosser logischer adressierung ATE198381T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/803,320 US5381537A (en) 1991-12-06 1991-12-06 Large logical addressing method and means

Publications (1)

Publication Number Publication Date
ATE198381T1 true ATE198381T1 (de) 2001-01-15

Family

ID=25186222

Family Applications (1)

Application Number Title Priority Date Filing Date
AT92118610T ATE198381T1 (de) 1991-12-06 1992-10-30 Verfahren zu grosser logischer adressierung

Country Status (5)

Country Link
US (1) US5381537A (de)
EP (1) EP0545076B1 (de)
JP (1) JPH07104818B2 (de)
AT (1) ATE198381T1 (de)
DE (1) DE69231611T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5826057A (en) * 1992-01-16 1998-10-20 Kabushiki Kaisha Toshiba Method for managing virtual address space at improved space utilization efficiency
US5479631A (en) * 1992-11-19 1995-12-26 International Business Machines Corporation System for designating real main storage addresses in instructions while dynamic address translation is on
US5548746A (en) * 1993-11-12 1996-08-20 International Business Machines Corporation Non-contiguous mapping of I/O addresses to use page protection of a process
US5606683A (en) * 1994-01-28 1997-02-25 Quantum Effect Design, Inc. Structure and method for virtual-to-physical address translation in a translation lookaside buffer
US5655139A (en) * 1995-05-26 1997-08-05 National Semiconductor Corporation Execution unit architecture to support X86 instruction set and X86 segmented addressing
JPH0934748A (ja) * 1995-07-17 1997-02-07 Mitsubishi Electric Corp エミュレーション用マイクロコンピュータ
US5732404A (en) * 1996-03-29 1998-03-24 Unisys Corporation Flexible expansion of virtual memory addressing
US5956754A (en) * 1997-03-03 1999-09-21 Data General Corporation Dynamic shared user-mode mapping of shared memory
US5940868A (en) * 1997-07-18 1999-08-17 Digital Equipment Corporation Large memory allocation method and apparatus
US6192463B1 (en) * 1997-10-07 2001-02-20 Microchip Technology, Inc. Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor
US6349380B1 (en) * 1999-03-12 2002-02-19 Intel Corporation Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
US6502181B1 (en) 1999-09-17 2002-12-31 Zilog, Inc. Method and apparatus for an enhanced processor
US7124286B2 (en) 2000-01-14 2006-10-17 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US6560694B1 (en) 2000-01-14 2003-05-06 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
US6973562B1 (en) * 2000-01-14 2005-12-06 Advanced Micro Devices, Inc. Establishing an operating mode in a processor
US6571330B1 (en) 2000-01-14 2003-05-27 Advanced Micro Devices, Inc. Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor
US6715063B1 (en) 2000-01-14 2004-03-30 Advanced Micro Devices, Inc. Call gate expansion for 64 bit addressing
US6877158B1 (en) * 2000-06-08 2005-04-05 International Business Machines Corporation Logical partitioning via hypervisor mediated address translation
US6807622B1 (en) * 2000-08-09 2004-10-19 Advanced Micro Devices, Inc. Processor which overrides default operand size for implicit stack pointer references and near branches
US7058791B1 (en) 2000-08-09 2006-06-06 Advanced Micro Devices, Inc. Establishing a mode indication responsive to two or more indications
US7100028B2 (en) * 2000-08-09 2006-08-29 Advanced Micro Devices, Inc. Multiple entry points for system call instructions
US6779049B2 (en) * 2000-12-14 2004-08-17 International Business Machines Corporation Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism
US6807617B2 (en) 2001-04-02 2004-10-19 Advanced Micro Devices, Inc. Processor, method and apparatus with descriptor table storing segment descriptors of varying size
US6711663B2 (en) * 2001-11-15 2004-03-23 Key Technology Corporation Algorithm of flash memory capable of quickly building table and preventing improper operation and control system thereof
US6704852B2 (en) * 2001-11-16 2004-03-09 Key Technology Corporation Control device applicable to flash memory card and method for building partial lookup table
US6981125B2 (en) * 2003-04-22 2005-12-27 International Business Machines Corporation Method and apparatus for managing shared virtual storage in an information handling system
US10365858B2 (en) 2013-11-06 2019-07-30 Pure Storage, Inc. Thin provisioning in a storage device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400729A1 (fr) * 1977-08-17 1979-03-16 Cii Honeywell Bull Dispositif pour la transformation d'adresses virtuelles en adresses physiques dans un systeme de traitement de donnees
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
NL7807314A (nl) * 1978-07-06 1980-01-08 Philips Nv Inrichting voor het vergroten van de lengte van een logisch computeradres.
US4355355A (en) * 1980-03-19 1982-10-19 International Business Machines Corp. Address generating mechanism for multiple virtual spaces
EP0148478B1 (de) * 1983-12-23 1989-08-09 Hitachi, Ltd. Datenprozessor mit Steuerung der signifikanten Bitlänge von Allzweckregistern
JPS6184754A (ja) * 1984-10-03 1986-04-30 Hitachi Ltd 拡張アドレス変換装置
US4868740A (en) * 1986-06-04 1989-09-19 Hitachi, Ltd. System for processing data with multiple virtual address and data word lengths
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
JPH0195347A (ja) * 1987-10-08 1989-04-13 Nec Corp アドレス変換方式
CA1308202C (en) * 1988-02-10 1992-09-29 Richard I. Baum Access register translation means for address generating mechanism for multiple virtual spaces
US5023773A (en) * 1988-02-10 1991-06-11 International Business Machines Corporation Authorization for selective program access to data in multiple address spaces
US4979098A (en) * 1988-02-10 1990-12-18 International Business Machines Corporation Multiple address space token designation, protection controls, designation translation and lookaside

Also Published As

Publication number Publication date
EP0545076B1 (de) 2000-12-27
DE69231611T2 (de) 2001-07-05
JPH05233453A (ja) 1993-09-10
EP0545076A1 (de) 1993-06-09
US5381537A (en) 1995-01-10
DE69231611D1 (de) 2001-02-01
JPH07104818B2 (ja) 1995-11-13

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