ATE242508T1 - Ausnahmebehandlung in einem datenprozessor - Google Patents
Ausnahmebehandlung in einem datenprozessorInfo
- Publication number
- ATE242508T1 ATE242508T1 AT96103209T AT96103209T ATE242508T1 AT E242508 T1 ATE242508 T1 AT E242508T1 AT 96103209 T AT96103209 T AT 96103209T AT 96103209 T AT96103209 T AT 96103209T AT E242508 T1 ATE242508 T1 AT E242508T1
- Authority
- AT
- Austria
- Prior art keywords
- instruction
- register
- physical
- logical
- registers
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Retry When Errors Occur (AREA)
- Exchange Systems With Centralized Control (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US39789395A | 1995-03-03 | 1995-03-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE242508T1 true ATE242508T1 (de) | 2003-06-15 |
Family
ID=23573099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT96103209T ATE242508T1 (de) | 1995-03-03 | 1996-03-01 | Ausnahmebehandlung in einem datenprozessor |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5675759A (de) |
| EP (2) | EP0730225B1 (de) |
| AT (1) | ATE242508T1 (de) |
| DE (2) | DE69628480T2 (de) |
Families Citing this family (57)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100483212B1 (ko) * | 1996-03-28 | 2005-10-19 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 순차프로세서상에서데이터요소들의세트를처리하기위한방법및컴퓨터시스템 |
| US5881305A (en) * | 1996-12-13 | 1999-03-09 | Advanced Micro Devices, Inc. | Register rename stack for a microprocessor |
| US5872990A (en) * | 1997-01-07 | 1999-02-16 | International Business Machines Corporation | Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment |
| US5765017A (en) * | 1997-01-13 | 1998-06-09 | International Business Machines Corporation | Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers |
| US6314511B2 (en) * | 1997-04-03 | 2001-11-06 | University Of Washington | Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers |
| US6003126A (en) * | 1997-07-01 | 1999-12-14 | International Business Machines | Special instruction register including allocation field utilized for temporary designation of physical registers as general registers |
| US5961636A (en) * | 1997-09-22 | 1999-10-05 | International Business Machines Corporation | Checkpoint table for selective instruction flushing in a speculative execution unit |
| US6009509A (en) * | 1997-10-08 | 1999-12-28 | International Business Machines Corporation | Method and system for the temporary designation and utilization of a plurality of physical registers as a stack |
| US5974525A (en) * | 1997-12-05 | 1999-10-26 | Intel Corporation | System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized |
| US6108771A (en) * | 1997-12-19 | 2000-08-22 | International Business Machines Corporation | Register renaming with a pool of physical registers |
| US6212619B1 (en) * | 1998-05-11 | 2001-04-03 | International Business Machines Corporation | System and method for high-speed register renaming by counting |
| US6122656A (en) * | 1998-07-31 | 2000-09-19 | Advanced Micro Devices, Inc. | Processor configured to map logical register numbers to physical register numbers using virtual register numbers |
| US6230262B1 (en) | 1998-07-31 | 2001-05-08 | Advanced Micro Devices, Inc. | Processor configured to selectively free physical registers upon retirement of instructions |
| US6119223A (en) * | 1998-07-31 | 2000-09-12 | Advanced Micro Devices, Inc. | Map unit having rapid misprediction recovery |
| US6633563B1 (en) * | 1999-03-02 | 2003-10-14 | Nortel Networks Limited | Assigning cell data to one of several processors provided in a data switch |
| US6553483B1 (en) * | 1999-11-29 | 2003-04-22 | Intel Corporation | Enhanced virtual renaming scheme and deadlock prevention therefor |
| US6633970B1 (en) * | 1999-12-28 | 2003-10-14 | Intel Corporation | Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer |
| GB2403833B (en) * | 2000-02-16 | 2005-02-23 | Hewlett Packard Co | Method and apparatus for resteering failing speculation check instructions field |
| US7191315B2 (en) | 2001-06-04 | 2007-03-13 | Sun Microsystems, Inc. | Method and system for tracking and recycling physical register assignment |
| US20040064657A1 (en) * | 2002-09-27 | 2004-04-01 | Muraleedhara Navada | Memory structure including information storage elements and associated validity storage elements |
| US7117297B2 (en) * | 2003-05-23 | 2006-10-03 | Hewlett-Packard Development Company, L.P. | Method and apparatus for storing multiple entry types and ordering information using a single addressable storage array |
| TWI223756B (en) * | 2003-10-09 | 2004-11-11 | Univ Nat Sun Yat Sen | Automatic register backup/restore system and method |
| US7216219B2 (en) * | 2004-05-03 | 2007-05-08 | Sun Microsystems Inc. | Method and apparatus for avoiding write-after-read hazards in an execute-ahead processor |
| US20070204139A1 (en) | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Compact linked-list-based multi-threaded instruction graduation buffer |
| US8327115B2 (en) | 2006-04-12 | 2012-12-04 | Soft Machines, Inc. | Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode |
| US20080016326A1 (en) | 2006-07-14 | 2008-01-17 | Mips Technologies, Inc. | Latest producer tracking in an out-of-order processor, and applications thereof |
| US7370178B1 (en) * | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
| WO2008061154A2 (en) | 2006-11-14 | 2008-05-22 | Soft Machines, Inc. | Apparatus and method for processing instructions in a multi-threaded architecture using context switching |
| JP5595633B2 (ja) * | 2007-02-26 | 2014-09-24 | スパンション エルエルシー | シミュレーション方法及びシミュレーション装置 |
| TWI389026B (zh) * | 2009-06-08 | 2013-03-11 | Rdc Semiconductor Co Ltd | 暫存器更名表的回復方法與回復系統 |
| CN103250131B (zh) | 2010-09-17 | 2015-12-16 | 索夫特机械公司 | 包括用于早期远分支预测的影子缓存的单周期多分支预测 |
| KR101966712B1 (ko) | 2011-03-25 | 2019-04-09 | 인텔 코포레이션 | 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트 |
| WO2012135031A2 (en) | 2011-03-25 | 2012-10-04 | Soft Machines, Inc. | Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines |
| CN103562866B (zh) | 2011-03-25 | 2018-03-30 | 英特尔公司 | 用于通过使用由可分割引擎实例化的虚拟核来支持代码块执行的寄存器文件段 |
| US9170818B2 (en) * | 2011-04-26 | 2015-10-27 | Freescale Semiconductor, Inc. | Register renaming scheme with checkpoint repair in a processing device |
| EP2710481B1 (de) | 2011-05-20 | 2021-02-17 | Intel Corporation | Dezentralisierte zuordnung von ressourcen und verbindungsstrukturen zur unterstützung der ausführung von anweisungssequenzen durch mehrere maschinen |
| WO2012162189A1 (en) | 2011-05-20 | 2012-11-29 | Soft Machines, Inc. | An interconnect structure to support the execution of instruction sequences by a plurality of engines |
| IN2014CN03678A (de) | 2011-11-22 | 2015-09-25 | Soft Machines Inc | |
| WO2013077876A1 (en) | 2011-11-22 | 2013-05-30 | Soft Machines, Inc. | A microprocessor accelerated code optimizer |
| WO2013101194A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Selective control for commit lines for shadowing data in storage elements |
| WO2014150991A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for implementing a reduced size register view data structure in a microprocessor |
| US9811342B2 (en) | 2013-03-15 | 2017-11-07 | Intel Corporation | Method for performing dual dispatch of blocks and half blocks |
| EP2972836B1 (de) | 2013-03-15 | 2022-11-09 | Intel Corporation | Verfahren zur emulierung einer zentralisierten gast-flag-architektur mithilfe einer nativen verteilten flag-architektur |
| WO2014150971A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for dependency broadcasting through a block organized source view data structure |
| US10140138B2 (en) | 2013-03-15 | 2018-11-27 | Intel Corporation | Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation |
| US9886279B2 (en) * | 2013-03-15 | 2018-02-06 | Intel Corporation | Method for populating and instruction view data structure by using register template snapshots |
| US9569216B2 (en) | 2013-03-15 | 2017-02-14 | Soft Machines, Inc. | Method for populating a source view data structure by using register template snapshots |
| US9891924B2 (en) | 2013-03-15 | 2018-02-13 | Intel Corporation | Method for implementing a reduced size register view data structure in a microprocessor |
| WO2014151018A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for executing multithreaded instructions grouped onto blocks |
| US10275255B2 (en) | 2013-03-15 | 2019-04-30 | Intel Corporation | Method for dependency broadcasting through a source organized source view data structure |
| WO2014150806A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines, Inc. | A method for populating register view data structure by using register template snapshots |
| US9904625B2 (en) | 2013-03-15 | 2018-02-27 | Intel Corporation | Methods, systems and apparatus for predicting the way of a set associative cache |
| JP6307975B2 (ja) * | 2014-03-28 | 2018-04-11 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
| US20180203703A1 (en) * | 2017-01-13 | 2018-07-19 | Optimum Semiconductor Technologies, Inc. | Implementation of register renaming, call-return prediction and prefetch |
| US11204773B2 (en) * | 2018-09-07 | 2021-12-21 | Arm Limited | Storing a processing state based on confidence in a predicted branch outcome and a number of recent state changes |
| US10977038B2 (en) | 2019-06-19 | 2021-04-13 | Arm Limited | Checkpointing speculative register mappings |
| US20210165654A1 (en) * | 2019-12-03 | 2021-06-03 | Marvell International Ltd. | Eliminating execution of instructions that produce a constant result |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992938A (en) * | 1987-07-01 | 1991-02-12 | International Business Machines Corporation | Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers |
| US4901233A (en) * | 1987-07-20 | 1990-02-13 | International Business Machines Corporation | Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries |
| US5197132A (en) * | 1990-06-29 | 1993-03-23 | Digital Equipment Corporation | Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery |
| US5355457A (en) * | 1991-05-21 | 1994-10-11 | Motorola, Inc. | Data processor for performing simultaneous instruction retirement and backtracking |
| US5481683A (en) * | 1992-10-30 | 1996-01-02 | International Business Machines Corporation | Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions |
| US5493669A (en) * | 1993-03-03 | 1996-02-20 | Motorola, Inc. | Data processor for simultaneously searching two fields of the rename buffer having first and second most recently allogated bits |
| US5548776A (en) * | 1993-09-30 | 1996-08-20 | Intel Corporation | N-wide bypass for data dependencies within register alias table |
| US5499352A (en) * | 1993-09-30 | 1996-03-12 | Intel Corporation | Floating point register alias table FXCH and retirement floating point register array |
-
1995
- 1995-09-01 US US08/522,567 patent/US5675759A/en not_active Expired - Lifetime
-
1996
- 1996-03-01 AT AT96103209T patent/ATE242508T1/de not_active IP Right Cessation
- 1996-03-01 DE DE69628480T patent/DE69628480T2/de not_active Expired - Lifetime
- 1996-03-01 DE DE69638299T patent/DE69638299D1/de not_active Expired - Lifetime
- 1996-03-01 EP EP96103209A patent/EP0730225B1/de not_active Expired - Lifetime
- 1996-03-01 EP EP03002467A patent/EP1308837B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1308837A2 (de) | 2003-05-07 |
| DE69638299D1 (de) | 2011-01-13 |
| EP1308837A3 (de) | 2007-02-28 |
| DE69628480T2 (de) | 2004-05-06 |
| EP0730225A2 (de) | 1996-09-04 |
| EP0730225A3 (de) | 1999-12-08 |
| EP0730225B1 (de) | 2003-06-04 |
| DE69628480D1 (de) | 2003-07-10 |
| US5675759A (en) | 1997-10-07 |
| EP1308837B1 (de) | 2010-12-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |