ATE266883T1 - Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung - Google Patents

Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung

Info

Publication number
ATE266883T1
ATE266883T1 AT01000501T AT01000501T ATE266883T1 AT E266883 T1 ATE266883 T1 AT E266883T1 AT 01000501 T AT01000501 T AT 01000501T AT 01000501 T AT01000501 T AT 01000501T AT E266883 T1 ATE266883 T1 AT E266883T1
Authority
AT
Austria
Prior art keywords
interface unit
unit
host port
port interface
signal groups
Prior art date
Application number
AT01000501T
Other languages
English (en)
Inventor
Patrick J Smith
Jason A Jones
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE266883T1 publication Critical patent/ATE266883T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Selective Calling Equipment (AREA)
  • Image Input (AREA)
AT01000501T 2000-09-27 2001-09-26 Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung ATE266883T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US67066500A 2000-09-27 2000-09-27

Publications (1)

Publication Number Publication Date
ATE266883T1 true ATE266883T1 (de) 2004-05-15

Family

ID=24691340

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01000501T ATE266883T1 (de) 2000-09-27 2001-09-26 Gerät und verfahren für eine hauptrechnersportschnitstelleneinheit in einer einrichtung zur digitalen signalverarbeitung

Country Status (4)

Country Link
EP (1) EP1193606B1 (de)
JP (1) JP2002157213A (de)
AT (1) ATE266883T1 (de)
DE (1) DE60103222T2 (de)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182800A (en) * 1990-11-16 1993-01-26 International Business Machines Corporation Direct memory access controller with adaptive pipelining and bus control features
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes

Also Published As

Publication number Publication date
DE60103222D1 (de) 2004-06-17
EP1193606B1 (de) 2004-05-12
JP2002157213A (ja) 2002-05-31
EP1193606A3 (de) 2002-08-28
EP1193606A2 (de) 2002-04-03
DE60103222T2 (de) 2005-05-04

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Legal Events

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