ATE269989T1 - Verfahren und vorrichtung um den ablauf eines anwendungsprozessors in einem in gruppen angeordneten multiprozessorsystem zu initialisieren - Google Patents
Verfahren und vorrichtung um den ablauf eines anwendungsprozessors in einem in gruppen angeordneten multiprozessorsystem zu initialisierenInfo
- Publication number
- ATE269989T1 ATE269989T1 AT00950318T AT00950318T ATE269989T1 AT E269989 T1 ATE269989 T1 AT E269989T1 AT 00950318 T AT00950318 T AT 00950318T AT 00950318 T AT00950318 T AT 00950318T AT E269989 T1 ATE269989 T1 AT E269989T1
- Authority
- AT
- Austria
- Prior art keywords
- processors
- processor
- address
- application processor
- initializing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/54—Link editing before load time
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Multi Processors (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/362,388 US6687818B1 (en) | 1999-07-28 | 1999-07-28 | Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system |
| PCT/US2000/018910 WO2001009719A1 (en) | 1999-07-28 | 2000-07-12 | Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE269989T1 true ATE269989T1 (de) | 2004-07-15 |
Family
ID=23425928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT00950318T ATE269989T1 (de) | 1999-07-28 | 2000-07-12 | Verfahren und vorrichtung um den ablauf eines anwendungsprozessors in einem in gruppen angeordneten multiprozessorsystem zu initialisieren |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6687818B1 (de) |
| EP (1) | EP1200892B1 (de) |
| JP (2) | JP2003506776A (de) |
| KR (1) | KR100472391B1 (de) |
| AT (1) | ATE269989T1 (de) |
| BR (1) | BR0012777A (de) |
| DE (1) | DE60011777D1 (de) |
| WO (1) | WO2001009719A1 (de) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7065641B2 (en) * | 2002-06-13 | 2006-06-20 | Intel Corporation | Weighted processor selection apparatus and method for use in multiprocessor systems |
| US7039740B2 (en) * | 2002-07-19 | 2006-05-02 | Newisys, Inc. | Interrupt handling in systems having multiple multi-processor clusters |
| US7167908B2 (en) * | 2002-09-27 | 2007-01-23 | Intel Corporation | Facilitating operation of a multi-processor system via a resolved symbolic constant |
| US6971103B2 (en) * | 2002-10-15 | 2005-11-29 | Sandbridge Technologies, Inc. | Inter-thread communications using shared interrupt register |
| US20040083398A1 (en) * | 2002-10-29 | 2004-04-29 | Intel Corporation | Methods and apparatus for setting a bus-to-core ratio of a multi-processor platform |
| US7831974B2 (en) * | 2002-11-12 | 2010-11-09 | Intel Corporation | Method and apparatus for serialized mutual exclusion |
| US7181604B2 (en) * | 2003-02-13 | 2007-02-20 | Sun Microsystems, Inc. | Method and apparatus for configuring the boot options of a multi-domain system |
| US20060156291A1 (en) * | 2005-01-12 | 2006-07-13 | Dell Products L.P. | System and method for managing processor execution in a multiprocessor system |
| US7568063B2 (en) * | 2006-02-02 | 2009-07-28 | Hewlett-Packard Development Company, L.P. | System and method for a distributed crossbar network using a plurality of crossbars |
| US8068114B2 (en) * | 2007-04-30 | 2011-11-29 | Advanced Micro Devices, Inc. | Mechanism for granting controlled access to a shared resource |
| US7783813B2 (en) * | 2007-06-14 | 2010-08-24 | International Business Machines Corporation | Multi-node configuration of processor cards connected via processor fabrics |
| US8032681B2 (en) * | 2007-09-06 | 2011-10-04 | Intel Corporation | Processor selection for an interrupt based on willingness to accept the interrupt and on priority |
| US7627706B2 (en) * | 2007-09-06 | 2009-12-01 | Intel Corporation | Creation of logical APIC ID with cluster ID and intra-cluster ID |
| US7769938B2 (en) * | 2007-09-06 | 2010-08-03 | Intel Corporation | Processor selection for an interrupt identifying a processor cluster |
| US8190864B1 (en) * | 2007-10-25 | 2012-05-29 | Oracle America, Inc. | APIC implementation for a highly-threaded x86 processor |
| US8024557B2 (en) * | 2007-12-31 | 2011-09-20 | Icera, Inc. | Booting an integrated circuit |
| US8117494B2 (en) * | 2009-12-22 | 2012-02-14 | Intel Corporation | DMI redundancy in multiple processor computer systems |
| JP5609242B2 (ja) * | 2010-04-28 | 2014-10-22 | 富士通株式会社 | 情報処理装置及びメモリダンプ採取方法 |
| US8688883B2 (en) | 2011-09-08 | 2014-04-01 | Intel Corporation | Increasing turbo mode residency of a processor |
| US9372816B2 (en) * | 2011-12-29 | 2016-06-21 | Intel Corporation | Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit |
| WO2013101086A1 (en) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Boot strap processor assignment for a multi-core processing unit |
| EP3014420A4 (de) * | 2013-06-29 | 2017-04-05 | Intel Corporation | On-chip-geflecht |
| US10193826B2 (en) | 2015-07-15 | 2019-01-29 | Intel Corporation | Shared mesh |
| KR102623918B1 (ko) * | 2017-12-25 | 2024-01-11 | 인텔 코포레이션 | 프리-메모리 초기화 멀티스레드 병렬 컴퓨팅 플랫폼 |
| WO2024186049A1 (ko) * | 2023-03-03 | 2024-09-12 | 삼성전자 주식회사 | 전자 장치 및 전자 장치에서 비정상 동작 중 데이터 획득 방법 |
Family Cites Families (53)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3641505A (en) | 1969-06-25 | 1972-02-08 | Bell Telephone Labor Inc | Multiprocessor computer adapted for partitioning into a plurality of independently operating systems |
| US3812469A (en) | 1972-05-12 | 1974-05-21 | Burroughs Corp | Multiprocessing system having means for partitioning into independent processing subsystems |
| US4000485A (en) | 1975-06-30 | 1976-12-28 | Honeywell Information Systems, Inc. | Data processing system providing locked operation of shared resources |
| US4253146A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Module for coupling computer-processors |
| US4253144A (en) | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
| US4245306A (en) | 1978-12-21 | 1981-01-13 | Burroughs Corporation | Selection of addressed processor in a multi-processor network |
| US4240143A (en) | 1978-12-22 | 1980-12-16 | Burroughs Corporation | Hierarchical multi-processor network for memory sharing |
| US4488217A (en) | 1979-03-12 | 1984-12-11 | Digital Equipment Corporation | Data processing system with lock-unlock instruction facility |
| US4392196A (en) | 1980-08-11 | 1983-07-05 | Harris Corporation | Multi-processor time alignment control system |
| US4466059A (en) | 1981-10-15 | 1984-08-14 | International Business Machines Corporation | Method and apparatus for limiting data occupancy in a cache |
| US4441155A (en) | 1981-11-23 | 1984-04-03 | International Business Machines Corporation | Page controlled cache directory addressing |
| US4464717A (en) | 1982-03-31 | 1984-08-07 | Honeywell Information Systems Inc. | Multilevel cache system with graceful degradation capability |
| US4586133A (en) | 1983-04-05 | 1986-04-29 | Burroughs Corporation | Multilevel controller for a cache memory interface in a multiprocessing system |
| US4667288A (en) | 1983-06-30 | 1987-05-19 | Honeywell Information Systems Inc. | Enable/disable control checking apparatus |
| US4562536A (en) | 1983-06-30 | 1985-12-31 | Honeywell Information Systems Inc. | Directory test error mode control apparatus |
| US4686621A (en) | 1983-06-30 | 1987-08-11 | Honeywell Information Systems Inc. | Test apparatus for testing a multilevel cache system with graceful degradation capability |
| US4564903A (en) | 1983-10-05 | 1986-01-14 | International Business Machines Corporation | Partitioned multiprocessor programming system |
| US5067071A (en) | 1985-02-27 | 1991-11-19 | Encore Computer Corporation | Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus |
| US4875155A (en) | 1985-06-28 | 1989-10-17 | International Business Machines Corporation | Peripheral subsystem having read/write cache with record access |
| JPS62194563A (ja) | 1986-02-21 | 1987-08-27 | Hitachi Ltd | バツフア記憶装置 |
| US4843541A (en) | 1987-07-29 | 1989-06-27 | International Business Machines Corporation | Logical resource partitioning of a data processing system |
| US5016167A (en) | 1987-12-21 | 1991-05-14 | Amdahl Corporation | Resource contention deadlock detection and prevention |
| US5251308A (en) | 1987-12-22 | 1993-10-05 | Kendall Square Research Corporation | Shared memory multiprocessor with data hiding and post-store |
| EP0348053B1 (de) | 1988-06-21 | 1995-08-16 | Amdahl Corporation | Startsteuerung von logischen Systemen in einem Datenverarbeitungssystem mit logischer Prozessormöglichkeit |
| US5142676A (en) | 1988-12-28 | 1992-08-25 | Gte Laboratories Incorporated | Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory |
| US4967414A (en) | 1989-01-06 | 1990-10-30 | International Business Machines Corp. | LRU error detection using the collection of read and written LRU bits |
| US5060136A (en) | 1989-01-06 | 1991-10-22 | International Business Machines Corp. | Four-way associative cache with dlat and separately addressable arrays used for updating certain bits without reading them out first |
| US5237670A (en) | 1989-01-30 | 1993-08-17 | Alantec, Inc. | Method and apparatus for data transfer between source and destination modules |
| JP2833062B2 (ja) | 1989-10-30 | 1998-12-09 | 株式会社日立製作所 | キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置 |
| US5497497A (en) * | 1989-11-03 | 1996-03-05 | Compaq Computer Corp. | Method and apparatus for resetting multiple processors using a common ROM |
| JP2826857B2 (ja) | 1989-12-13 | 1998-11-18 | 株式会社日立製作所 | キャッシュ制御方法および制御装置 |
| JPH04119445A (ja) | 1990-09-11 | 1992-04-20 | Canon Inc | 計算機システム |
| US5555420A (en) * | 1990-12-21 | 1996-09-10 | Intel Corporation | Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management |
| US5408629A (en) | 1992-08-13 | 1995-04-18 | Unisys Corporation | Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system |
| JPH06110781A (ja) | 1992-09-30 | 1994-04-22 | Nec Corp | キャッシュメモリ装置 |
| JP2809961B2 (ja) | 1993-03-02 | 1998-10-15 | 株式会社東芝 | マルチプロセッサ |
| US5499354A (en) | 1993-05-19 | 1996-03-12 | International Business Machines Corporation | Method and means for dynamic cache management by variable space and time binding and rebinding of cache extents to DASD cylinders |
| FR2707774B1 (fr) | 1993-07-15 | 1995-08-18 | Bull Sa | Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux. |
| US5504874A (en) | 1993-09-29 | 1996-04-02 | Silicon Graphics, Inc. | System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions |
| WO1995025306A2 (en) | 1994-03-14 | 1995-09-21 | Stanford University | Distributed shared-cache for multi-processors |
| US5490280A (en) | 1994-03-31 | 1996-02-06 | Intel Corporation | Apparatus and method for entry allocation for a resource buffer |
| US5465336A (en) | 1994-06-30 | 1995-11-07 | International Business Machines Corporation | Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system |
| US5642506A (en) | 1994-12-14 | 1997-06-24 | International Business Machines Corporation | Method and apparatus for initializing a multiprocessor system |
| US5717942A (en) | 1994-12-27 | 1998-02-10 | Unisys Corporation | Reset for independent partitions within a computer system |
| US5838955A (en) | 1995-05-03 | 1998-11-17 | Apple Computer, Inc. | Controller for providing access to a video frame buffer in split-bus transaction environment |
| US5729158A (en) | 1995-07-07 | 1998-03-17 | Sun Microsystems, Inc. | Parametric tuning of an integrated circuit after fabrication |
| US5724527A (en) * | 1995-12-28 | 1998-03-03 | Intel Corporation | Fault-tolerant boot strap mechanism for a multiprocessor system |
| US5860002A (en) | 1996-07-12 | 1999-01-12 | Digital Equipment Corporation | System for assigning boot strap processor in symmetric multiprocessor computer with watchdog reassignment |
| US5717897A (en) | 1996-09-09 | 1998-02-10 | Unisys Corporation | System for coordinating coherency of cache memories of multiple host computers of a distributed information system |
| US5867658A (en) | 1997-04-04 | 1999-02-02 | International Business Machines Corporation | Method and apparatus for implementing a stop state for a processor in a multiprocessor system |
| US6216216B1 (en) * | 1998-10-07 | 2001-04-10 | Compaq Computer Corporation | Method and apparatus for providing processor partitioning on a multiprocessor machine |
| US6370606B1 (en) * | 1998-11-05 | 2002-04-09 | Compaq Computer Corporation | System and method for simulating hardware interrupts in a multiprocessor computer system |
| US6339808B1 (en) * | 1999-01-04 | 2002-01-15 | Advanced Micro Devices, Inc. | Address space conversion to retain software compatibility in new architectures |
-
1999
- 1999-07-28 US US09/362,388 patent/US6687818B1/en not_active Expired - Lifetime
-
2000
- 2000-07-12 BR BR0012777-9A patent/BR0012777A/pt not_active IP Right Cessation
- 2000-07-12 KR KR10-2002-7001139A patent/KR100472391B1/ko not_active Expired - Fee Related
- 2000-07-12 DE DE60011777T patent/DE60011777D1/de not_active Expired - Lifetime
- 2000-07-12 AT AT00950318T patent/ATE269989T1/de not_active IP Right Cessation
- 2000-07-12 JP JP2001514665A patent/JP2003506776A/ja active Pending
- 2000-07-12 EP EP00950318A patent/EP1200892B1/de not_active Expired - Lifetime
- 2000-07-12 WO PCT/US2000/018910 patent/WO2001009719A1/en not_active Ceased
-
2007
- 2007-01-22 JP JP2007011912A patent/JP2007149116A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1200892B1 (de) | 2004-06-23 |
| US6687818B1 (en) | 2004-02-03 |
| JP2007149116A (ja) | 2007-06-14 |
| BR0012777A (pt) | 2002-05-07 |
| DE60011777D1 (de) | 2004-07-29 |
| WO2001009719A1 (en) | 2001-02-08 |
| KR100472391B1 (ko) | 2005-03-10 |
| KR20020022089A (ko) | 2002-03-23 |
| JP2003506776A (ja) | 2003-02-18 |
| EP1200892A1 (de) | 2002-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE269989T1 (de) | Verfahren und vorrichtung um den ablauf eines anwendungsprozessors in einem in gruppen angeordneten multiprozessorsystem zu initialisieren | |
| DE60206257D1 (de) | Verfahren und vorrichtung zum abschalten und/oder neustarten von logischen partitionen in einem datenverarbeitungssystem | |
| DE60008929D1 (de) | Schnellstart eines mikroprozessorbasierten systems | |
| DE60028069D1 (de) | Verfahren und vorrichtung zur kontexterhaltung unter ausführung von übersetzten befehlen | |
| WO2003029993A3 (en) | An apparatus and method for enumeration of processors during hot-plug of a compute node | |
| WO2005069155A3 (en) | Method and apparatus for task schedulin in a multi-processor system based on memory requirements | |
| ATE286606T1 (de) | Initialisieren und wiederanlaufen von betriebssystemen | |
| ATE330277T1 (de) | VERFAHREN UND GERÄT ZUR URLADUNG EINER ßNICHT UNIFORMEN SPEICHERZUGRIFF (NUMA) MASCHINEß | |
| WO2005024556A3 (en) | System and method for direct memory access from host without processor intervention wherei automatic access to memory during host start up does not occur | |
| JP2010250817A (ja) | システム管理モードにおけるプロセッサ間割り込みの再方向付け | |
| EP2040159A3 (de) | Prozessor und Schnittstelle | |
| EP2128759A4 (de) | Herauffahr-steuerverfahren für ein betriebssystem und informationsverarbeitungseinrichtung | |
| EP0788054A3 (de) | Speichersteuerungsvorrichtung und -system | |
| SE436604B (sv) | Mikroprogramstyranordning for inkorning av mikroprogram | |
| CN112965755B (zh) | 多核处理器的初始化方法、装置、电子设备及存储介质 | |
| CN110045992B (zh) | 一种适用于多核板卡的通用系统及方法 | |
| EP1103890A3 (de) | Verfahren für den direkten Anruf einer Funktion durch einen Software-Modul mittels eines Prozessors mit einer Speicherverwaltungseinheit | |
| CN112199101A (zh) | 一种基于串口的mcu升级方法、系统、设备及介质 | |
| GB2345996A (en) | Method and apparatus for accessing and executing the contents of physical memory from a virtual memory subsystem | |
| JP4967555B2 (ja) | マルチプロセッサシステム | |
| KR970076161A (ko) | 프로그램 다운로딩을 위한 동적 식별번호 부여방법 | |
| JPS5592947A (en) | Interruption control system for microprogram | |
| JPH11265284A (ja) | データ処理装置 | |
| JPH0341517A (ja) | セットアップ起動方式 | |
| JPH01286028A (ja) | マイクロプログラムのパッチ方式 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |