ATE308054T1 - Testsystem - Google Patents

Testsystem

Info

Publication number
ATE308054T1
ATE308054T1 AT02254231T AT02254231T ATE308054T1 AT E308054 T1 ATE308054 T1 AT E308054T1 AT 02254231 T AT02254231 T AT 02254231T AT 02254231 T AT02254231 T AT 02254231T AT E308054 T1 ATE308054 T1 AT E308054T1
Authority
AT
Austria
Prior art keywords
circuit
testing
test
external clock
external
Prior art date
Application number
AT02254231T
Other languages
English (en)
Inventor
Richard J Evans
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE308054T1 publication Critical patent/ATE308054T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318502—Test of Combinational circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Lubricants (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)
AT02254231T 2001-06-20 2002-06-18 Testsystem ATE308054T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US29917501P 2001-06-20 2001-06-20

Publications (1)

Publication Number Publication Date
ATE308054T1 true ATE308054T1 (de) 2005-11-15

Family

ID=23153615

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02254231T ATE308054T1 (de) 2001-06-20 2002-06-18 Testsystem

Country Status (4)

Country Link
US (1) US20030009714A1 (de)
EP (1) EP1271162B1 (de)
AT (1) ATE308054T1 (de)
DE (1) DE60206845T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040085082A1 (en) * 2002-10-30 2004-05-06 Townley Kent Richard High -frequency scan testability with low-speed testers
US7085976B1 (en) * 2003-02-18 2006-08-01 Xilinx, Inc. Method and apparatus for hardware co-simulation clocking
US7155649B2 (en) * 2003-03-12 2006-12-26 Matsushita Electric Industrial Co., Ltd. Scan test control method and scan test circuit
US7404128B2 (en) * 2004-02-17 2008-07-22 Texas Instruments Incorporated Serial data I/O on JTAG TCK with TMS clocking
US7519111B2 (en) * 2004-03-15 2009-04-14 Texas Instruments Incorporated Apparatus and method for providing system and test clock signals to an integrated circuit on a single pin
DE602004013918D1 (de) * 2004-04-07 2008-07-03 Sgs Thomson Microelectronics Hochgeschwindigkeitsprüfung von integrierten Schaltungen
JP2006038743A (ja) * 2004-07-29 2006-02-09 Nec Electronics Corp 半導体集積回路装置及びその試験装置
US7627798B2 (en) * 2004-10-08 2009-12-01 Kabushiki Kaisha Toshiba Systems and methods for circuit testing using LBIST
WO2006123204A1 (en) * 2005-05-19 2006-11-23 Freescale Semiconductor, Inc. Method and device for high speed testing of an integrated circuit
KR100870037B1 (ko) * 2006-10-26 2008-11-24 삼성전자주식회사 테스트가 용이한 반도체 장치, 반도체 장치 테스트 방법,반도체 장치 테스트를 위한 테스트 클럭 생성 방법 및 장치
US7987401B2 (en) * 2006-11-27 2011-07-26 Broadcom Corporation System and method for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing
US20080282110A1 (en) * 2007-05-09 2008-11-13 Amar Guettaf Scan clock architecture supporting slow speed scan, at speed scan, and logic bist
JP5029161B2 (ja) * 2007-06-15 2012-09-19 株式会社デンソー 半導体集積装置
US8205125B2 (en) * 2009-10-23 2012-06-19 Texas Instruments Incorporated Enhanced control in scan tests of integrated circuits with partitioned scan chains
KR101992205B1 (ko) 2012-12-12 2019-06-24 삼성전자주식회사 온칩 클록 제어회로 및 시스템 온 칩
US9194915B2 (en) 2013-09-12 2015-11-24 International Business Machines Corporation Control test point for timing stability during scan capture
US9465404B2 (en) * 2014-08-06 2016-10-11 Freescale Semiconductor, Inc. Timing synchronization circuit for wireless communication apparatus
KR20160121947A (ko) * 2015-04-13 2016-10-21 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770573B2 (ja) * 1989-07-11 1995-07-31 富士通株式会社 半導体集積回路装置
US5524114A (en) * 1993-10-22 1996-06-04 Lsi Logic Corporation Method and apparatus for testing semiconductor devices at speed
JPH08201481A (ja) * 1995-01-27 1996-08-09 Internatl Business Mach Corp <Ibm> 半導体集積回路
US5519715A (en) * 1995-01-27 1996-05-21 Sun Microsystems, Inc. Full-speed microprocessor testing employing boundary scan
US6055658A (en) * 1995-10-02 2000-04-25 International Business Machines Corporation Apparatus and method for testing high speed components using low speed test apparatus
US5909451A (en) * 1996-11-21 1999-06-01 Sun Microsystems, Inc. System and method for providing scan chain for digital electronic device having multiple clock domains
JP3257425B2 (ja) * 1996-12-25 2002-02-18 日本電気株式会社 テスト回路及びテスト方法
US5875153A (en) * 1997-04-30 1999-02-23 Texas Instruments Incorporated Internal/external clock option for built-in self test
US6000051A (en) * 1997-10-10 1999-12-07 Logic Vision, Inc. Method and apparatus for high-speed interconnect testing
US6158032A (en) * 1998-03-27 2000-12-05 International Business Machines Corporation Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof
US6163865A (en) * 1998-07-22 2000-12-19 Lucent Technologies, Inc. Built-in self-test circuit for read channel device
US6418545B1 (en) * 1999-06-04 2002-07-09 Koninklijke Philips Electronics N.V. System and method to reduce scan test pins on an integrated circuit
TW484016B (en) * 1999-07-28 2002-04-21 Hitachi Ltd Semiconductor integrated circuit and recording medium
JP3434762B2 (ja) * 1999-12-27 2003-08-11 エヌイーシーマイクロシステム株式会社 半導体集積回路
US6598192B1 (en) * 2000-02-28 2003-07-22 Motorola, Inc. Method and apparatus for testing an integrated circuit
US6715105B1 (en) * 2000-11-14 2004-03-30 Agilent Technologies, Inc. Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
US7191373B2 (en) * 2001-03-01 2007-03-13 Syntest Technologies, Inc. Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
US6671848B1 (en) * 2001-03-20 2003-12-30 Advanced Micro Devices, Inc. Test circuit for exposing higher order speed paths
US6738921B2 (en) * 2001-03-20 2004-05-18 International Business Machines Corporation Clock controller for AC self-test timing analysis of logic system

Also Published As

Publication number Publication date
DE60206845D1 (de) 2005-12-01
DE60206845T2 (de) 2006-07-06
US20030009714A1 (en) 2003-01-09
EP1271162A2 (de) 2003-01-02
EP1271162B1 (de) 2005-10-26
EP1271162A3 (de) 2003-12-17

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties