ATE317982T1 - Verfahren zum speichern von registereigenschaften in einer datenstruktur und dazugehörige datenstruktur - Google Patents

Verfahren zum speichern von registereigenschaften in einer datenstruktur und dazugehörige datenstruktur

Info

Publication number
ATE317982T1
ATE317982T1 AT02292677T AT02292677T ATE317982T1 AT E317982 T1 ATE317982 T1 AT E317982T1 AT 02292677 T AT02292677 T AT 02292677T AT 02292677 T AT02292677 T AT 02292677T AT E317982 T1 ATE317982 T1 AT E317982T1
Authority
AT
Austria
Prior art keywords
data structure
properties
associated data
storing registry
registry
Prior art date
Application number
AT02292677T
Other languages
English (en)
Inventor
Dirk George Cyriel Goethals
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Application granted granted Critical
Publication of ATE317982T1 publication Critical patent/ATE317982T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT02292677T 2002-10-28 2002-10-28 Verfahren zum speichern von registereigenschaften in einer datenstruktur und dazugehörige datenstruktur ATE317982T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02292677A EP1416290B1 (de) 2002-10-28 2002-10-28 Verfahren zum Speichern von Registereigenschaften in einer Datenstruktur und dazugehörige Datenstruktur

Publications (1)

Publication Number Publication Date
ATE317982T1 true ATE317982T1 (de) 2006-03-15

Family

ID=32088069

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02292677T ATE317982T1 (de) 2002-10-28 2002-10-28 Verfahren zum speichern von registereigenschaften in einer datenstruktur und dazugehörige datenstruktur

Country Status (5)

Country Link
US (1) US7346749B2 (de)
EP (1) EP1416290B1 (de)
AT (1) ATE317982T1 (de)
DE (1) DE60209201T2 (de)
ES (1) ES2253503T3 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7827324B2 (en) * 2006-09-20 2010-11-02 Integrated Device Technology Inc. Method of handling flow control in daisy-chain protocols
US10990664B2 (en) * 2017-11-20 2021-04-27 International Business Machines Corporation Eliminating and reporting kernel instruction alteration

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4450560A (en) * 1981-10-09 1984-05-22 Teradyne, Inc. Tester for LSI devices and memory devices
US5243274A (en) * 1992-08-07 1993-09-07 Westinghouse Electric Corp. Asic tester
US5991907A (en) * 1996-02-02 1999-11-23 Lucent Technologies Inc. Method for testing field programmable gate arrays
US5812416A (en) * 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition
US6120551A (en) * 1997-09-29 2000-09-19 Xilinx, Inc. Hardwire logic device emulating an FPGA
US6148432A (en) * 1997-11-17 2000-11-14 Micron Technology, Inc. Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis
US6102963A (en) * 1997-12-29 2000-08-15 Vantis Corporation Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's
JP3809727B2 (ja) * 1998-06-17 2006-08-16 富士ゼロックス株式会社 情報処理システム、回路情報管理方法および回路情報記憶装置

Also Published As

Publication number Publication date
EP1416290A1 (de) 2004-05-06
ES2253503T3 (es) 2006-06-01
EP1416290B1 (de) 2006-02-15
US20040153820A1 (en) 2004-08-05
DE60209201T2 (de) 2006-11-16
DE60209201D1 (de) 2006-04-20
US7346749B2 (en) 2008-03-18

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties