ATE327555T1 - System und verfahren zum frühen schreiben in speicher durch halten der bitleitung auf festem potential - Google Patents

System und verfahren zum frühen schreiben in speicher durch halten der bitleitung auf festem potential

Info

Publication number
ATE327555T1
ATE327555T1 AT01995491T AT01995491T ATE327555T1 AT E327555 T1 ATE327555 T1 AT E327555T1 AT 01995491 T AT01995491 T AT 01995491T AT 01995491 T AT01995491 T AT 01995491T AT E327555 T1 ATE327555 T1 AT E327555T1
Authority
AT
Austria
Prior art keywords
bitline
memory
fixed potential
written
write
Prior art date
Application number
AT01995491T
Other languages
English (en)
Inventor
John E Barth Jr
Harold Pilo
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE327555T1 publication Critical patent/ATE327555T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
AT01995491T 2001-06-29 2001-12-10 System und verfahren zum frühen schreiben in speicher durch halten der bitleitung auf festem potential ATE327555T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/896,746 US6400629B1 (en) 2001-06-29 2001-06-29 System and method for early write to memory by holding bitline at fixed potential

Publications (1)

Publication Number Publication Date
ATE327555T1 true ATE327555T1 (de) 2006-06-15

Family

ID=25406754

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01995491T ATE327555T1 (de) 2001-06-29 2001-12-10 System und verfahren zum frühen schreiben in speicher durch halten der bitleitung auf festem potential

Country Status (9)

Country Link
US (1) US6400629B1 (de)
EP (1) EP1433179B1 (de)
JP (1) JP3953461B2 (de)
KR (1) KR100613317B1 (de)
CN (1) CN100345213C (de)
AT (1) ATE327555T1 (de)
DE (1) DE60119995T2 (de)
TW (1) TW574708B (de)
WO (1) WO2003003376A1 (de)

Families Citing this family (19)

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Publication number Priority date Publication date Assignee Title
US6788591B1 (en) 2003-08-26 2004-09-07 International Business Machines Corporation System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch
KR100590855B1 (ko) * 2003-10-14 2006-06-19 주식회사 하이닉스반도체 전류 소모의 감소를 위한 반도체 메모리 소자
US7009905B2 (en) * 2003-12-23 2006-03-07 International Business Machines Corporation Method and apparatus to reduce bias temperature instability (BTI) effects
US7079427B2 (en) * 2004-07-02 2006-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for a high-speed access architecture for semiconductor memory
US7221605B2 (en) * 2004-08-31 2007-05-22 Micron Technology, Inc. Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
US7236415B2 (en) * 2004-09-01 2007-06-26 Micron Technology, Inc. Sample and hold memory sense amplifier
KR100720260B1 (ko) * 2004-11-15 2007-05-22 주식회사 하이닉스반도체 반도체 메모리 장치의 로컬 입출력 라인 프리차지 회로
KR20090119143A (ko) * 2008-05-15 2009-11-19 삼성전자주식회사 비트라인 센스 앰프, 이를 포함하는 메모리 코어 및 반도체메모리 장치
CN101359509B (zh) * 2008-09-02 2010-06-02 北京芯技佳易微电子科技有限公司 一次性可编程存储器电路及其编程和读取方法
KR20110036211A (ko) * 2009-10-01 2011-04-07 삼성전자주식회사 프리 센싱 및 분리 회로를 포함하는 반도체 메모리 장치
KR102048255B1 (ko) 2012-10-25 2019-11-25 삼성전자주식회사 비트 라인 감지 증폭기 및 이를 포함하는 반도체 메모리 장치 및 메모리 시스템
GB2512844B (en) * 2013-04-08 2017-06-21 Surecore Ltd Reduced Power Memory Unit
US9281043B1 (en) * 2014-12-24 2016-03-08 Intel Corporation Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
US11068639B2 (en) * 2018-10-19 2021-07-20 Arm Limited Metal layout techniques
JP2021034090A (ja) * 2019-08-28 2021-03-01 キオクシア株式会社 不揮発性半導体記憶装置
US11017845B2 (en) * 2019-09-11 2021-05-25 Sigmasense, Llc. RAM cell processing circuit for concurrency of refresh and read
CN111863051B (zh) * 2020-07-27 2022-11-22 安徽大学 灵敏放大器、存储器和灵敏放大器的控制方法
US11929112B2 (en) 2020-07-27 2024-03-12 Anhui University Sense amplifier, memory, and method for controlling sense amplifier
US11404127B1 (en) * 2021-02-11 2022-08-02 Sandisk Technologies Llc Read refresh to improve power on data retention for a non-volatile memory

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JPS615495A (ja) 1984-05-31 1986-01-11 Toshiba Corp 半導体記憶装置
US5007022A (en) 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
JP3101298B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
US5237533A (en) * 1991-12-20 1993-08-17 National Semiconductor Corporation High speed switched sense amplifier
US5339274A (en) * 1992-10-30 1994-08-16 International Business Machines Corporation Variable bitline precharge voltage sensing technique for DRAM structures
EP0597231B1 (de) * 1992-11-12 1998-11-25 United Memories, Inc. Leseverstärker für einen integrierten Speicher
JPH07211068A (ja) 1994-01-18 1995-08-11 Matsushita Electric Ind Co Ltd メモリ装置
US5677865A (en) * 1995-09-11 1997-10-14 Micron Technology, Inc. Ferroelectric memory using reference charge circuit
JPH09162305A (ja) * 1995-12-08 1997-06-20 Mitsubishi Electric Corp 半導体記憶装置
JPH10111828A (ja) 1996-09-27 1998-04-28 Internatl Business Mach Corp <Ibm> メモリシステム、データ転送方法
US5923593A (en) 1996-12-17 1999-07-13 Monolithic Systems, Inc. Multi-port DRAM cell and memory system using same
JPH1186539A (ja) 1997-09-04 1999-03-30 Canon Inc データ処理装置、及び方法
JP2978871B2 (ja) 1998-01-30 1999-11-15 日本電気アイシーマイコンシステム株式会社 リフレッシュ制御方式
US5963497A (en) 1998-05-18 1999-10-05 Silicon Aquarius, Inc. Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same

Also Published As

Publication number Publication date
CN1522445A (zh) 2004-08-18
EP1433179A4 (de) 2005-07-06
JP3953461B2 (ja) 2007-08-08
JP2004531019A (ja) 2004-10-07
KR100613317B1 (ko) 2006-08-21
CN100345213C (zh) 2007-10-24
TW574708B (en) 2004-02-01
KR20040008197A (ko) 2004-01-28
WO2003003376A1 (en) 2003-01-09
DE60119995D1 (de) 2006-06-29
US6400629B1 (en) 2002-06-04
EP1433179B1 (de) 2006-05-24
DE60119995T2 (de) 2007-05-24
EP1433179A1 (de) 2004-06-30

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