ATE331341T1 - Verriegelte regelkreise mit niedriger verriegelungszeitverzögerung mit der verwendung einer zeitzyklusunterdrückungsvorrichtung - Google Patents

Verriegelte regelkreise mit niedriger verriegelungszeitverzögerung mit der verwendung einer zeitzyklusunterdrückungsvorrichtung

Info

Publication number
ATE331341T1
ATE331341T1 AT03813246T AT03813246T ATE331341T1 AT E331341 T1 ATE331341 T1 AT E331341T1 AT 03813246 T AT03813246 T AT 03813246T AT 03813246 T AT03813246 T AT 03813246T AT E331341 T1 ATE331341 T1 AT E331341T1
Authority
AT
Austria
Prior art keywords
delay locked
control loop
time cycle
suppression device
time delay
Prior art date
Application number
AT03813246T
Other languages
English (en)
Inventor
Sri Navaneethakrishna Easwaran
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE331341T1 publication Critical patent/ATE331341T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00032—DC control of switching transistors
    • H03K2005/00039—DC control of switching transistors having four transistors serially

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Dram (AREA)
AT03813246T 2002-12-13 2003-12-09 Verriegelte regelkreise mit niedriger verriegelungszeitverzögerung mit der verwendung einer zeitzyklusunterdrückungsvorrichtung ATE331341T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43321302P 2002-12-13 2002-12-13

Publications (1)

Publication Number Publication Date
ATE331341T1 true ATE331341T1 (de) 2006-07-15

Family

ID=32595138

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03813246T ATE331341T1 (de) 2002-12-13 2003-12-09 Verriegelte regelkreise mit niedriger verriegelungszeitverzögerung mit der verwendung einer zeitzyklusunterdrückungsvorrichtung

Country Status (8)

Country Link
US (1) US7256635B2 (de)
EP (1) EP1573920B1 (de)
JP (1) JP4597681B2 (de)
CN (1) CN100542037C (de)
AT (1) ATE331341T1 (de)
AU (1) AU2003302953A1 (de)
DE (1) DE60306424T2 (de)
WO (1) WO2004055989A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227809B2 (en) * 2005-10-14 2007-06-05 Micron Technology, Inc. Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration
US7423465B2 (en) * 2006-01-27 2008-09-09 Micron Technology, Inc. Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit
US8073890B2 (en) * 2006-02-22 2011-12-06 Micron Technology, Inc. Continuous high-frequency event filter
TW200734462A (en) 2006-03-08 2007-09-16 In Motion Invest Ltd Regulating stem cells
US9404084B2 (en) 2007-06-20 2016-08-02 Kwalata Trading Limited Regulating stem cells
CN101446842B (zh) * 2008-12-29 2010-04-21 中国科学院计算技术研究所 一种门控时钟系统及其工作方法
CN103280813B (zh) * 2013-05-17 2014-12-03 华北电力大学 用于电压控制的tcsc控制器及其控制方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2548340B2 (ja) * 1988-11-01 1996-10-30 松下電器産業株式会社 チャタリング除去回路
US4973860A (en) * 1989-05-02 1990-11-27 Ast Research Inc. Circuit for synchronizing an asynchronous input signal to a high frequency clock
JP2795323B2 (ja) * 1989-06-14 1998-09-10 富士通株式会社 位相差検出回路
US5001374A (en) * 1989-09-08 1991-03-19 Amp Incorporated Digital filter for removing short duration noise
JPH03136519A (ja) * 1989-10-23 1991-06-11 Matsushita Electric Ind Co Ltd ハザード防止回路
JPH0475121A (ja) * 1990-07-17 1992-03-10 Mitsubishi Electric Corp 自動車用入力インターフエイス回路
US5463655A (en) * 1993-02-17 1995-10-31 National Semiconductor Corporation Single-ended pulse gating circuit
FR2713034B1 (fr) * 1993-11-23 1996-01-26 Matra Mhs Circuit de récupération d'horloge à oscillateurs appariés.
US5623223A (en) * 1994-10-12 1997-04-22 National Semiconductor Corporation Glitchless clock switching circuit
US6088255A (en) * 1998-03-20 2000-07-11 Fujitsu Limited Semiconductor device with prompt timing stabilization
US6289068B1 (en) * 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
JP2984665B1 (ja) * 1998-08-28 1999-11-29 日本電気アイシーマイコンシステム株式会社 波形整形回路
JP3439670B2 (ja) * 1998-10-15 2003-08-25 富士通株式会社 階層型ｄｌｌ回路を利用したタイミングクロック発生回路
FR2793091B1 (fr) * 1999-04-30 2001-06-08 France Telecom Dispositif d'asservissement de frequence
JP2001028542A (ja) * 1999-07-13 2001-01-30 Oki Micro Design Co Ltd Ｐｌｌ回路
US6417705B1 (en) * 2000-04-18 2002-07-09 National Semiconductor Corporation Output driver with DLL control of output driver strength

Also Published As

Publication number Publication date
AU2003302953A1 (en) 2004-07-09
JP2006510300A (ja) 2006-03-23
WO2004055989A2 (en) 2004-07-01
DE60306424D1 (de) 2006-08-03
CN1726643A (zh) 2006-01-25
WO2004055989A3 (en) 2004-12-02
US20060103440A1 (en) 2006-05-18
US7256635B2 (en) 2007-08-14
JP4597681B2 (ja) 2010-12-15
DE60306424T2 (de) 2007-02-01
CN100542037C (zh) 2009-09-16
EP1573920A2 (de) 2005-09-14
EP1573920B1 (de) 2006-06-21

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