ATE441868T1 - Verfahren und vorrichtung zum verstellen der phase einer eingangs-/ausgangsschaltung - Google Patents

Verfahren und vorrichtung zum verstellen der phase einer eingangs-/ausgangsschaltung

Info

Publication number
ATE441868T1
ATE441868T1 AT01946226T AT01946226T ATE441868T1 AT E441868 T1 ATE441868 T1 AT E441868T1 AT 01946226 T AT01946226 T AT 01946226T AT 01946226 T AT01946226 T AT 01946226T AT E441868 T1 ATE441868 T1 AT E441868T1
Authority
AT
Austria
Prior art keywords
circuit
clock
phase
input
phase adjustment
Prior art date
Application number
AT01946226T
Other languages
English (en)
Inventor
Keng Wong
Gregory Taylor
Songmin Kim
Chi-Yeu Chao
Chee Lim
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE441868T1 publication Critical patent/ATE441868T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
AT01946226T 2000-06-26 2001-06-07 Verfahren und vorrichtung zum verstellen der phase einer eingangs-/ausgangsschaltung ATE441868T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/604,049 US6748549B1 (en) 2000-06-26 2000-06-26 Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
PCT/US2001/018754 WO2002001233A2 (en) 2000-06-26 2001-06-07 Method and apparatus for adjusting the phase of input/output circuitry

Publications (1)

Publication Number Publication Date
ATE441868T1 true ATE441868T1 (de) 2009-09-15

Family

ID=24417975

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01946226T ATE441868T1 (de) 2000-06-26 2001-06-07 Verfahren und vorrichtung zum verstellen der phase einer eingangs-/ausgangsschaltung

Country Status (8)

Country Link
US (1) US6748549B1 (de)
EP (1) EP1295134B1 (de)
CN (1) CN1287527C (de)
AT (1) ATE441868T1 (de)
AU (1) AU2001268304A1 (de)
DE (1) DE60139777D1 (de)
TW (1) TW530197B (de)
WO (1) WO2002001233A2 (de)

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US6735709B1 (en) 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
US7180352B2 (en) * 2001-06-28 2007-02-20 Intel Corporation Clock recovery using clock phase interpolator
JP2003043117A (ja) * 2001-08-02 2003-02-13 Fujitsu Ltd 半導体集積回路
JP2003157699A (ja) * 2001-11-20 2003-05-30 Oki Electric Ind Co Ltd 半導体記憶装置
DE50210698D1 (de) * 2002-03-23 2007-09-27 Micronas Gmbh Taktschema und Takteinrichtung für eine monolitisch integrierte Schaltung
JP3779687B2 (ja) * 2003-01-29 2006-05-31 Ｎｅｃエレクトロニクス株式会社 表示装置駆動回路
US6954093B2 (en) 2003-03-27 2005-10-11 Micronas Gmbh Clocking scheme and clock system for a monolithic integrated circuit
KR100515071B1 (ko) * 2003-04-29 2005-09-16 주식회사 하이닉스반도체 디엘엘 장치
US6919769B2 (en) * 2003-09-24 2005-07-19 Intel Corporation Method and apparatus for fast lock acquisition in self-biased phase locked loops
US6970029B2 (en) * 2003-12-30 2005-11-29 Intel Corporation Variable-delay signal generators and methods of operation therefor
US7477078B2 (en) * 2004-02-02 2009-01-13 Synthesys Research, Inc Variable phase bit sampling with minimized synchronization loss
US7024324B2 (en) * 2004-05-27 2006-04-04 Intel Corporation Delay element calibration
US7154320B2 (en) * 2005-03-29 2006-12-26 Intel Corporation Frequency-based slope-adjustment circuit
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US7571267B1 (en) * 2006-03-27 2009-08-04 Integrated Device Technology, Inc. Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews
CN101420510B (zh) * 2007-10-26 2014-06-11 瑞昱半导体股份有限公司 应用于多媒体接口的时钟的产生装置及其相关方法
IT1397376B1 (it) * 2009-12-30 2013-01-10 St Microelectronics Srl Regolazione di una linea di ritardo programmabile ad anello pseudo-chiuso
CN102859879B (zh) * 2010-05-13 2015-03-11 华为技术有限公司 用于校验锁相环中的输出频率的系统和方法
CN102281063A (zh) * 2010-06-10 2011-12-14 中兴通讯股份有限公司 调整频率的方法以及装置
TWI482030B (zh) * 2011-06-21 2015-04-21 Via Tech Inc 補償同步資料匯流排上的非對齊之裝置及方法
US20140003564A1 (en) * 2012-06-27 2014-01-02 Broadcom Corporation Multichip synchronization system
GB2513529A (en) 2012-11-15 2014-11-05 Ibm System and method of low latency data tranfer between clock domains operated in various synchronization modes
KR102006243B1 (ko) * 2012-12-24 2019-08-01 에스케이하이닉스 주식회사 반도체 장치의 데이터 라이트 회로
EP2762990B1 (de) * 2013-02-01 2015-12-09 Nxp B.V. Taktauswahlschaltung und Verfahren
US9286961B1 (en) * 2015-03-30 2016-03-15 Apple Inc. Memory controller half-clock delay adjustment
CN105759195A (zh) * 2016-02-24 2016-07-13 复旦大学 基于精细调相的建立保持时间测试系统和方法
US10324879B2 (en) 2016-09-28 2019-06-18 International Business Machines Corporation Mitigation of side effects of simultaneous switching of input/output (I/O data signals
US11133806B1 (en) * 2019-05-14 2021-09-28 Space Exploration Technologies Corp. Phase lock loop (PLL) synchronization
US11153067B2 (en) 2019-05-14 2021-10-19 Space Exploration Technologies Corp. Chip to chip time synchronization
KR102911992B1 (ko) * 2020-08-07 2026-01-12 삼성전자 주식회사 비휘발성 메모리 장치 및 상기 비휘발성 메모리 장치를 포함하는 스토리지 장치
CN115267304B (zh) * 2021-04-30 2025-09-02 脸萌有限公司 供电电压检测器、供电电压检测装置、系统和介质
US12155391B2 (en) 2021-12-09 2024-11-26 Rambus, Inc. Clock buffer
CN115167611B (zh) * 2022-06-24 2026-01-09 无锡芯光互连技术研究院有限公司 Pcie设备时钟保持装置、方法和可读存储介质

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US5446867A (en) * 1992-05-29 1995-08-29 Intel Corporation Microprocessor PLL clock circuit with selectable delayed feedback
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US6236695B1 (en) * 1999-05-21 2001-05-22 Intel Corporation Output buffer with timing feedback

Also Published As

Publication number Publication date
TW530197B (en) 2003-05-01
EP1295134A2 (de) 2003-03-26
WO2002001233A2 (en) 2002-01-03
CN1528051A (zh) 2004-09-08
CN1287527C (zh) 2006-11-29
DE60139777D1 (de) 2009-10-15
WO2002001233A3 (en) 2002-08-01
EP1295134B1 (de) 2009-09-02
AU2001268304A1 (en) 2002-01-08
US6748549B1 (en) 2004-06-08

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