ATE331989T1 - Asynchrone zentralisierte multikanal-dma- steuerung - Google Patents

Asynchrone zentralisierte multikanal-dma- steuerung

Info

Publication number
ATE331989T1
ATE331989T1 AT00975211T AT00975211T ATE331989T1 AT E331989 T1 ATE331989 T1 AT E331989T1 AT 00975211 T AT00975211 T AT 00975211T AT 00975211 T AT00975211 T AT 00975211T AT E331989 T1 ATE331989 T1 AT E331989T1
Authority
AT
Austria
Prior art keywords
requests
system bus
peripheral
bus
circuit
Prior art date
Application number
AT00975211T
Other languages
English (en)
Inventor
John Milford Brooks
Original Assignee
Conexant Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems Inc filed Critical Conexant Systems Inc
Application granted granted Critical
Publication of ATE331989T1 publication Critical patent/ATE331989T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G06F13/4036—Coupling between buses using bus bridges with arbitration and deadlock prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Selective Calling Equipment (AREA)
  • Communication Control (AREA)
AT00975211T 1999-09-30 2000-09-27 Asynchrone zentralisierte multikanal-dma- steuerung ATE331989T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/409,820 US6532511B1 (en) 1999-09-30 1999-09-30 Asochronous centralized multi-channel DMA controller

Publications (1)

Publication Number Publication Date
ATE331989T1 true ATE331989T1 (de) 2006-07-15

Family

ID=23622095

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00975211T ATE331989T1 (de) 1999-09-30 2000-09-27 Asynchrone zentralisierte multikanal-dma- steuerung

Country Status (5)

Country Link
US (1) US6532511B1 (de)
EP (1) EP1222551B1 (de)
AT (1) ATE331989T1 (de)
DE (1) DE60029118T2 (de)
WO (1) WO2001024015A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6829669B2 (en) * 2000-09-08 2004-12-07 Texas Instruments Incorporated Bus bridge interface system
US6760802B2 (en) * 2000-09-08 2004-07-06 Texas Instruments Incorporated Time-out counter for multiple transaction bus system bus bridge
EP1308846B1 (de) * 2001-10-31 2008-10-01 Infineon Technologies AG Datenübertragungseinrichtung
US7130953B2 (en) * 2003-03-05 2006-10-31 Broadcom Corporation Bus architecture techniques employing busses with different complexities
KR100630071B1 (ko) * 2003-11-05 2006-09-27 삼성전자주식회사 다중 프로세서 환경에서의 ｄｍａ를 이용한 고속 데이터전송 방법 및 그 장치
US20050038946A1 (en) * 2003-08-12 2005-02-17 Tadpole Computer, Inc. System and method using a high speed interface in a system having co-processors
CN100412833C (zh) * 2003-11-17 2008-08-20 北京北大众志微系统科技有限责任公司 Dma控制器、具有层次总线结构的系统芯片及数据传输方法
KR100633742B1 (ko) * 2003-12-23 2006-10-13 한국전자통신연구원 주변 장치로부터 데이터 전송 크기를 자동으로 갱신하는직접 메모리 액세스 제어 장치 및 방법
US20060031603A1 (en) * 2004-08-09 2006-02-09 Bradfield Travis A Multi-threaded/multi-issue DMA engine data transfer system
JP4785637B2 (ja) * 2006-06-16 2011-10-05 キヤノン株式会社 データ転送装置及びその制御方法
TWI376605B (en) * 2006-09-04 2012-11-11 Novatek Microelectronics Corp Method and apparatus for enhancing data rate of advanced micro-controller bus architecture
US8224885B1 (en) 2009-01-26 2012-07-17 Teradici Corporation Method and system for remote computing session management
US8504756B2 (en) 2011-05-30 2013-08-06 Lsi Corporation System, circuit and method for improving system-on-chip bandwidth performance for high latency peripheral read accesses
WO2014147448A1 (en) * 2013-03-22 2014-09-25 Freescale Semiconductor, Inc. A method of controlling direct memory access of a peripheral memory of a peripheral by a master, an associated circuitry, an associated device and an associated computer program product
US9891986B2 (en) * 2016-01-26 2018-02-13 Nxp Usa, Inc. System and method for performing bus transactions
US11295205B2 (en) * 2018-09-28 2022-04-05 Qualcomm Incorporated Neural processing unit (NPU) direct memory access (NDMA) memory bandwidth optimization

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208915A (en) * 1982-11-09 1993-05-04 Siemens Aktiengesellschaft Apparatus for the microprogram control of information transfer and a method for operating the same
US5717873A (en) 1993-09-30 1998-02-10 Intel Corporation Deadlock avoidance mechanism and method for multiple bus topology
US5623697A (en) 1994-11-30 1997-04-22 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension
JPH0954746A (ja) 1995-08-11 1997-02-25 Toshiba Corp コンピュータシステム
US5768545A (en) 1996-06-11 1998-06-16 Intel Corporation Collect all transfers buffering mechanism utilizing passive release for a multiple bus environment
US6145017A (en) * 1997-08-05 2000-11-07 Adaptec, Inc. Data alignment system for a hardware accelerated command interpreter engine
US6279050B1 (en) * 1998-12-18 2001-08-21 Emc Corporation Data transfer apparatus having upper, lower, middle state machines, with middle state machine arbitrating among lower state machine side requesters including selective assembly/disassembly requests

Also Published As

Publication number Publication date
EP1222551B1 (de) 2006-06-28
EP1222551A2 (de) 2002-07-17
WO2001024015A3 (en) 2001-10-25
DE60029118D1 (de) 2006-08-10
DE60029118T2 (de) 2007-02-01
US6532511B1 (en) 2003-03-11
WO2001024015A2 (en) 2001-04-05

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Legal Events

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