ATE340411T1 - Verfahren zur herstellung einer halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung

Info

Publication number
ATE340411T1
ATE340411T1 AT97947922T AT97947922T ATE340411T1 AT E340411 T1 ATE340411 T1 AT E340411T1 AT 97947922 T AT97947922 T AT 97947922T AT 97947922 T AT97947922 T AT 97947922T AT E340411 T1 ATE340411 T1 AT E340411T1
Authority
AT
Austria
Prior art keywords
temperature
sputtering process
aluminum
temperature sputtering
producing
Prior art date
Application number
AT97947922T
Other languages
English (en)
Inventor
Toyohiko Kuno
Kenichi Kitamura
Ken Tanaka
Original Assignee
Asahi Chemical Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Ind filed Critical Asahi Chemical Ind
Application granted granted Critical
Publication of ATE340411T1 publication Critical patent/ATE340411T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Die Bonding (AREA)
  • Physical Vapour Deposition (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
AT97947922T 1996-12-12 1997-12-12 Verfahren zur herstellung einer halbleitervorrichtung ATE340411T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33193196 1996-12-12

Publications (1)

Publication Number Publication Date
ATE340411T1 true ATE340411T1 (de) 2006-10-15

Family

ID=18249249

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97947922T ATE340411T1 (de) 1996-12-12 1997-12-12 Verfahren zur herstellung einer halbleitervorrichtung

Country Status (10)

Country Link
US (1) US6162729A (de)
EP (1) EP0951066B1 (de)
JP (1) JP4226658B2 (de)
KR (1) KR100339670B1 (de)
CN (1) CN1121711C (de)
AT (1) ATE340411T1 (de)
AU (1) AU5411498A (de)
DE (1) DE69736717T2 (de)
TW (1) TW417178B (de)
WO (1) WO1998026450A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10032792A1 (de) * 2000-06-28 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Verdrahtung für Kontaktlöcher
US20060157947A1 (en) * 2003-09-19 2006-07-20 Paulovits Gabor Jr Method of skate board identification
JP2007299947A (ja) * 2006-04-28 2007-11-15 Toshiba Corp 半導体装置の製造方法
CN101673678B (zh) * 2008-09-09 2011-03-16 中芯国际集成电路制造(北京)有限公司 铝层的生长方法及金属-绝缘体-金属板
JP6096013B2 (ja) * 2013-03-15 2017-03-15 旭化成エレクトロニクス株式会社 半導体装置の製造方法および半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055908A (en) * 1987-07-27 1991-10-08 Texas Instruments Incorporated Semiconductor circuit having metallization with TiW
US4970176A (en) * 1989-09-29 1990-11-13 Motorola, Inc. Multiple step metallization process
US5658828A (en) * 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
JPH0464222A (ja) * 1990-07-04 1992-02-28 Fujitsu Ltd 半導体装置の製造方法
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5270255A (en) * 1993-01-08 1993-12-14 Chartered Semiconductor Manufacturing Pte, Ltd. Metallization process for good metal step coverage while maintaining useful alignment mark
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
JPH06260441A (ja) * 1993-03-03 1994-09-16 Nec Corp 半導体装置の製造方法
US5356836A (en) * 1993-08-19 1994-10-18 Industrial Technology Research Institute Aluminum plug process
KR950015602A (ko) * 1993-11-22 1995-06-17 모리시다 요이치 반도체 장치의 제조방법
US5523259A (en) * 1994-12-05 1996-06-04 At&T Corp. Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer
TW298674B (de) * 1995-07-07 1997-02-21 At & T Corp
US5633199A (en) * 1995-11-02 1997-05-27 Motorola Inc. Process for fabricating a metallized interconnect structure in a semiconductor device
US5844318A (en) * 1997-02-18 1998-12-01 Micron Technology, Inc. Aluminum film for semiconductive devices

Also Published As

Publication number Publication date
AU5411498A (en) 1998-07-03
CN1240052A (zh) 1999-12-29
KR20000069433A (ko) 2000-11-25
EP0951066A1 (de) 1999-10-20
JP4226658B2 (ja) 2009-02-18
TW417178B (en) 2001-01-01
DE69736717T2 (de) 2007-09-13
EP0951066A4 (de) 2000-02-23
CN1121711C (zh) 2003-09-17
KR100339670B1 (ko) 2002-06-05
WO1998026450A1 (fr) 1998-06-18
US6162729A (en) 2000-12-19
DE69736717D1 (de) 2006-11-02
EP0951066B1 (de) 2006-09-20

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