ATE382952T1 - Verfahren zur erstellung einer halbleiterscheibe aus integrierten schaltungschips sowie nach diesem verfahren hergestellte vorrichtung - Google Patents

Verfahren zur erstellung einer halbleiterscheibe aus integrierten schaltungschips sowie nach diesem verfahren hergestellte vorrichtung

Info

Publication number
ATE382952T1
ATE382952T1 AT04394026T AT04394026T ATE382952T1 AT E382952 T1 ATE382952 T1 AT E382952T1 AT 04394026 T AT04394026 T AT 04394026T AT 04394026 T AT04394026 T AT 04394026T AT E382952 T1 ATE382952 T1 AT E382952T1
Authority
AT
Austria
Prior art keywords
creating
integrated circuit
neo
wafer
circuit chips
Prior art date
Application number
AT04394026T
Other languages
English (en)
Inventor
Jonathan M Stern
Original Assignee
Irvine Sensors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Irvine Sensors Corp filed Critical Irvine Sensors Corp
Application granted granted Critical
Publication of ATE382952T1 publication Critical patent/ATE382952T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07234—Using a reflow oven
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations

Landscapes

  • Dicing (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT04394026T 2002-11-06 2004-05-12 Verfahren zur erstellung einer halbleiterscheibe aus integrierten schaltungschips sowie nach diesem verfahren hergestellte vorrichtung ATE382952T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US42402502P 2002-11-06 2002-11-06
EP04394026A EP1596433B1 (de) 2002-11-06 2004-05-12 Verfahren zur Erstellung einer Halbleiterscheibe aus integrierten Schaltungschips sowie nach diesem Verfahren hergestellte Vorrichtung

Publications (1)

Publication Number Publication Date
ATE382952T1 true ATE382952T1 (de) 2008-01-15

Family

ID=38670615

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04394026T ATE382952T1 (de) 2002-11-06 2004-05-12 Verfahren zur erstellung einer halbleiterscheibe aus integrierten schaltungschips sowie nach diesem verfahren hergestellte vorrichtung

Country Status (3)

Country Link
US (2) US6998328B2 (de)
EP (1) EP1596433B1 (de)
AT (1) ATE382952T1 (de)

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US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US6998328B2 (en) * 2002-11-06 2006-02-14 Irvine Sensors Corp. Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method
FR2904472B1 (fr) * 2006-07-28 2008-10-31 Microcomposants De Haute Secur Procede de fabrication d'un circuit integre encapsule et circuit integre encapsule associe
KR100789626B1 (ko) * 2006-12-27 2007-12-27 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
DE102007010731A1 (de) * 2007-02-26 2008-08-28 Würth Elektronik GmbH & Co. KG Verfahren zum Einbetten von Chips und Leiterplatte
FR2917234B1 (fr) 2007-06-07 2009-11-06 Commissariat Energie Atomique Dispositif multi composants integres dans une matrice semi-conductrice.
FR2917236B1 (fr) 2007-06-07 2009-10-23 Commissariat Energie Atomique Procede de realisation de via dans un substrat reconstitue.
US7759163B2 (en) * 2008-04-18 2010-07-20 Infineon Technologies Ag Semiconductor module
FR2947948B1 (fr) 2009-07-09 2012-03-09 Commissariat Energie Atomique Plaquette poignee presentant des fenetres de visualisation
DE102012101399B3 (de) * 2012-02-22 2013-08-01 Chih-hao Chen Methode zur umweltfreundlichen Bearbeitung von Substraten
CN106098630A (zh) * 2016-08-09 2016-11-09 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装方法及封装件
CN106409690B (zh) * 2016-09-29 2019-04-30 上海航天电子通讯设备研究所 基于激光纳米加工技术的埋置芯片互连方法
US10163693B1 (en) * 2017-12-21 2018-12-25 Micron Technology, Inc. Methods for processing semiconductor dice and fabricating assemblies incorporating same
US10573547B1 (en) * 2018-11-05 2020-02-25 Honeywell Federal Manufacturing & Technologies, Llc Apparatus and method for facilitating planar delayering of integrated circuit die
CN110211888A (zh) * 2019-06-14 2019-09-06 上海先方半导体有限公司 一种嵌入式扇出封装结构及其制造方法
CN110335852A (zh) * 2019-07-18 2019-10-15 上海先方半导体有限公司 一种扇出封装结构及封装方法
CN112151457A (zh) * 2020-09-22 2020-12-29 维沃移动通信有限公司 封装结构及其制作方法和电子设备
DE102022113643A1 (de) 2022-05-31 2023-11-30 Rolls-Royce Deutschland Ltd & Co Kg Elektrisches Modul

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JP3846094B2 (ja) * 1998-03-17 2006-11-15 株式会社デンソー 半導体装置の製造方法
US6297548B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US6214640B1 (en) * 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US6117704A (en) * 1999-03-31 2000-09-12 Irvine Sensors Corporation Stackable layers containing encapsulated chips
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JP2001144218A (ja) * 1999-11-17 2001-05-25 Sony Corp 半導体装置及び半導体装置の製造方法
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US6998328B2 (en) * 2002-11-06 2006-02-14 Irvine Sensors Corp. Method for creating neo-wafers from singulated integrated circuit die and a device made according to the method

Also Published As

Publication number Publication date
EP1596433A1 (de) 2005-11-16
US6998328B2 (en) 2006-02-14
EP1596433B1 (de) 2008-01-02
US20040140533A1 (en) 2004-07-22
US20060094240A1 (en) 2006-05-04

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