ATE557419T1 - Verfahren zur herstellung eines halbleiterbauelements - Google Patents

Verfahren zur herstellung eines halbleiterbauelements

Info

Publication number
ATE557419T1
ATE557419T1 AT03710424T AT03710424T ATE557419T1 AT E557419 T1 ATE557419 T1 AT E557419T1 AT 03710424 T AT03710424 T AT 03710424T AT 03710424 T AT03710424 T AT 03710424T AT E557419 T1 ATE557419 T1 AT E557419T1
Authority
AT
Austria
Prior art keywords
conductive portion
producing
semiconductor component
insulating layer
depression
Prior art date
Application number
AT03710424T
Other languages
English (en)
Inventor
Ikuya Miyazawa
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of ATE557419T1 publication Critical patent/ATE557419T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
AT03710424T 2002-03-19 2003-03-19 Verfahren zur herstellung eines halbleiterbauelements ATE557419T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002076307 2002-03-19
JP2003007276 2003-01-15
PCT/JP2003/003301 WO2003079430A1 (fr) 2002-03-19 2003-03-19 Dispositif semi-conducteur, procede de fabrication, plaquette de circuit et appareil electronique

Publications (1)

Publication Number Publication Date
ATE557419T1 true ATE557419T1 (de) 2012-05-15

Family

ID=28043774

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03710424T ATE557419T1 (de) 2002-03-19 2003-03-19 Verfahren zur herstellung eines halbleiterbauelements

Country Status (8)

Country Link
US (1) US6841849B2 (de)
EP (1) EP1391923B1 (de)
JP (1) JP4129643B2 (de)
KR (1) KR100512817B1 (de)
CN (1) CN1279605C (de)
AT (1) ATE557419T1 (de)
TW (1) TW594972B (de)
WO (1) WO2003079430A1 (de)

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* Cited by examiner, † Cited by third party
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US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP4110390B2 (ja) 2002-03-19 2008-07-02 セイコーエプソン株式会社 半導体装置の製造方法
JP4081666B2 (ja) * 2002-09-24 2008-04-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004297019A (ja) * 2003-03-28 2004-10-21 Seiko Epson Corp 半導体装置、回路基板及び電子機器
JP3646719B2 (ja) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3646720B2 (ja) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
DE10342559B3 (de) * 2003-09-15 2005-04-14 Infineon Technologies Ag Randstruktur eines Leistungshalbleiterbauelementes und ihr Herstellungsverfahren
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
JP4706180B2 (ja) * 2003-12-22 2011-06-22 セイコーエプソン株式会社 半導体装置の製造方法
JP3698160B2 (ja) * 2004-01-09 2005-09-21 セイコーエプソン株式会社 半導体装置の製造方法
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
JP2005353682A (ja) * 2004-06-08 2005-12-22 Seiko Epson Corp 回路素子の製造方法、電子素子の製造方法、回路基板、電子機器、および電気光学装置
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
TWI250834B (en) * 2004-11-03 2006-03-01 Phoenix Prec Technology Corp Method for fabricating electrical connections of circuit board
JP4170313B2 (ja) * 2005-05-24 2008-10-22 シャープ株式会社 半導体装置の製造方法
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
TWI287273B (en) * 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7714535B2 (en) 2006-07-28 2010-05-11 Semiconductor Energy Laboratory Co., Ltd. Power storage device
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
JP2008166652A (ja) * 2007-01-05 2008-07-17 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
JP4265668B2 (ja) * 2007-03-08 2009-05-20 ソニー株式会社 回路基板の製造方法および回路基板
JP4534096B2 (ja) * 2007-04-12 2010-09-01 ローム株式会社 半導体チップおよびその製造方法、ならびに半導体装置
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
IT1391239B1 (it) 2008-08-08 2011-12-01 Milano Politecnico Metodo per la formazione di bump in substrati con through via
KR101215648B1 (ko) * 2011-02-11 2012-12-26 에스케이하이닉스 주식회사 반도체 칩 및 그 제조방법
US20150262911A1 (en) * 2014-03-14 2015-09-17 International Business Machines Corporation Tsv with end cap, method and 3d integrated circuit
US10804206B2 (en) * 2017-07-31 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench protection

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US117705A (en) * 1871-08-01 Improvement in machines for removing runners from strawberry vines
JPS607148A (ja) * 1983-06-24 1985-01-14 Nec Corp 半導体装置の製造方法
JPS607149A (ja) * 1983-06-24 1985-01-14 Nec Corp 半導体装置の製造方法
JPH0215652A (ja) * 1988-07-01 1990-01-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
DE4314907C1 (de) * 1993-05-05 1994-08-25 Siemens Ag Verfahren zur Herstellung von vertikal miteinander elektrisch leitend kontaktierten Halbleiterbauelementen
EP2270845A3 (de) * 1996-10-29 2013-04-03 Invensas Corporation Integrierte Schaltungen und Verfahren zu ihrer Herstellung
JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
JP3792954B2 (ja) * 1999-08-10 2006-07-05 株式会社東芝 半導体装置の製造方法
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JP3778256B2 (ja) * 2000-02-28 2006-05-24 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2001326325A (ja) * 2000-05-16 2001-11-22 Seiko Epson Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR20040012897A (ko) 2004-02-11
JPWO2003079430A1 (ja) 2005-07-21
TW594972B (en) 2004-06-21
TW200305992A (en) 2003-11-01
EP1391923A1 (de) 2004-02-25
JP4129643B2 (ja) 2008-08-06
CN1533604A (zh) 2004-09-29
WO2003079430A1 (fr) 2003-09-25
KR100512817B1 (ko) 2005-09-06
US20040155330A1 (en) 2004-08-12
US6841849B2 (en) 2005-01-11
EP1391923A4 (de) 2005-06-15
CN1279605C (zh) 2006-10-11
EP1391923B1 (de) 2012-05-09

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