ATE404996T1 - Verfahren zur herstellung von paaren paralleler finfets - Google Patents

Verfahren zur herstellung von paaren paralleler finfets

Info

Publication number
ATE404996T1
ATE404996T1 AT04777432T AT04777432T ATE404996T1 AT E404996 T1 ATE404996 T1 AT E404996T1 AT 04777432 T AT04777432 T AT 04777432T AT 04777432 T AT04777432 T AT 04777432T AT E404996 T1 ATE404996 T1 AT E404996T1
Authority
AT
Austria
Prior art keywords
type
finfet
fin
doping region
impurity doping
Prior art date
Application number
AT04777432T
Other languages
English (en)
Inventor
Andres Bryant
William Clark
David Fried
Mark Jaffe
Edward Nowak
John Pekarik
Christopher Putnam
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE404996T1 publication Critical patent/ATE404996T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
AT04777432T 2003-07-01 2004-06-30 Verfahren zur herstellung von paaren paralleler finfets ATE404996T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/604,206 US6943405B2 (en) 2003-07-01 2003-07-01 Integrated circuit having pairs of parallel complementary FinFETs

Publications (1)

Publication Number Publication Date
ATE404996T1 true ATE404996T1 (de) 2008-08-15

Family

ID=33552188

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04777432T ATE404996T1 (de) 2003-07-01 2004-06-30 Verfahren zur herstellung von paaren paralleler finfets

Country Status (8)

Country Link
US (2) US6943405B2 (de)
EP (1) EP1639648B1 (de)
JP (1) JP5041808B2 (de)
KR (1) KR100792604B1 (de)
CN (1) CN100483734C (de)
AT (1) ATE404996T1 (de)
DE (1) DE602004015793D1 (de)
WO (1) WO2005004206A2 (de)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6924561B1 (en) * 2003-12-08 2005-08-02 Advanced Micro Devices, Inc. SRAM formation using shadow implantation
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US6974983B1 (en) * 2004-02-02 2005-12-13 Advanced Micro Devices, Inc. Isolated FinFET P-channel/N-channel transistor pair
US7253650B2 (en) * 2004-05-25 2007-08-07 International Business Machines Corporation Increase productivity at wafer test using probe retest data analysis
KR100559553B1 (ko) * 2004-07-07 2006-03-10 동부아남반도체 주식회사 반도체 소자의 셸로우 트렌치 소자분리막 제조 방법
CN100364094C (zh) * 2005-01-31 2008-01-23 北京大学 一种FinFET电路与纳机电梁集成的芯片及其制作方法
JP4987244B2 (ja) * 2005-04-28 2012-07-25 株式会社東芝 半導体装置の製造方法
EP1764827A1 (de) * 2005-09-16 2007-03-21 Interuniversitair Microelektronica Centrum ( Imec) Strukturierung mittels rekursiver Spacertechnik
WO2007063990A1 (ja) * 2005-12-02 2007-06-07 Nec Corporation 半導体装置およびその製造方法
US7301210B2 (en) * 2006-01-12 2007-11-27 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing
US7491995B2 (en) * 2006-04-04 2009-02-17 Micron Technology, Inc. DRAM with nanofin transistors
JP2009534783A (ja) * 2006-04-24 2009-09-24 エヌエックスピー ビー ヴィ スタティック・ランダムアクセスメモリ・セル
US8227316B2 (en) * 2006-06-29 2012-07-24 International Business Machines Corporation Method for manufacturing double gate finFET with asymmetric halo
JP4552908B2 (ja) * 2006-07-26 2010-09-29 エルピーダメモリ株式会社 半導体装置の製造方法
CN101536153B (zh) * 2006-11-06 2011-07-20 Nxp股份有限公司 制造fet栅极的方法
US8368144B2 (en) * 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials
US20080283910A1 (en) * 2007-05-15 2008-11-20 Qimonda Ag Integrated circuit and method of forming an integrated circuit
JP4461154B2 (ja) * 2007-05-15 2010-05-12 株式会社東芝 半導体装置
US9088349B2 (en) 2007-06-18 2015-07-21 Digi International Inc. System and method for transmitting and detecting spread spectrum signals
US9088348B2 (en) 2007-06-18 2015-07-21 Digi International Inc. System and method for obtaining frequency and time synchronization in a wideband communication system
KR20090017041A (ko) * 2007-08-13 2009-02-18 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US7710765B2 (en) * 2007-09-27 2010-05-04 Micron Technology, Inc. Back gated SRAM cell
US8111129B2 (en) * 2008-03-12 2012-02-07 International Business Machines Corporation Resistor and design structure having substantially parallel resistor material lengths
US20110018064A1 (en) * 2008-04-04 2011-01-27 Nxp B.V. Sram cell comprising finfets
DE102008030864B4 (de) * 2008-06-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement als Doppelgate- und Tri-Gatetransistor, die auf einem Vollsubstrat aufgebaut sind und Verfahren zur Herstellung des Transistors
US7888192B2 (en) * 2008-11-10 2011-02-15 Texas Instruments Incorporated Process for forming integrated circuits with both split gate and common gate FinFET transistors
JP2011066362A (ja) * 2009-09-18 2011-03-31 Toshiba Corp 半導体装置
US9245805B2 (en) 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
US8021949B2 (en) * 2009-12-01 2011-09-20 International Business Machines Corporation Method and structure for forming finFETs with multiple doping regions on a same chip
KR101105508B1 (ko) * 2009-12-30 2012-01-13 주식회사 하이닉스반도체 반도체 메모리 소자의 제조 방법
US8621398B2 (en) * 2010-05-14 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Automatic layout conversion for FinFET device
US8268689B2 (en) 2010-08-23 2012-09-18 International Business Machines Corporation Multiple threshold voltages in field effect transistor devices
US8524546B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Formation of multi-height MUGFET
US8524545B2 (en) 2010-10-22 2013-09-03 International Business Machines Corporation Simultaneous formation of FinFET and MUGFET
US8445384B2 (en) * 2011-03-15 2013-05-21 International Business Machines Corporation High density six transistor FinFET SRAM cell layout
US8816444B2 (en) * 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9082849B2 (en) 2011-09-30 2015-07-14 The Institute of Microelectronics Chinese Academy of Science Semiconductor structure and method for manufacturing the same
CN103035711B (zh) * 2011-09-30 2016-04-20 中国科学院微电子研究所 一种半导体结构及其制造方法
CN103367152B (zh) * 2012-03-31 2016-05-25 中芯国际集成电路制造(上海)有限公司 半导体器件、鳍式场效应管的形成方法
US8586455B1 (en) 2012-05-15 2013-11-19 International Business Machines Corporation Preventing shorting of adjacent devices
US8927432B2 (en) * 2012-06-14 2015-01-06 International Business Machines Corporation Continuously scalable width and height semiconductor fins
KR102049774B1 (ko) 2013-01-24 2019-11-28 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9083444B2 (en) 2013-03-12 2015-07-14 Digi International Inc. Chirp spread spectrum system and method
US9766321B2 (en) 2013-03-14 2017-09-19 Digi International Inc. Indoor positioning with radio frequency chirp signal propagation delay measurement
US9412601B2 (en) * 2013-03-15 2016-08-09 Infineon Technologies Dresden Gmbh Method for processing a carrier
CN104124160B (zh) * 2013-04-23 2018-03-30 中国科学院微电子研究所 半导体器件制造方法
US9412664B2 (en) 2013-05-06 2016-08-09 International Business Machines Corporation Dual material finFET on single substrate
US9583597B2 (en) * 2013-05-24 2017-02-28 GlobalFoundries, Inc. Asymmetric FinFET semiconductor devices and methods for fabricating the same
US9257427B2 (en) 2013-07-15 2016-02-09 Globalfoundries Inc. Merged tapered finFET
US9704880B2 (en) * 2013-11-06 2017-07-11 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US9633907B2 (en) 2014-05-28 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned nanowire formation using double patterning
US9431383B2 (en) 2014-07-22 2016-08-30 Samsung Electronics Co., Ltd. Integrated circuit, semiconductor device based on integrated circuit, and standard cell library
KR101958421B1 (ko) * 2014-07-22 2019-03-14 삼성전자 주식회사 집적 회로, 상기 집적 회로에 따른 반도체 소자 및 표준 셀 라이브러리
US9536739B2 (en) * 2014-10-28 2017-01-03 International Business Machines Corporation Self-cut sidewall image transfer process
US9437445B1 (en) * 2015-02-24 2016-09-06 International Business Machines Corporation Dual fin integration for electron and hole mobility enhancement
US10879241B2 (en) 2015-09-25 2020-12-29 Intel Corporation Techniques for controlling transistor sub-fin leakage
KR102481480B1 (ko) * 2015-11-13 2022-12-26 삼성전자 주식회사 반도체 소자 및 그 제조 방법
US10256328B2 (en) 2016-05-18 2019-04-09 International Business Machines Corporation Dummy dielectric fins for finFETs with silicon and silicon germanium channels
US9870948B2 (en) 2016-06-09 2018-01-16 International Business Machines Corporation Forming insulator fin structure in isolation region to support gate structures
US9761452B1 (en) * 2016-07-08 2017-09-12 Globalfoundries Inc. Devices and methods of forming SADP on SRAM and SAQP on logic
US10714598B2 (en) 2017-06-30 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor device
CN110945656B (zh) * 2017-08-17 2024-05-24 英特尔公司 晶体管制造中的集成的纳米线及纳米带图案化
CN112840449B (zh) * 2018-10-01 2024-05-07 新加坡优尼山帝斯电子私人有限公司 柱状半导体装置的制造方法
KR102535448B1 (ko) * 2018-12-21 2023-05-26 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 3 차원 반도체 장치의 제조 방법

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
JP2789931B2 (ja) * 1991-05-27 1998-08-27 日本電気株式会社 半導体装置
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
US5372957A (en) * 1993-07-22 1994-12-13 Taiwan Semiconductor Manufacturing Company Multiple tilted angle ion implantation MOSFET method
US6063688A (en) * 1997-09-29 2000-05-16 Intel Corporation Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US6069390A (en) * 1998-01-15 2000-05-30 International Business Machines Corporation Semiconductor integrated circuits with mesas
US6177299B1 (en) * 1998-01-15 2001-01-23 International Business Machines Corporation Transistor having substantially isolated body and method of making the same
US6010934A (en) * 1998-03-02 2000-01-04 Texas Instruments - Acer Incorporated Method of making nanometer Si islands for single electron transistors
US6010933A (en) * 1998-07-17 2000-01-04 Vanguard International Semiconductor Method for making a planarized capacitor-over-bit-line structure for dynamic random access memory (DRAM) devices
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
US6967140B2 (en) * 2000-03-01 2005-11-22 Intel Corporation Quantum wire gate device and method of making same
US6342410B1 (en) * 2000-07-10 2002-01-29 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with three sided gate structure on semiconductor on insulator
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP4044276B2 (ja) * 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6429123B1 (en) * 2000-10-04 2002-08-06 Vanguard International Semiconductor Corporation Method of manufacturing buried metal lines having ultra fine features
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6475890B1 (en) * 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
DE10137575A1 (de) * 2001-07-31 2003-02-27 Infineon Technologies Ag Verfahren zur Erzeugung einer Maske sowie Verfahren zur Herstellung einer Halbleitervorrichtung
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US6800905B2 (en) * 2001-12-14 2004-10-05 International Business Machines Corporation Implanted asymmetric doped polysilicon gate FinFET
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
US6818952B2 (en) * 2002-10-01 2004-11-16 International Business Machines Corporation Damascene gate multi-mesa MOSFET
US6864519B2 (en) * 2002-11-26 2005-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US7074656B2 (en) * 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US6872647B1 (en) * 2003-05-06 2005-03-29 Advanced Micro Devices, Inc. Method for forming multiple fins in a semiconductor device
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7265059B2 (en) * 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Multiple fin formation

Also Published As

Publication number Publication date
US20050272195A1 (en) 2005-12-08
JP2007525015A (ja) 2007-08-30
US6943405B2 (en) 2005-09-13
KR100792604B1 (ko) 2008-01-09
EP1639648A2 (de) 2006-03-29
EP1639648A4 (de) 2007-05-30
CN100483734C (zh) 2009-04-29
US7517806B2 (en) 2009-04-14
EP1639648B1 (de) 2008-08-13
WO2005004206A3 (en) 2005-02-17
CN1846309A (zh) 2006-10-11
US20050001273A1 (en) 2005-01-06
JP5041808B2 (ja) 2012-10-03
DE602004015793D1 (de) 2008-09-25
KR20060031676A (ko) 2006-04-12
WO2005004206A2 (en) 2005-01-13

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