ATE415703T1 - Herstellung von hohlräumen in einer siliziumscheibe - Google Patents

Herstellung von hohlräumen in einer siliziumscheibe

Info

Publication number
ATE415703T1
ATE415703T1 AT03799651T AT03799651T ATE415703T1 AT E415703 T1 ATE415703 T1 AT E415703T1 AT 03799651 T AT03799651 T AT 03799651T AT 03799651 T AT03799651 T AT 03799651T AT E415703 T1 ATE415703 T1 AT E415703T1
Authority
AT
Austria
Prior art keywords
production
cavities
insulation layer
silicon disc
layer
Prior art date
Application number
AT03799651T
Other languages
English (en)
Inventor
Walter Schwarzenbach
Christophe Maleville
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0216409A external-priority patent/FR2849269B1/fr
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE415703T1 publication Critical patent/ATE415703T1/de

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005—Bulk micromachining
    • B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Silicon Compounds (AREA)
  • Thin Film Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
AT03799651T 2002-12-20 2003-12-19 Herstellung von hohlräumen in einer siliziumscheibe ATE415703T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0216409A FR2849269B1 (fr) 2002-12-20 2002-12-20 Procede de realisation de cavites dans une plaque de silicium
US44812403P 2003-02-20 2003-02-20

Publications (1)

Publication Number Publication Date
ATE415703T1 true ATE415703T1 (de) 2008-12-15

Family

ID=32683899

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03799651T ATE415703T1 (de) 2002-12-20 2003-12-19 Herstellung von hohlräumen in einer siliziumscheibe

Country Status (5)

Country Link
EP (1) EP1573802B1 (de)
AT (1) ATE415703T1 (de)
AU (1) AU2003299368A1 (de)
DE (1) DE60324960D1 (de)
WO (1) WO2004059725A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005083775A1 (en) * 2004-02-19 2005-09-09 International Business Machines Corporation FORMATION OF PATTERNED SILICON-ON-INSULATOR (SOI)/SILICON-ON-NOTHING (SON) COMPOSITE STRUCTURE BY POROUS Si ENGINEERING
FR2875947B1 (fr) * 2004-09-30 2007-09-07 Tracit Technologies Nouvelle structure pour microelectronique et microsysteme et procede de realisation
FR2876220B1 (fr) 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
FR2897982B1 (fr) 2006-02-27 2008-07-11 Tracit Technologies Sa Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat
FR3000601B1 (fr) * 2012-12-28 2016-12-09 Commissariat Energie Atomique Procede de formation des espaceurs d'une grille d'un transistor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4956314A (en) * 1989-05-30 1990-09-11 Motorola, Inc. Differential etching of silicon nitride
JPH06132262A (ja) * 1992-10-22 1994-05-13 Hitachi Ltd 薄膜のエッチング方法
FR2700065B1 (fr) * 1992-12-28 1995-02-10 Commissariat Energie Atomique Procédé de fabrication d'accéléromètres utilisant la technologie silicium sur isolant.
US5976945A (en) * 1997-11-20 1999-11-02 Vanguard International Semiconductor Corporation Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
US6335292B1 (en) * 1999-04-15 2002-01-01 Micron Technology, Inc. Method of controlling striations and CD loss in contact oxide etch
FR2795554B1 (fr) * 1999-06-28 2003-08-22 France Telecom Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs

Also Published As

Publication number Publication date
DE60324960D1 (de) 2009-01-08
EP1573802A1 (de) 2005-09-14
WO2004059725A1 (fr) 2004-07-15
AU2003299368A1 (en) 2004-07-22
EP1573802B1 (de) 2008-11-26

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Legal Events

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